1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * motu-protocol-v2.c - a part of driver for MOTU FireWire series 4 * 5 * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp> 6 */ 7 8 #include "motu.h" 9 10 #define V2_CLOCK_STATUS_OFFSET 0x0b14 11 #define V2_CLOCK_RATE_MASK 0x00000038 12 #define V2_CLOCK_RATE_SHIFT 3 13 #define V2_CLOCK_SRC_MASK 0x00000007 14 #define V2_CLOCK_SRC_SHIFT 0 15 #define V2_CLOCK_FETCH_ENABLE 0x02000000 16 #define V2_CLOCK_MODEL_SPECIFIC 0x04000000 17 18 #define V2_IN_OUT_CONF_OFFSET 0x0c04 19 #define V2_OPT_OUT_IFACE_MASK 0x00000c00 20 #define V2_OPT_OUT_IFACE_SHIFT 10 21 #define V2_OPT_IN_IFACE_MASK 0x00000300 22 #define V2_OPT_IN_IFACE_SHIFT 8 23 #define V2_OPT_IFACE_MODE_NONE 0 24 #define V2_OPT_IFACE_MODE_ADAT 1 25 #define V2_OPT_IFACE_MODE_SPDIF 2 26 27 static int get_clock_rate(u32 data, unsigned int *rate) 28 { 29 unsigned int index = (data & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT; 30 if (index >= ARRAY_SIZE(snd_motu_clock_rates)) 31 return -EIO; 32 33 *rate = snd_motu_clock_rates[index]; 34 35 return 0; 36 } 37 38 int snd_motu_protocol_v2_get_clock_rate(struct snd_motu *motu, 39 unsigned int *rate) 40 { 41 __be32 reg; 42 int err; 43 44 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, 45 sizeof(reg)); 46 if (err < 0) 47 return err; 48 49 return get_clock_rate(be32_to_cpu(reg), rate); 50 } 51 52 int snd_motu_protocol_v2_set_clock_rate(struct snd_motu *motu, 53 unsigned int rate) 54 { 55 __be32 reg; 56 u32 data; 57 int i; 58 int err; 59 60 for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) { 61 if (snd_motu_clock_rates[i] == rate) 62 break; 63 } 64 if (i == ARRAY_SIZE(snd_motu_clock_rates)) 65 return -EINVAL; 66 67 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, 68 sizeof(reg)); 69 if (err < 0) 70 return err; 71 data = be32_to_cpu(reg); 72 73 data &= ~V2_CLOCK_RATE_MASK; 74 data |= i << V2_CLOCK_RATE_SHIFT; 75 76 reg = cpu_to_be32(data); 77 return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®, 78 sizeof(reg)); 79 } 80 81 static int get_clock_source(struct snd_motu *motu, u32 data, 82 enum snd_motu_clock_source *src) 83 { 84 unsigned int index = data & V2_CLOCK_SRC_MASK; 85 if (index > 5) 86 return -EIO; 87 88 switch (index) { 89 case 0: 90 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL; 91 break; 92 case 1: 93 { 94 __be32 reg; 95 96 // To check the configuration of optical interface. 97 int err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, 98 ®, sizeof(reg)); 99 if (err < 0) 100 return err; 101 102 if (be32_to_cpu(reg) & 0x00000200) 103 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT; 104 else 105 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT; 106 break; 107 } 108 case 2: 109 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX; 110 break; 111 case 3: 112 *src = SND_MOTU_CLOCK_SOURCE_SPH; 113 break; 114 case 4: 115 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC; 116 break; 117 case 5: 118 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB; 119 break; 120 default: 121 return -EIO; 122 } 123 124 return 0; 125 } 126 127 int snd_motu_protocol_v2_get_clock_source(struct snd_motu *motu, 128 enum snd_motu_clock_source *src) 129 { 130 __be32 reg; 131 int err; 132 133 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, 134 sizeof(reg)); 135 if (err < 0) 136 return err; 137 138 return get_clock_source(motu, be32_to_cpu(reg), src); 139 } 140 141 int snd_motu_protocol_v2_switch_fetching_mode(struct snd_motu *motu, 142 bool enable) 143 { 144 enum snd_motu_clock_source src; 145 __be32 reg; 146 u32 data; 147 int err = 0; 148 149 // 828mkII implements Altera ACEX 1K EP1K30. Nothing to do. 150 if (motu->spec == &snd_motu_spec_828mk2) 151 return 0; 152 153 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, 154 sizeof(reg)); 155 if (err < 0) 156 return err; 157 data = be32_to_cpu(reg); 158 159 err = get_clock_source(motu, data, &src); 160 if (err < 0) 161 return err; 162 163 data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC); 164 if (enable) 165 data |= V2_CLOCK_FETCH_ENABLE; 166 167 if (motu->spec->flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) { 168 // Expected for Traveler and 896HD, which implements Altera 169 // Cyclone EP1C3. 170 data |= V2_CLOCK_MODEL_SPECIFIC; 171 } else { 172 // For UltraLite and 8pre, which implements Xilinx Spartan 173 // XC3S200. 174 unsigned int rate; 175 176 err = get_clock_rate(data, &rate); 177 if (err < 0) 178 return err; 179 180 if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000) 181 data |= V2_CLOCK_MODEL_SPECIFIC; 182 } 183 184 reg = cpu_to_be32(data); 185 return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®, 186 sizeof(reg)); 187 } 188 189 static void calculate_fixed_part(struct snd_motu_packet_format *formats, 190 enum amdtp_stream_direction dir, 191 enum snd_motu_spec_flags flags, 192 unsigned char analog_ports) 193 { 194 unsigned char pcm_chunks[3] = {0, 0, 0}; 195 196 formats->msg_chunks = 2; 197 198 pcm_chunks[0] = analog_ports; 199 pcm_chunks[1] = analog_ports; 200 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 201 pcm_chunks[2] = analog_ports; 202 203 if (dir == AMDTP_IN_STREAM) { 204 if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) { 205 pcm_chunks[0] += 2; 206 pcm_chunks[1] += 2; 207 } 208 if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) { 209 pcm_chunks[0] += 2; 210 pcm_chunks[1] += 2; 211 } 212 } else { 213 if (flags & SND_MOTU_SPEC_RX_SEPARATED_MAIN) { 214 pcm_chunks[0] += 2; 215 pcm_chunks[1] += 2; 216 } 217 218 // Packets to v2 units include 2 chunks for phone 1/2, except 219 // for 176.4/192.0 kHz. 220 pcm_chunks[0] += 2; 221 pcm_chunks[1] += 2; 222 } 223 224 if (flags & SND_MOTU_SPEC_HAS_AESEBU_IFACE) { 225 pcm_chunks[0] += 2; 226 pcm_chunks[1] += 2; 227 } 228 229 /* 230 * All of v2 models have a pair of coaxial interfaces for digital in/out 231 * port. At 44.1/48.0/88.2/96.0 kHz, packets includes PCM from these 232 * ports. 233 */ 234 pcm_chunks[0] += 2; 235 pcm_chunks[1] += 2; 236 237 formats->fixed_part_pcm_chunks[0] = pcm_chunks[0]; 238 formats->fixed_part_pcm_chunks[1] = pcm_chunks[1]; 239 formats->fixed_part_pcm_chunks[2] = pcm_chunks[2]; 240 } 241 242 static void calculate_differed_part(struct snd_motu_packet_format *formats, 243 enum snd_motu_spec_flags flags, 244 u32 data, u32 mask, u32 shift) 245 { 246 unsigned char pcm_chunks[2] = {0, 0}; 247 248 /* 249 * When optical interfaces are configured for S/PDIF (TOSLINK), 250 * the above PCM frames come from them, instead of coaxial 251 * interfaces. 252 */ 253 data = (data & mask) >> shift; 254 if (data == V2_OPT_IFACE_MODE_ADAT) { 255 if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) { 256 pcm_chunks[0] += 8; 257 pcm_chunks[1] += 4; 258 } 259 // 8pre has two sets of optical interface and doesn't reduce 260 // chunks for ADAT signals. 261 if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) { 262 pcm_chunks[1] += 4; 263 } 264 } 265 266 /* At mode x4, no data chunks are supported in this part. */ 267 formats->differed_part_pcm_chunks[0] = pcm_chunks[0]; 268 formats->differed_part_pcm_chunks[1] = pcm_chunks[1]; 269 } 270 271 int snd_motu_protocol_v2_cache_packet_formats(struct snd_motu *motu) 272 { 273 __be32 reg; 274 u32 data; 275 int err; 276 277 err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®, 278 sizeof(reg)); 279 if (err < 0) 280 return err; 281 data = be32_to_cpu(reg); 282 283 calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM, 284 motu->spec->flags, motu->spec->analog_in_ports); 285 calculate_differed_part(&motu->tx_packet_formats, motu->spec->flags, 286 data, V2_OPT_IN_IFACE_MASK, V2_OPT_IN_IFACE_SHIFT); 287 288 calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM, 289 motu->spec->flags, motu->spec->analog_out_ports); 290 calculate_differed_part(&motu->rx_packet_formats, motu->spec->flags, 291 data, V2_OPT_OUT_IFACE_MASK, V2_OPT_OUT_IFACE_SHIFT); 292 293 motu->tx_packet_formats.pcm_byte_offset = 10; 294 motu->rx_packet_formats.pcm_byte_offset = 10; 295 296 return 0; 297 } 298 299 const struct snd_motu_spec snd_motu_spec_828mk2 = { 300 .name = "828mk2", 301 .protocol_version = SND_MOTU_PROTOCOL_V2, 302 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 303 SND_MOTU_SPEC_TX_MICINST_CHUNK | 304 SND_MOTU_SPEC_TX_RETURN_CHUNK | 305 SND_MOTU_SPEC_RX_SEPARATED_MAIN | 306 SND_MOTU_SPEC_HAS_OPT_IFACE_A | 307 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 308 SND_MOTU_SPEC_TX_MIDI_2ND_Q, 309 310 .analog_in_ports = 8, 311 .analog_out_ports = 8, 312 }; 313 314 const struct snd_motu_spec snd_motu_spec_traveler = { 315 .name = "Traveler", 316 .protocol_version = SND_MOTU_PROTOCOL_V2, 317 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 318 SND_MOTU_SPEC_SUPPORT_CLOCK_X4 | 319 SND_MOTU_SPEC_TX_RETURN_CHUNK | 320 SND_MOTU_SPEC_HAS_AESEBU_IFACE | 321 SND_MOTU_SPEC_HAS_OPT_IFACE_A | 322 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 323 SND_MOTU_SPEC_TX_MIDI_2ND_Q, 324 325 .analog_in_ports = 8, 326 .analog_out_ports = 8, 327 }; 328 329 const struct snd_motu_spec snd_motu_spec_ultralite = { 330 .name = "UltraLite", 331 .protocol_version = SND_MOTU_PROTOCOL_V2, 332 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 333 SND_MOTU_SPEC_TX_MICINST_CHUNK | // padding. 334 SND_MOTU_SPEC_TX_RETURN_CHUNK | 335 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 336 SND_MOTU_SPEC_TX_MIDI_2ND_Q | 337 SND_MOTU_SPEC_RX_SEPARATED_MAIN, 338 .analog_in_ports = 8, 339 .analog_out_ports = 8, 340 }; 341 342 const struct snd_motu_spec snd_motu_spec_8pre = { 343 .name = "8pre", 344 .protocol_version = SND_MOTU_PROTOCOL_V2, 345 // In tx, use coax chunks for mix-return 1/2. In rx, use coax chunks for 346 // dummy 1/2. 347 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 348 SND_MOTU_SPEC_HAS_OPT_IFACE_A | 349 SND_MOTU_SPEC_HAS_OPT_IFACE_B | 350 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 351 SND_MOTU_SPEC_TX_MIDI_2ND_Q, 352 .analog_in_ports = 8, 353 .analog_out_ports = 2, 354 }; 355