1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * motu-protocol-v2.c - a part of driver for MOTU FireWire series 4 * 5 * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp> 6 */ 7 8 #include "motu.h" 9 10 #define V2_CLOCK_STATUS_OFFSET 0x0b14 11 #define V2_CLOCK_RATE_MASK 0x00000038 12 #define V2_CLOCK_RATE_SHIFT 3 13 #define V2_CLOCK_SRC_MASK 0x00000007 14 #define V2_CLOCK_SRC_SHIFT 0 15 #define V2_CLOCK_FETCH_ENABLE 0x02000000 16 #define V2_CLOCK_MODEL_SPECIFIC 0x04000000 17 18 #define V2_IN_OUT_CONF_OFFSET 0x0c04 19 #define V2_OPT_OUT_IFACE_MASK 0x00000c00 20 #define V2_OPT_OUT_IFACE_SHIFT 10 21 #define V2_OPT_IN_IFACE_MASK 0x00000300 22 #define V2_OPT_IN_IFACE_SHIFT 8 23 #define V2_OPT_IFACE_MODE_NONE 0 24 #define V2_OPT_IFACE_MODE_ADAT 1 25 #define V2_OPT_IFACE_MODE_SPDIF 2 26 27 static int get_clock_rate(u32 data, unsigned int *rate) 28 { 29 unsigned int index = (data & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT; 30 if (index >= ARRAY_SIZE(snd_motu_clock_rates)) 31 return -EIO; 32 33 *rate = snd_motu_clock_rates[index]; 34 35 return 0; 36 } 37 38 int snd_motu_protocol_v2_get_clock_rate(struct snd_motu *motu, 39 unsigned int *rate) 40 { 41 __be32 reg; 42 int err; 43 44 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, 45 sizeof(reg)); 46 if (err < 0) 47 return err; 48 49 return get_clock_rate(be32_to_cpu(reg), rate); 50 } 51 52 int snd_motu_protocol_v2_set_clock_rate(struct snd_motu *motu, 53 unsigned int rate) 54 { 55 __be32 reg; 56 u32 data; 57 int i; 58 int err; 59 60 for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) { 61 if (snd_motu_clock_rates[i] == rate) 62 break; 63 } 64 if (i == ARRAY_SIZE(snd_motu_clock_rates)) 65 return -EINVAL; 66 67 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, 68 sizeof(reg)); 69 if (err < 0) 70 return err; 71 data = be32_to_cpu(reg); 72 73 data &= ~V2_CLOCK_RATE_MASK; 74 data |= i << V2_CLOCK_RATE_SHIFT; 75 76 reg = cpu_to_be32(data); 77 return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®, 78 sizeof(reg)); 79 } 80 81 static int get_clock_source(struct snd_motu *motu, u32 data, 82 enum snd_motu_clock_source *src) 83 { 84 unsigned int index = data & V2_CLOCK_SRC_MASK; 85 if (index > 5) 86 return -EIO; 87 88 switch (index) { 89 case 0: 90 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL; 91 break; 92 case 1: 93 { 94 __be32 reg; 95 96 // To check the configuration of optical interface. 97 int err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, 98 ®, sizeof(reg)); 99 if (err < 0) 100 return err; 101 102 if (be32_to_cpu(reg) & 0x00000200) 103 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT; 104 else 105 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT; 106 break; 107 } 108 case 2: 109 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX; 110 break; 111 case 3: 112 *src = SND_MOTU_CLOCK_SOURCE_SPH; 113 break; 114 case 4: 115 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC; 116 break; 117 case 5: 118 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB; 119 break; 120 default: 121 return -EIO; 122 } 123 124 return 0; 125 } 126 127 int snd_motu_protocol_v2_get_clock_source(struct snd_motu *motu, 128 enum snd_motu_clock_source *src) 129 { 130 __be32 reg; 131 int err; 132 133 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, 134 sizeof(reg)); 135 if (err < 0) 136 return err; 137 138 return get_clock_source(motu, be32_to_cpu(reg), src); 139 } 140 141 int snd_motu_protocol_v2_switch_fetching_mode(struct snd_motu *motu, 142 bool enable) 143 { 144 enum snd_motu_clock_source src; 145 __be32 reg; 146 u32 data; 147 int err = 0; 148 149 // 828mkII implements Altera ACEX 1K EP1K30. Nothing to do. 150 if (motu->spec == &snd_motu_spec_828mk2) 151 return 0; 152 153 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, 154 sizeof(reg)); 155 if (err < 0) 156 return err; 157 data = be32_to_cpu(reg); 158 159 err = get_clock_source(motu, data, &src); 160 if (err < 0) 161 return err; 162 163 data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC); 164 if (enable) 165 data |= V2_CLOCK_FETCH_ENABLE; 166 167 if (motu->spec == &snd_motu_spec_traveler) { 168 // Expected for Traveler and 896HD, which implements Altera 169 // Cyclone EP1C3. 170 data |= V2_CLOCK_MODEL_SPECIFIC; 171 } else { 172 // For UltraLite and 8pre, which implements Xilinx Spartan 173 // XC3S200. 174 unsigned int rate; 175 176 err = get_clock_rate(data, &rate); 177 if (err < 0) 178 return err; 179 180 if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000) 181 data |= V2_CLOCK_MODEL_SPECIFIC; 182 } 183 184 reg = cpu_to_be32(data); 185 return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®, 186 sizeof(reg)); 187 } 188 189 static void calculate_fixed_part(struct snd_motu_packet_format *formats, 190 enum amdtp_stream_direction dir, 191 enum snd_motu_spec_flags flags, 192 unsigned char analog_ports) 193 { 194 unsigned char pcm_chunks[3] = {0, 0, 0}; 195 196 pcm_chunks[0] = analog_ports; 197 pcm_chunks[1] = analog_ports; 198 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 199 pcm_chunks[2] = analog_ports; 200 201 if (dir == AMDTP_IN_STREAM) { 202 if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) { 203 pcm_chunks[0] += 2; 204 pcm_chunks[1] += 2; 205 } 206 if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) { 207 pcm_chunks[0] += 2; 208 pcm_chunks[1] += 2; 209 } 210 } else { 211 if (flags & SND_MOTU_SPEC_RX_SEPARATED_MAIN) { 212 pcm_chunks[0] += 2; 213 pcm_chunks[1] += 2; 214 } 215 216 // Packets to v2 units include 2 chunks for phone 1/2, except 217 // for 176.4/192.0 kHz. 218 pcm_chunks[0] += 2; 219 pcm_chunks[1] += 2; 220 } 221 222 if (flags & SND_MOTU_SPEC_HAS_AESEBU_IFACE) { 223 pcm_chunks[0] += 2; 224 pcm_chunks[1] += 2; 225 } 226 227 /* 228 * All of v2 models have a pair of coaxial interfaces for digital in/out 229 * port. At 44.1/48.0/88.2/96.0 kHz, packets includes PCM from these 230 * ports. 231 */ 232 pcm_chunks[0] += 2; 233 pcm_chunks[1] += 2; 234 235 formats->fixed_part_pcm_chunks[0] = pcm_chunks[0]; 236 formats->fixed_part_pcm_chunks[1] = pcm_chunks[1]; 237 formats->fixed_part_pcm_chunks[2] = pcm_chunks[2]; 238 } 239 240 static void calculate_differed_part(struct snd_motu_packet_format *formats, 241 enum snd_motu_spec_flags flags, 242 u32 data, u32 mask, u32 shift) 243 { 244 unsigned char pcm_chunks[2] = {0, 0}; 245 246 /* 247 * When optical interfaces are configured for S/PDIF (TOSLINK), 248 * the above PCM frames come from them, instead of coaxial 249 * interfaces. 250 */ 251 data = (data & mask) >> shift; 252 if (data == V2_OPT_IFACE_MODE_ADAT) { 253 if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) { 254 pcm_chunks[0] += 8; 255 pcm_chunks[1] += 4; 256 } 257 // 8pre has two sets of optical interface and doesn't reduce 258 // chunks for ADAT signals. 259 if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) { 260 pcm_chunks[1] += 4; 261 } 262 } 263 264 /* At mode x4, no data chunks are supported in this part. */ 265 formats->differed_part_pcm_chunks[0] = pcm_chunks[0]; 266 formats->differed_part_pcm_chunks[1] = pcm_chunks[1]; 267 } 268 269 static int detect_packet_formats_828mk2(struct snd_motu *motu, u32 data) 270 { 271 if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) == 272 V2_OPT_IFACE_MODE_ADAT) { 273 motu->tx_packet_formats.pcm_chunks[0] += 8; 274 motu->tx_packet_formats.pcm_chunks[1] += 4; 275 } 276 277 if (((data & V2_OPT_OUT_IFACE_MASK) >> V2_OPT_OUT_IFACE_SHIFT) == 278 V2_OPT_IFACE_MODE_ADAT) { 279 motu->rx_packet_formats.pcm_chunks[0] += 8; 280 motu->rx_packet_formats.pcm_chunks[1] += 4; 281 } 282 283 return 0; 284 } 285 286 static int detect_packet_formats_traveler(struct snd_motu *motu, u32 data) 287 { 288 if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) == 289 V2_OPT_IFACE_MODE_ADAT) { 290 motu->tx_packet_formats.pcm_chunks[0] += 8; 291 motu->tx_packet_formats.pcm_chunks[1] += 4; 292 } 293 294 if (((data & V2_OPT_OUT_IFACE_MASK) >> V2_OPT_OUT_IFACE_SHIFT) == 295 V2_OPT_IFACE_MODE_ADAT) { 296 motu->rx_packet_formats.pcm_chunks[0] += 8; 297 motu->rx_packet_formats.pcm_chunks[1] += 4; 298 } 299 300 return 0; 301 } 302 303 static int detect_packet_formats_8pre(struct snd_motu *motu, u32 data) 304 { 305 if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) == 306 V2_OPT_IFACE_MODE_ADAT) { 307 motu->tx_packet_formats.pcm_chunks[0] += 8; 308 motu->tx_packet_formats.pcm_chunks[1] += 8; 309 } 310 311 if (((data & V2_OPT_OUT_IFACE_MASK) >> V2_OPT_OUT_IFACE_SHIFT) == 312 V2_OPT_IFACE_MODE_ADAT) { 313 motu->rx_packet_formats.pcm_chunks[0] += 8; 314 motu->rx_packet_formats.pcm_chunks[1] += 8; 315 } 316 317 return 0; 318 } 319 320 int snd_motu_protocol_v2_cache_packet_formats(struct snd_motu *motu) 321 { 322 __be32 reg; 323 u32 data; 324 int err; 325 326 motu->tx_packet_formats.pcm_byte_offset = 10; 327 motu->rx_packet_formats.pcm_byte_offset = 10; 328 329 motu->tx_packet_formats.msg_chunks = 2; 330 motu->rx_packet_formats.msg_chunks = 2; 331 332 err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®, 333 sizeof(reg)); 334 if (err < 0) 335 return err; 336 data = be32_to_cpu(reg); 337 338 calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM, 339 motu->spec->flags, motu->spec->analog_in_ports); 340 calculate_differed_part(&motu->tx_packet_formats, motu->spec->flags, 341 data, V2_OPT_IN_IFACE_MASK, V2_OPT_IN_IFACE_SHIFT); 342 343 calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM, 344 motu->spec->flags, motu->spec->analog_out_ports); 345 calculate_differed_part(&motu->rx_packet_formats, motu->spec->flags, 346 data, V2_OPT_OUT_IFACE_MASK, V2_OPT_OUT_IFACE_SHIFT); 347 348 349 if (motu->spec == &snd_motu_spec_828mk2) 350 return detect_packet_formats_828mk2(motu, data); 351 else if (motu->spec == &snd_motu_spec_traveler) 352 return detect_packet_formats_traveler(motu, data); 353 else if (motu->spec == &snd_motu_spec_8pre) 354 return detect_packet_formats_8pre(motu, data); 355 else 356 return 0; 357 } 358 359 const struct snd_motu_spec snd_motu_spec_828mk2 = { 360 .name = "828mk2", 361 .protocol_version = SND_MOTU_PROTOCOL_V2, 362 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 363 SND_MOTU_SPEC_TX_MICINST_CHUNK | 364 SND_MOTU_SPEC_TX_RETURN_CHUNK | 365 SND_MOTU_SPEC_RX_SEPARATED_MAIN | 366 SND_MOTU_SPEC_HAS_OPT_IFACE_A | 367 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 368 SND_MOTU_SPEC_TX_MIDI_2ND_Q, 369 .tx_fixed_pcm_chunks = {14, 14, 0}, 370 .rx_fixed_pcm_chunks = {14, 14, 0}, 371 .analog_in_ports = 8, 372 .analog_out_ports = 8, 373 }; 374 375 const struct snd_motu_spec snd_motu_spec_traveler = { 376 .name = "Traveler", 377 .protocol_version = SND_MOTU_PROTOCOL_V2, 378 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 379 SND_MOTU_SPEC_SUPPORT_CLOCK_X4 | 380 SND_MOTU_SPEC_TX_RETURN_CHUNK | 381 SND_MOTU_SPEC_HAS_AESEBU_IFACE | 382 SND_MOTU_SPEC_HAS_OPT_IFACE_A | 383 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 384 SND_MOTU_SPEC_TX_MIDI_2ND_Q, 385 .tx_fixed_pcm_chunks = {14, 14, 8}, 386 .rx_fixed_pcm_chunks = {14, 14, 8}, 387 .analog_in_ports = 8, 388 .analog_out_ports = 8, 389 }; 390 391 const struct snd_motu_spec snd_motu_spec_ultralite = { 392 .name = "UltraLite", 393 .protocol_version = SND_MOTU_PROTOCOL_V2, 394 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 395 SND_MOTU_SPEC_TX_MICINST_CHUNK | // padding. 396 SND_MOTU_SPEC_TX_RETURN_CHUNK | 397 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 398 SND_MOTU_SPEC_TX_MIDI_2ND_Q | 399 SND_MOTU_SPEC_RX_SEPARATED_MAIN, 400 .tx_fixed_pcm_chunks = {14, 14, 0}, 401 .rx_fixed_pcm_chunks = {14, 14, 0}, 402 .analog_in_ports = 8, 403 .analog_out_ports = 8, 404 }; 405 406 const struct snd_motu_spec snd_motu_spec_8pre = { 407 .name = "8pre", 408 .protocol_version = SND_MOTU_PROTOCOL_V2, 409 // In tx, use coax chunks for mix-return 1/2. In rx, use coax chunks for 410 // dummy 1/2. 411 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 412 SND_MOTU_SPEC_HAS_OPT_IFACE_A | 413 SND_MOTU_SPEC_HAS_OPT_IFACE_B | 414 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 415 SND_MOTU_SPEC_TX_MIDI_2ND_Q, 416 .tx_fixed_pcm_chunks = {10, 6, 0}, 417 .rx_fixed_pcm_chunks = {10, 6, 0}, 418 .analog_in_ports = 8, 419 .analog_out_ports = 2, 420 }; 421