1 // SPDX-License-Identifier: GPL-2.0
2 // ff-protocol-former.c - a part of driver for RME Fireface series
3 //
4 // Copyright (c) 2019 Takashi Sakamoto
5 //
6 // Licensed under the terms of the GNU General Public License, version 2.
7 
8 #include <linux/delay.h>
9 
10 #include "ff.h"
11 
12 #define FORMER_REG_SYNC_STATUS		0x0000801c0000ull
13 /* For block write request. */
14 #define FORMER_REG_FETCH_PCM_FRAMES	0x0000801c0000ull
15 #define FORMER_REG_CLOCK_CONFIG		0x0000801c0004ull
16 
17 static int parse_clock_bits(u32 data, unsigned int *rate,
18 			    enum snd_ff_clock_src *src)
19 {
20 	static const struct {
21 		unsigned int rate;
22 		u32 mask;
23 	} *rate_entry, rate_entries[] = {
24 		{  32000, 0x00000002, },
25 		{  44100, 0x00000000, },
26 		{  48000, 0x00000006, },
27 		{  64000, 0x0000000a, },
28 		{  88200, 0x00000008, },
29 		{  96000, 0x0000000e, },
30 		{ 128000, 0x00000012, },
31 		{ 176400, 0x00000010, },
32 		{ 192000, 0x00000016, },
33 	};
34 	static const struct {
35 		enum snd_ff_clock_src src;
36 		u32 mask;
37 	} *clk_entry, clk_entries[] = {
38 		{ SND_FF_CLOCK_SRC_ADAT1,	0x00000000, },
39 		{ SND_FF_CLOCK_SRC_ADAT2,	0x00000400, },
40 		{ SND_FF_CLOCK_SRC_SPDIF,	0x00000c00, },
41 		{ SND_FF_CLOCK_SRC_WORD,	0x00001000, },
42 		{ SND_FF_CLOCK_SRC_LTC,		0x00001800, },
43 	};
44 	int i;
45 
46 	for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
47 		rate_entry = rate_entries + i;
48 		if ((data & 0x0000001e) == rate_entry->mask) {
49 			*rate = rate_entry->rate;
50 			break;
51 		}
52 	}
53 	if (i == ARRAY_SIZE(rate_entries))
54 		return -EIO;
55 
56 	if (data & 0x00000001) {
57 		*src = SND_FF_CLOCK_SRC_INTERNAL;
58 	} else {
59 		for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
60 			clk_entry = clk_entries + i;
61 			if ((data & 0x00001c00) == clk_entry->mask) {
62 				*src = clk_entry->src;
63 				break;
64 			}
65 		}
66 		if (i == ARRAY_SIZE(clk_entries))
67 			return -EIO;
68 	}
69 
70 	return 0;
71 }
72 
73 static int former_get_clock(struct snd_ff *ff, unsigned int *rate,
74 			    enum snd_ff_clock_src *src)
75 {
76 	__le32 reg;
77 	u32 data;
78 	int err;
79 
80 	err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
81 				 FORMER_REG_CLOCK_CONFIG, &reg, sizeof(reg), 0);
82 	if (err < 0)
83 		return err;
84 	data = le32_to_cpu(reg);
85 
86 	return parse_clock_bits(data, rate, src);
87 }
88 
89 static int former_switch_fetching_mode(struct snd_ff *ff, bool enable)
90 {
91 	unsigned int count;
92 	__le32 *reg;
93 	int i;
94 	int err;
95 
96 	count = 0;
97 	for (i = 0; i < SND_FF_STREAM_MODE_COUNT; ++i)
98 		count = max(count, ff->spec->pcm_playback_channels[i]);
99 
100 	reg = kcalloc(count, sizeof(__le32), GFP_KERNEL);
101 	if (!reg)
102 		return -ENOMEM;
103 
104 	if (!enable) {
105 		/*
106 		 * Each quadlet is corresponding to data channels in a data
107 		 * blocks in reverse order. Precisely, quadlets for available
108 		 * data channels should be enabled. Here, I take second best
109 		 * to fetch PCM frames from all of data channels regardless of
110 		 * stf.
111 		 */
112 		for (i = 0; i < count; ++i)
113 			reg[i] = cpu_to_le32(0x00000001);
114 	}
115 
116 	err = snd_fw_transaction(ff->unit, TCODE_WRITE_BLOCK_REQUEST,
117 				 FORMER_REG_FETCH_PCM_FRAMES, reg,
118 				 sizeof(__le32) * count, 0);
119 	kfree(reg);
120 	return err;
121 }
122 
123 static void dump_clock_config(struct snd_ff *ff, struct snd_info_buffer *buffer)
124 {
125 	__le32 reg;
126 	u32 data;
127 	unsigned int rate;
128 	enum snd_ff_clock_src src;
129 	const char *label;
130 	int err;
131 
132 	err = snd_fw_transaction(ff->unit, TCODE_READ_BLOCK_REQUEST,
133 				 FORMER_REG_CLOCK_CONFIG, &reg, sizeof(reg), 0);
134 	if (err < 0)
135 		return;
136 	data = le32_to_cpu(reg);
137 
138 	snd_iprintf(buffer, "Output S/PDIF format: %s (Emphasis: %s)\n",
139 		    (data & 0x00000020) ? "Professional" : "Consumer",
140 		    (data & 0x00000040) ? "on" : "off");
141 
142 	snd_iprintf(buffer, "Optical output interface format: %s\n",
143 		    (data & 0x00000100) ? "S/PDIF" : "ADAT");
144 
145 	snd_iprintf(buffer, "Word output single speed: %s\n",
146 		    (data & 0x00002000) ? "on" : "off");
147 
148 	snd_iprintf(buffer, "S/PDIF input interface: %s\n",
149 		    (data & 0x00000200) ? "Optical" : "Coaxial");
150 
151 	err = parse_clock_bits(data, &rate, &src);
152 	if (err < 0)
153 		return;
154 	label = snd_ff_proc_get_clk_label(src);
155 	if (!label)
156 		return;
157 
158 	snd_iprintf(buffer, "Clock configuration: %d %s\n", rate, label);
159 }
160 
161 static void dump_sync_status(struct snd_ff *ff, struct snd_info_buffer *buffer)
162 {
163 	static const struct {
164 		char *const label;
165 		u32 locked_mask;
166 		u32 synced_mask;
167 	} *clk_entry, clk_entries[] = {
168 		{ "WDClk",	0x40000000, 0x20000000, },
169 		{ "S/PDIF",	0x00080000, 0x00040000, },
170 		{ "ADAT1",	0x00000400, 0x00001000, },
171 		{ "ADAT2",	0x00000800, 0x00002000, },
172 	};
173 	static const struct {
174 		char *const label;
175 		u32 mask;
176 	} *referred_entry, referred_entries[] = {
177 		{ "ADAT1",	0x00000000, },
178 		{ "ADAT2",	0x00400000, },
179 		{ "S/PDIF",	0x00c00000, },
180 		{ "WDclk",	0x01000000, },
181 		{ "TCO",	0x01400000, },
182 	};
183 	static const struct {
184 		unsigned int rate;
185 		u32 mask;
186 	} *rate_entry, rate_entries[] = {
187 		{ 32000,	0x02000000, },
188 		{ 44100,	0x04000000, },
189 		{ 48000,	0x06000000, },
190 		{ 64000,	0x08000000, },
191 		{ 88200,	0x0a000000, },
192 		{ 96000,	0x0c000000, },
193 		{ 128000,	0x0e000000, },
194 		{ 176400,	0x10000000, },
195 		{ 192000,	0x12000000, },
196 	};
197 	__le32 reg[2];
198 	u32 data[2];
199 	int i;
200 	int err;
201 
202 	err = snd_fw_transaction(ff->unit, TCODE_READ_BLOCK_REQUEST,
203 				 FORMER_REG_SYNC_STATUS, reg, sizeof(reg), 0);
204 	if (err < 0)
205 		return;
206 	data[0] = le32_to_cpu(reg[0]);
207 	data[1] = le32_to_cpu(reg[1]);
208 
209 	snd_iprintf(buffer, "External source detection:\n");
210 
211 	for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
212 		const char *state;
213 
214 		clk_entry = clk_entries + i;
215 		if (data[0] & clk_entry->locked_mask) {
216 			if (data[0] & clk_entry->synced_mask)
217 				state = "sync";
218 			else
219 				state = "lock";
220 		} else {
221 			state = "none";
222 		}
223 
224 		snd_iprintf(buffer, "%s: %s\n", clk_entry->label, state);
225 	}
226 
227 	snd_iprintf(buffer, "Referred clock:\n");
228 
229 	if (data[1] & 0x00000001) {
230 		snd_iprintf(buffer, "Internal\n");
231 	} else {
232 		unsigned int rate;
233 		const char *label;
234 
235 		for (i = 0; i < ARRAY_SIZE(referred_entries); ++i) {
236 			referred_entry = referred_entries + i;
237 			if ((data[0] & 0x1e0000) == referred_entry->mask) {
238 				label = referred_entry->label;
239 				break;
240 			}
241 		}
242 		if (i == ARRAY_SIZE(referred_entries))
243 			label = "none";
244 
245 		for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
246 			rate_entry = rate_entries + i;
247 			if ((data[0] & 0x1e000000) == rate_entry->mask) {
248 				rate = rate_entry->rate;
249 				break;
250 			}
251 		}
252 		if (i == ARRAY_SIZE(rate_entries))
253 			rate = 0;
254 
255 		snd_iprintf(buffer, "%s %d\n", label, rate);
256 	}
257 }
258 
259 static void former_dump_status(struct snd_ff *ff,
260 			       struct snd_info_buffer *buffer)
261 {
262 	dump_clock_config(ff, buffer);
263 	dump_sync_status(ff, buffer);
264 }
265 
266 static int former_fill_midi_msg(struct snd_ff *ff,
267 				struct snd_rawmidi_substream *substream,
268 				unsigned int port)
269 {
270 	u8 *buf = (u8 *)ff->msg_buf[port];
271 	int len;
272 	int i;
273 
274 	len = snd_rawmidi_transmit_peek(substream, buf,
275 					SND_FF_MAXIMIM_MIDI_QUADS);
276 	if (len <= 0)
277 		return len;
278 
279 	// One quadlet includes one byte.
280 	for (i = len - 1; i >= 0; --i)
281 		ff->msg_buf[port][i] = cpu_to_le32(buf[i]);
282 	ff->rx_bytes[port] = len;
283 
284 	return len;
285 }
286 
287 #define FF800_STF		0x0000fc88f000
288 #define FF800_RX_PACKET_FORMAT	0x0000fc88f004
289 #define FF800_ALLOC_TX_STREAM	0x0000fc88f008
290 #define FF800_ISOC_COMM_START	0x0000fc88f00c
291 #define   FF800_TX_S800_FLAG	0x00000800
292 #define FF800_ISOC_COMM_STOP	0x0000fc88f010
293 
294 #define FF800_TX_PACKET_ISOC_CH	0x0000801c0008
295 
296 static int allocate_rx_resources(struct snd_ff *ff)
297 {
298 	u32 data;
299 	__le32 reg;
300 	int err;
301 
302 	// Controllers should allocate isochronous resources for rx stream.
303 	err = fw_iso_resources_allocate(&ff->rx_resources,
304 				amdtp_stream_get_max_payload(&ff->rx_stream),
305 				fw_parent_device(ff->unit)->max_speed);
306 	if (err < 0)
307 		return err;
308 
309 	// Set isochronous channel and the number of quadlets of rx packets.
310 	data = ff->rx_stream.data_block_quadlets << 3;
311 	data = (data << 8) | ff->rx_resources.channel;
312 	reg = cpu_to_le32(data);
313 	return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
314 				FF800_RX_PACKET_FORMAT, &reg, sizeof(reg), 0);
315 }
316 
317 static int allocate_tx_resources(struct snd_ff *ff)
318 {
319 	__le32 reg;
320 	unsigned int count;
321 	unsigned int tx_isoc_channel;
322 	int err;
323 
324 	reg = cpu_to_le32(ff->tx_stream.data_block_quadlets);
325 	err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
326 				 FF800_ALLOC_TX_STREAM, &reg, sizeof(reg), 0);
327 	if (err < 0)
328 		return err;
329 
330 	// Wait till the format of tx packet is available.
331 	count = 0;
332 	while (count++ < 10) {
333 		u32 data;
334 		err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
335 				FF800_TX_PACKET_ISOC_CH, &reg, sizeof(reg), 0);
336 		if (err < 0)
337 			return err;
338 
339 		data = le32_to_cpu(reg);
340 		if (data != 0xffffffff) {
341 			tx_isoc_channel = data;
342 			break;
343 		}
344 
345 		msleep(50);
346 	}
347 	if (count >= 10)
348 		return -ETIMEDOUT;
349 
350 	// NOTE: this is a makeshift to start OHCI 1394 IR context in the
351 	// channel. On the other hand, 'struct fw_iso_resources.allocated' is
352 	// not true and it's not deallocated at stop.
353 	ff->tx_resources.channel = tx_isoc_channel;
354 
355 	return 0;
356 }
357 
358 static int ff800_begin_session(struct snd_ff *ff, unsigned int rate)
359 {
360 	__le32 reg;
361 	int err;
362 
363 	reg = cpu_to_le32(rate);
364 	err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
365 				 FF800_STF, &reg, sizeof(reg), 0);
366 	if (err < 0)
367 		return err;
368 
369 	// If starting isochronous communication immediately, change of STF has
370 	// no effect. In this case, the communication runs based on former STF.
371 	// Let's sleep for a bit.
372 	msleep(100);
373 
374 	err = allocate_rx_resources(ff);
375 	if (err < 0)
376 		return err;
377 
378 	err = allocate_tx_resources(ff);
379 	if (err < 0)
380 		return err;
381 
382 	reg = cpu_to_le32(0x80000000);
383 	reg |= cpu_to_le32(ff->tx_stream.data_block_quadlets);
384 	if (fw_parent_device(ff->unit)->max_speed == SCODE_800)
385 		reg |= cpu_to_le32(FF800_TX_S800_FLAG);
386 	return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
387 				 FF800_ISOC_COMM_START, &reg, sizeof(reg), 0);
388 }
389 
390 static void ff800_finish_session(struct snd_ff *ff)
391 {
392 	__le32 reg;
393 
394 	reg = cpu_to_le32(0x80000000);
395 	snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
396 			   FF800_ISOC_COMM_STOP, &reg, sizeof(reg), 0);
397 }
398 
399 // Fireface 800 doesn't allow drivers to register lower 4 bytes of destination
400 // address.
401 // A write transaction to clear registered higher 4 bytes of destination address
402 // has an effect to suppress asynchronous transaction from device.
403 static void ff800_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
404 				  __le32 *buf, size_t length)
405 {
406 	int i;
407 
408 	for (i = 0; i < length / 4; i++) {
409 		u8 byte = le32_to_cpu(buf[i]) & 0xff;
410 		struct snd_rawmidi_substream *substream;
411 
412 		substream = READ_ONCE(ff->tx_midi_substreams[0]);
413 		if (substream)
414 			snd_rawmidi_receive(substream, &byte, 1);
415 	}
416 }
417 
418 const struct snd_ff_protocol snd_ff_protocol_ff800 = {
419 	.handle_midi_msg	= ff800_handle_midi_msg,
420 	.fill_midi_msg		= former_fill_midi_msg,
421 	.get_clock		= former_get_clock,
422 	.switch_fetching_mode	= former_switch_fetching_mode,
423 	.begin_session		= ff800_begin_session,
424 	.finish_session		= ff800_finish_session,
425 	.dump_status		= former_dump_status,
426 };
427 
428 #define FF400_STF		0x000080100500ull
429 #define FF400_RX_PACKET_FORMAT	0x000080100504ull
430 #define FF400_ISOC_COMM_START	0x000080100508ull
431 #define FF400_TX_PACKET_FORMAT	0x00008010050cull
432 #define FF400_ISOC_COMM_STOP	0x000080100510ull
433 
434 /*
435  * Fireface 400 manages isochronous channel number in 3 bit field. Therefore,
436  * we can allocate between 0 and 7 channel.
437  */
438 static int keep_resources(struct snd_ff *ff, unsigned int rate)
439 {
440 	enum snd_ff_stream_mode mode;
441 	int i;
442 	int err;
443 
444 	// Check whether the given value is supported or not.
445 	for (i = 0; i < CIP_SFC_COUNT; i++) {
446 		if (amdtp_rate_table[i] == rate)
447 			break;
448 	}
449 	if (i >= CIP_SFC_COUNT)
450 		return -EINVAL;
451 
452 	err = snd_ff_stream_get_multiplier_mode(i, &mode);
453 	if (err < 0)
454 		return err;
455 
456 	/* Keep resources for in-stream. */
457 	ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
458 	err = fw_iso_resources_allocate(&ff->tx_resources,
459 			amdtp_stream_get_max_payload(&ff->tx_stream),
460 			fw_parent_device(ff->unit)->max_speed);
461 	if (err < 0)
462 		return err;
463 
464 	/* Keep resources for out-stream. */
465 	ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
466 	err = fw_iso_resources_allocate(&ff->rx_resources,
467 			amdtp_stream_get_max_payload(&ff->rx_stream),
468 			fw_parent_device(ff->unit)->max_speed);
469 	if (err < 0)
470 		fw_iso_resources_free(&ff->tx_resources);
471 
472 	return err;
473 }
474 
475 static int ff400_begin_session(struct snd_ff *ff, unsigned int rate)
476 {
477 	__le32 reg;
478 	int err;
479 
480 	err = keep_resources(ff, rate);
481 	if (err < 0)
482 		return err;
483 
484 	/* Set the number of data blocks transferred in a second. */
485 	reg = cpu_to_le32(rate);
486 	err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
487 				 FF400_STF, &reg, sizeof(reg), 0);
488 	if (err < 0)
489 		return err;
490 
491 	msleep(100);
492 
493 	/*
494 	 * Set isochronous channel and the number of quadlets of received
495 	 * packets.
496 	 */
497 	reg = cpu_to_le32(((ff->rx_stream.data_block_quadlets << 3) << 8) |
498 			  ff->rx_resources.channel);
499 	err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
500 				 FF400_RX_PACKET_FORMAT, &reg, sizeof(reg), 0);
501 	if (err < 0)
502 		return err;
503 
504 	/*
505 	 * Set isochronous channel and the number of quadlets of transmitted
506 	 * packet.
507 	 */
508 	/* TODO: investigate the purpose of this 0x80. */
509 	reg = cpu_to_le32((0x80 << 24) |
510 			  (ff->tx_resources.channel << 5) |
511 			  (ff->tx_stream.data_block_quadlets));
512 	err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
513 				 FF400_TX_PACKET_FORMAT, &reg, sizeof(reg), 0);
514 	if (err < 0)
515 		return err;
516 
517 	/* Allow to transmit packets. */
518 	reg = cpu_to_le32(0x00000001);
519 	return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
520 				 FF400_ISOC_COMM_START, &reg, sizeof(reg), 0);
521 }
522 
523 static void ff400_finish_session(struct snd_ff *ff)
524 {
525 	__le32 reg;
526 
527 	reg = cpu_to_le32(0x80000000);
528 	snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
529 			   FF400_ISOC_COMM_STOP, &reg, sizeof(reg), 0);
530 }
531 
532 // For Fireface 400, lower 4 bytes of destination address is configured by bit
533 // flag in quadlet register (little endian) at 0x'0000'801'0051c. Drivers can
534 // select one of 4 options:
535 //
536 // bit flags: offset of destination address
537 //  - 0x04000000: 0x'....'....'0000'0000
538 //  - 0x08000000: 0x'....'....'0000'0080
539 //  - 0x10000000: 0x'....'....'0000'0100
540 //  - 0x20000000: 0x'....'....'0000'0180
541 //
542 // Drivers can suppress the device to transfer asynchronous transactions by
543 // using below 2 bits.
544 //  - 0x01000000: suppress transmission
545 //  - 0x02000000: suppress transmission
546 //
547 // Actually, the register is write-only and includes the other options such as
548 // input attenuation. This driver allocates destination address with '0000'0000
549 // in its lower offset and expects userspace application to configure the
550 // register for it.
551 static void ff400_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
552 				  __le32 *buf, size_t length)
553 {
554 	int i;
555 
556 	for (i = 0; i < length / 4; i++) {
557 		u32 quad = le32_to_cpu(buf[i]);
558 		u8 byte;
559 		unsigned int index;
560 		struct snd_rawmidi_substream *substream;
561 
562 		/* Message in first port. */
563 		/*
564 		 * This value may represent the index of this unit when the same
565 		 * units are on the same IEEE 1394 bus. This driver doesn't use
566 		 * it.
567 		 */
568 		index = (quad >> 8) & 0xff;
569 		if (index > 0) {
570 			substream = READ_ONCE(ff->tx_midi_substreams[0]);
571 			if (substream != NULL) {
572 				byte = quad & 0xff;
573 				snd_rawmidi_receive(substream, &byte, 1);
574 			}
575 		}
576 
577 		/* Message in second port. */
578 		index = (quad >> 24) & 0xff;
579 		if (index > 0) {
580 			substream = READ_ONCE(ff->tx_midi_substreams[1]);
581 			if (substream != NULL) {
582 				byte = (quad >> 16) & 0xff;
583 				snd_rawmidi_receive(substream, &byte, 1);
584 			}
585 		}
586 	}
587 }
588 
589 const struct snd_ff_protocol snd_ff_protocol_ff400 = {
590 	.handle_midi_msg	= ff400_handle_midi_msg,
591 	.fill_midi_msg		= former_fill_midi_msg,
592 	.get_clock		= former_get_clock,
593 	.switch_fetching_mode	= former_switch_fetching_mode,
594 	.begin_session		= ff400_begin_session,
595 	.finish_session		= ff400_finish_session,
596 	.dump_status		= former_dump_status,
597 };
598