1 /* 2 * digi00x.h - a part of driver for Digidesign Digi 002/003 family 3 * 4 * Copyright (c) 2014-2015 Takashi Sakamoto 5 * 6 * Licensed under the terms of the GNU General Public License, version 2. 7 */ 8 9 #ifndef SOUND_DIGI00X_H_INCLUDED 10 #define SOUND_DIGI00X_H_INCLUDED 11 12 #include <linux/compat.h> 13 #include <linux/device.h> 14 #include <linux/firewire.h> 15 #include <linux/module.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/sched/signal.h> 20 21 #include <sound/core.h> 22 #include <sound/initval.h> 23 #include <sound/info.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/firewire.h> 27 #include <sound/hwdep.h> 28 #include <sound/rawmidi.h> 29 30 #include "../lib.h" 31 #include "../iso-resources.h" 32 #include "../amdtp-stream.h" 33 34 struct snd_dg00x { 35 struct snd_card *card; 36 struct fw_unit *unit; 37 38 struct mutex mutex; 39 spinlock_t lock; 40 41 bool registered; 42 struct delayed_work dwork; 43 44 struct amdtp_stream tx_stream; 45 struct fw_iso_resources tx_resources; 46 47 struct amdtp_stream rx_stream; 48 struct fw_iso_resources rx_resources; 49 50 unsigned int substreams_counter; 51 52 /* for uapi */ 53 int dev_lock_count; 54 bool dev_lock_changed; 55 wait_queue_head_t hwdep_wait; 56 57 /* For asynchronous messages. */ 58 struct fw_address_handler async_handler; 59 u32 msg; 60 61 /* Console models have additional MIDI ports for control surface. */ 62 bool is_console; 63 }; 64 65 #define DG00X_ADDR_BASE 0xffffe0000000ull 66 67 #define DG00X_OFFSET_STREAMING_STATE 0x0000 68 #define DG00X_OFFSET_STREAMING_SET 0x0004 69 /* unknown but address in host space 0x0008 */ 70 /* For LSB of the address 0x000c */ 71 /* unknown 0x0010 */ 72 #define DG00X_OFFSET_MESSAGE_ADDR 0x0014 73 /* For LSB of the address 0x0018 */ 74 /* unknown 0x001c */ 75 /* unknown 0x0020 */ 76 /* not used 0x0024--0x00ff */ 77 #define DG00X_OFFSET_ISOC_CHANNELS 0x0100 78 /* unknown 0x0104 */ 79 /* unknown 0x0108 */ 80 /* unknown 0x010c */ 81 #define DG00X_OFFSET_LOCAL_RATE 0x0110 82 #define DG00X_OFFSET_EXTERNAL_RATE 0x0114 83 #define DG00X_OFFSET_CLOCK_SOURCE 0x0118 84 #define DG00X_OFFSET_OPT_IFACE_MODE 0x011c 85 /* unknown 0x0120 */ 86 /* Mixer control on/off 0x0124 */ 87 /* unknown 0x0128 */ 88 #define DG00X_OFFSET_DETECT_EXTERNAL 0x012c 89 /* unknown 0x0138 */ 90 #define DG00X_OFFSET_MMC 0x0400 91 92 enum snd_dg00x_rate { 93 SND_DG00X_RATE_44100 = 0, 94 SND_DG00X_RATE_48000, 95 SND_DG00X_RATE_88200, 96 SND_DG00X_RATE_96000, 97 SND_DG00X_RATE_COUNT, 98 }; 99 100 enum snd_dg00x_clock { 101 SND_DG00X_CLOCK_INTERNAL = 0, 102 SND_DG00X_CLOCK_SPDIF, 103 SND_DG00X_CLOCK_ADAT, 104 SND_DG00X_CLOCK_WORD, 105 SND_DG00X_CLOCK_COUNT, 106 }; 107 108 enum snd_dg00x_optical_mode { 109 SND_DG00X_OPT_IFACE_MODE_ADAT = 0, 110 SND_DG00X_OPT_IFACE_MODE_SPDIF, 111 SND_DG00X_OPT_IFACE_MODE_COUNT, 112 }; 113 114 #define DOT_MIDI_IN_PORTS 1 115 #define DOT_MIDI_OUT_PORTS 2 116 117 int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit, 118 enum amdtp_stream_direction dir); 119 int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate, 120 unsigned int pcm_channels); 121 void amdtp_dot_reset(struct amdtp_stream *s); 122 int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s, 123 struct snd_pcm_runtime *runtime); 124 void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port, 125 struct snd_rawmidi_substream *midi); 126 127 int snd_dg00x_transaction_register(struct snd_dg00x *dg00x); 128 int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x); 129 void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x); 130 131 extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT]; 132 extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT]; 133 int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x, 134 unsigned int *rate); 135 int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x, 136 unsigned int *rate); 137 int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate); 138 int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x, 139 enum snd_dg00x_clock *clock); 140 int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x, 141 bool *detect); 142 int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x); 143 int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x, unsigned int rate); 144 void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x); 145 void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x); 146 void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x); 147 148 void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x); 149 int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x); 150 void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x); 151 152 void snd_dg00x_proc_init(struct snd_dg00x *dg00x); 153 154 int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x); 155 156 int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x); 157 158 int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x); 159 #endif 160