1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * digi00x.h - a part of driver for Digidesign Digi 002/003 family 4 * 5 * Copyright (c) 2014-2015 Takashi Sakamoto 6 */ 7 8 #ifndef SOUND_DIGI00X_H_INCLUDED 9 #define SOUND_DIGI00X_H_INCLUDED 10 11 #include <linux/compat.h> 12 #include <linux/device.h> 13 #include <linux/firewire.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/delay.h> 17 #include <linux/slab.h> 18 #include <linux/sched/signal.h> 19 20 #include <sound/core.h> 21 #include <sound/initval.h> 22 #include <sound/info.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/firewire.h> 26 #include <sound/hwdep.h> 27 #include <sound/rawmidi.h> 28 29 #include "../lib.h" 30 #include "../iso-resources.h" 31 #include "../amdtp-stream.h" 32 33 struct snd_dg00x { 34 struct snd_card *card; 35 struct fw_unit *unit; 36 37 struct mutex mutex; 38 spinlock_t lock; 39 40 bool registered; 41 struct delayed_work dwork; 42 43 struct amdtp_stream tx_stream; 44 struct fw_iso_resources tx_resources; 45 46 struct amdtp_stream rx_stream; 47 struct fw_iso_resources rx_resources; 48 49 unsigned int substreams_counter; 50 51 /* for uapi */ 52 int dev_lock_count; 53 bool dev_lock_changed; 54 wait_queue_head_t hwdep_wait; 55 56 /* For asynchronous messages. */ 57 struct fw_address_handler async_handler; 58 u32 msg; 59 60 /* Console models have additional MIDI ports for control surface. */ 61 bool is_console; 62 }; 63 64 #define DG00X_ADDR_BASE 0xffffe0000000ull 65 66 #define DG00X_OFFSET_STREAMING_STATE 0x0000 67 #define DG00X_OFFSET_STREAMING_SET 0x0004 68 /* unknown but address in host space 0x0008 */ 69 /* For LSB of the address 0x000c */ 70 /* unknown 0x0010 */ 71 #define DG00X_OFFSET_MESSAGE_ADDR 0x0014 72 /* For LSB of the address 0x0018 */ 73 /* unknown 0x001c */ 74 /* unknown 0x0020 */ 75 /* not used 0x0024--0x00ff */ 76 #define DG00X_OFFSET_ISOC_CHANNELS 0x0100 77 /* unknown 0x0104 */ 78 /* unknown 0x0108 */ 79 /* unknown 0x010c */ 80 #define DG00X_OFFSET_LOCAL_RATE 0x0110 81 #define DG00X_OFFSET_EXTERNAL_RATE 0x0114 82 #define DG00X_OFFSET_CLOCK_SOURCE 0x0118 83 #define DG00X_OFFSET_OPT_IFACE_MODE 0x011c 84 /* unknown 0x0120 */ 85 /* Mixer control on/off 0x0124 */ 86 /* unknown 0x0128 */ 87 #define DG00X_OFFSET_DETECT_EXTERNAL 0x012c 88 /* unknown 0x0138 */ 89 #define DG00X_OFFSET_MMC 0x0400 90 91 enum snd_dg00x_rate { 92 SND_DG00X_RATE_44100 = 0, 93 SND_DG00X_RATE_48000, 94 SND_DG00X_RATE_88200, 95 SND_DG00X_RATE_96000, 96 SND_DG00X_RATE_COUNT, 97 }; 98 99 enum snd_dg00x_clock { 100 SND_DG00X_CLOCK_INTERNAL = 0, 101 SND_DG00X_CLOCK_SPDIF, 102 SND_DG00X_CLOCK_ADAT, 103 SND_DG00X_CLOCK_WORD, 104 SND_DG00X_CLOCK_COUNT, 105 }; 106 107 enum snd_dg00x_optical_mode { 108 SND_DG00X_OPT_IFACE_MODE_ADAT = 0, 109 SND_DG00X_OPT_IFACE_MODE_SPDIF, 110 SND_DG00X_OPT_IFACE_MODE_COUNT, 111 }; 112 113 #define DOT_MIDI_IN_PORTS 1 114 #define DOT_MIDI_OUT_PORTS 2 115 116 int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit, 117 enum amdtp_stream_direction dir); 118 int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate, 119 unsigned int pcm_channels); 120 void amdtp_dot_reset(struct amdtp_stream *s); 121 int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s, 122 struct snd_pcm_runtime *runtime); 123 void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port, 124 struct snd_rawmidi_substream *midi); 125 126 int snd_dg00x_transaction_register(struct snd_dg00x *dg00x); 127 int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x); 128 void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x); 129 130 extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT]; 131 extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT]; 132 int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x, 133 unsigned int *rate); 134 int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x, 135 unsigned int *rate); 136 int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate); 137 int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x, 138 enum snd_dg00x_clock *clock); 139 int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x, 140 bool *detect); 141 int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x); 142 int snd_dg00x_stream_reserve_duplex(struct snd_dg00x *dg00x, unsigned int rate); 143 int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x); 144 void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x); 145 void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x); 146 void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x); 147 148 void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x); 149 int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x); 150 void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x); 151 152 void snd_dg00x_proc_init(struct snd_dg00x *dg00x); 153 154 int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x); 155 156 int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x); 157 158 int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x); 159 #endif 160