1 /* 2 * dice_stream.c - a part of driver for DICE based devices 3 * 4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de> 5 * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp> 6 * 7 * Licensed under the terms of the GNU General Public License, version 2. 8 */ 9 10 #include "dice.h" 11 12 #define CALLBACK_TIMEOUT 200 13 #define NOTIFICATION_TIMEOUT_MS (2 * MSEC_PER_SEC) 14 15 struct reg_params { 16 unsigned int count; 17 unsigned int size; 18 }; 19 20 const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = { 21 /* mode 0 */ 22 [0] = 32000, 23 [1] = 44100, 24 [2] = 48000, 25 /* mode 1 */ 26 [3] = 88200, 27 [4] = 96000, 28 /* mode 2 */ 29 [5] = 176400, 30 [6] = 192000, 31 }; 32 33 int snd_dice_stream_get_rate_mode(struct snd_dice *dice, unsigned int rate, 34 enum snd_dice_rate_mode *mode) 35 { 36 /* Corresponding to each entry in snd_dice_rates. */ 37 static const enum snd_dice_rate_mode modes[] = { 38 [0] = SND_DICE_RATE_MODE_LOW, 39 [1] = SND_DICE_RATE_MODE_LOW, 40 [2] = SND_DICE_RATE_MODE_LOW, 41 [3] = SND_DICE_RATE_MODE_MIDDLE, 42 [4] = SND_DICE_RATE_MODE_MIDDLE, 43 [5] = SND_DICE_RATE_MODE_HIGH, 44 [6] = SND_DICE_RATE_MODE_HIGH, 45 }; 46 int i; 47 48 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); i++) { 49 if (!(dice->clock_caps & BIT(i))) 50 continue; 51 if (snd_dice_rates[i] != rate) 52 continue; 53 54 *mode = modes[i]; 55 return 0; 56 } 57 58 return -EINVAL; 59 } 60 61 /* 62 * This operation has an effect to synchronize GLOBAL_STATUS/GLOBAL_SAMPLE_RATE 63 * to GLOBAL_STATUS. Especially, just after powering on, these are different. 64 */ 65 static int ensure_phase_lock(struct snd_dice *dice) 66 { 67 __be32 reg, nominal; 68 int err; 69 70 err = snd_dice_transaction_read_global(dice, GLOBAL_CLOCK_SELECT, 71 ®, sizeof(reg)); 72 if (err < 0) 73 return err; 74 75 if (completion_done(&dice->clock_accepted)) 76 reinit_completion(&dice->clock_accepted); 77 78 err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT, 79 ®, sizeof(reg)); 80 if (err < 0) 81 return err; 82 83 if (wait_for_completion_timeout(&dice->clock_accepted, 84 msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0) { 85 /* 86 * Old versions of Dice firmware transfer no notification when 87 * the same clock status as current one is set. In this case, 88 * just check current clock status. 89 */ 90 err = snd_dice_transaction_read_global(dice, GLOBAL_STATUS, 91 &nominal, sizeof(nominal)); 92 if (err < 0) 93 return err; 94 if (!(be32_to_cpu(nominal) & STATUS_SOURCE_LOCKED)) 95 return -ETIMEDOUT; 96 } 97 98 return 0; 99 } 100 101 static int get_register_params(struct snd_dice *dice, 102 struct reg_params *tx_params, 103 struct reg_params *rx_params) 104 { 105 __be32 reg[2]; 106 int err; 107 108 err = snd_dice_transaction_read_tx(dice, TX_NUMBER, reg, sizeof(reg)); 109 if (err < 0) 110 return err; 111 tx_params->count = 112 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS); 113 tx_params->size = be32_to_cpu(reg[1]) * 4; 114 115 err = snd_dice_transaction_read_rx(dice, RX_NUMBER, reg, sizeof(reg)); 116 if (err < 0) 117 return err; 118 rx_params->count = 119 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS); 120 rx_params->size = be32_to_cpu(reg[1]) * 4; 121 122 return 0; 123 } 124 125 static void release_resources(struct snd_dice *dice) 126 { 127 unsigned int i; 128 129 for (i = 0; i < MAX_STREAMS; i++) { 130 if (amdtp_stream_running(&dice->tx_stream[i])) { 131 amdtp_stream_pcm_abort(&dice->tx_stream[i]); 132 amdtp_stream_stop(&dice->tx_stream[i]); 133 } 134 if (amdtp_stream_running(&dice->rx_stream[i])) { 135 amdtp_stream_pcm_abort(&dice->rx_stream[i]); 136 amdtp_stream_stop(&dice->rx_stream[i]); 137 } 138 139 fw_iso_resources_free(&dice->tx_resources[i]); 140 fw_iso_resources_free(&dice->rx_resources[i]); 141 } 142 } 143 144 static void stop_streams(struct snd_dice *dice, enum amdtp_stream_direction dir, 145 struct reg_params *params) 146 { 147 __be32 reg; 148 unsigned int i; 149 150 for (i = 0; i < params->count; i++) { 151 reg = cpu_to_be32((u32)-1); 152 if (dir == AMDTP_IN_STREAM) { 153 snd_dice_transaction_write_tx(dice, 154 params->size * i + TX_ISOCHRONOUS, 155 ®, sizeof(reg)); 156 } else { 157 snd_dice_transaction_write_rx(dice, 158 params->size * i + RX_ISOCHRONOUS, 159 ®, sizeof(reg)); 160 } 161 } 162 } 163 164 static int keep_resources(struct snd_dice *dice, 165 enum amdtp_stream_direction dir, unsigned int index, 166 unsigned int rate, unsigned int pcm_chs, 167 unsigned int midi_ports) 168 { 169 struct amdtp_stream *stream; 170 struct fw_iso_resources *resources; 171 bool double_pcm_frames; 172 unsigned int i; 173 int err; 174 175 if (dir == AMDTP_IN_STREAM) { 176 stream = &dice->tx_stream[index]; 177 resources = &dice->tx_resources[index]; 178 } else { 179 stream = &dice->rx_stream[index]; 180 resources = &dice->rx_resources[index]; 181 } 182 183 /* 184 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in 185 * one data block of AMDTP packet. Thus sampling transfer frequency is 186 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are 187 * transferred on AMDTP packets at 96 kHz. Two successive samples of a 188 * channel are stored consecutively in the packet. This quirk is called 189 * as 'Dual Wire'. 190 * For this quirk, blocking mode is required and PCM buffer size should 191 * be aligned to SYT_INTERVAL. 192 */ 193 double_pcm_frames = rate > 96000; 194 if (double_pcm_frames) { 195 rate /= 2; 196 pcm_chs *= 2; 197 } 198 199 err = amdtp_am824_set_parameters(stream, rate, pcm_chs, midi_ports, 200 double_pcm_frames); 201 if (err < 0) 202 return err; 203 204 if (double_pcm_frames) { 205 pcm_chs /= 2; 206 207 for (i = 0; i < pcm_chs; i++) { 208 amdtp_am824_set_pcm_position(stream, i, i * 2); 209 amdtp_am824_set_pcm_position(stream, i + pcm_chs, 210 i * 2 + 1); 211 } 212 } 213 214 return fw_iso_resources_allocate(resources, 215 amdtp_stream_get_max_payload(stream), 216 fw_parent_device(dice->unit)->max_speed); 217 } 218 219 static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir, 220 unsigned int rate, struct reg_params *params) 221 { 222 __be32 reg[2]; 223 unsigned int i, pcm_chs, midi_ports; 224 struct amdtp_stream *streams; 225 struct fw_iso_resources *resources; 226 struct fw_device *fw_dev = fw_parent_device(dice->unit); 227 int err = 0; 228 229 if (dir == AMDTP_IN_STREAM) { 230 streams = dice->tx_stream; 231 resources = dice->tx_resources; 232 } else { 233 streams = dice->rx_stream; 234 resources = dice->rx_resources; 235 } 236 237 for (i = 0; i < params->count; i++) { 238 if (dir == AMDTP_IN_STREAM) { 239 err = snd_dice_transaction_read_tx(dice, 240 params->size * i + TX_NUMBER_AUDIO, 241 reg, sizeof(reg)); 242 } else { 243 err = snd_dice_transaction_read_rx(dice, 244 params->size * i + RX_NUMBER_AUDIO, 245 reg, sizeof(reg)); 246 } 247 if (err < 0) 248 return err; 249 pcm_chs = be32_to_cpu(reg[0]); 250 midi_ports = be32_to_cpu(reg[1]); 251 252 err = keep_resources(dice, dir, i, rate, pcm_chs, midi_ports); 253 if (err < 0) 254 return err; 255 256 reg[0] = cpu_to_be32(resources[i].channel); 257 if (dir == AMDTP_IN_STREAM) { 258 err = snd_dice_transaction_write_tx(dice, 259 params->size * i + TX_ISOCHRONOUS, 260 reg, sizeof(reg[0])); 261 } else { 262 err = snd_dice_transaction_write_rx(dice, 263 params->size * i + RX_ISOCHRONOUS, 264 reg, sizeof(reg[0])); 265 } 266 if (err < 0) 267 return err; 268 269 if (dir == AMDTP_IN_STREAM) { 270 reg[0] = cpu_to_be32(fw_dev->max_speed); 271 err = snd_dice_transaction_write_tx(dice, 272 params->size * i + TX_SPEED, 273 reg, sizeof(reg[0])); 274 if (err < 0) 275 return err; 276 } 277 278 err = amdtp_stream_start(&streams[i], resources[i].channel, 279 fw_dev->max_speed); 280 if (err < 0) 281 return err; 282 } 283 284 return err; 285 } 286 287 /* 288 * MEMO: After this function, there're two states of streams: 289 * - None streams are running. 290 * - All streams are running. 291 */ 292 int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate) 293 { 294 unsigned int curr_rate; 295 unsigned int i; 296 struct reg_params tx_params, rx_params; 297 bool need_to_start = false; 298 enum snd_dice_rate_mode mode; 299 int err; 300 301 if (dice->substreams_counter == 0) 302 return -EIO; 303 304 /* Check sampling transmission frequency. */ 305 err = snd_dice_transaction_get_rate(dice, &curr_rate); 306 if (err < 0) { 307 dev_err(&dice->unit->device, 308 "fail to get sampling rate\n"); 309 return err; 310 } 311 if (rate == 0) 312 rate = curr_rate; 313 if (rate != curr_rate) 314 return -EINVAL; 315 316 /* Check error of packet streaming. */ 317 for (i = 0; i < MAX_STREAMS; ++i) { 318 if (amdtp_streaming_error(&dice->tx_stream[i])) 319 break; 320 if (amdtp_streaming_error(&dice->rx_stream[i])) 321 break; 322 } 323 if (i < MAX_STREAMS) 324 need_to_start = true; 325 326 /* Check required streams are running or not. */ 327 err = snd_dice_stream_get_rate_mode(dice, rate, &mode); 328 if (err < 0) 329 return err; 330 for (i = 0; i < MAX_STREAMS; ++i) { 331 if (dice->tx_pcm_chs[i][mode] > 0 && 332 !amdtp_stream_running(&dice->tx_stream[i])) 333 break; 334 if (dice->rx_pcm_chs[i][mode] > 0 && 335 !amdtp_stream_running(&dice->rx_stream[i])) 336 break; 337 } 338 if (i < MAX_STREAMS) 339 need_to_start = true; 340 341 if (need_to_start) { 342 err = get_register_params(dice, &tx_params, &rx_params); 343 if (err < 0) 344 return err; 345 346 /* Stop transmission. */ 347 snd_dice_transaction_clear_enable(dice); 348 stop_streams(dice, AMDTP_IN_STREAM, &tx_params); 349 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); 350 release_resources(dice); 351 352 err = ensure_phase_lock(dice); 353 if (err < 0) { 354 dev_err(&dice->unit->device, 355 "fail to ensure phase lock\n"); 356 goto error; 357 } 358 359 /* Start both streams. */ 360 err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params); 361 if (err < 0) 362 goto error; 363 err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params); 364 if (err < 0) 365 goto error; 366 367 err = snd_dice_transaction_set_enable(dice); 368 if (err < 0) { 369 dev_err(&dice->unit->device, 370 "fail to enable interface\n"); 371 goto error; 372 } 373 374 for (i = 0; i < MAX_STREAMS; i++) { 375 if ((i < tx_params.count && 376 !amdtp_stream_wait_callback(&dice->tx_stream[i], 377 CALLBACK_TIMEOUT)) || 378 (i < rx_params.count && 379 !amdtp_stream_wait_callback(&dice->rx_stream[i], 380 CALLBACK_TIMEOUT))) { 381 err = -ETIMEDOUT; 382 goto error; 383 } 384 } 385 } 386 387 return err; 388 error: 389 snd_dice_transaction_clear_enable(dice); 390 stop_streams(dice, AMDTP_IN_STREAM, &tx_params); 391 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); 392 release_resources(dice); 393 return err; 394 } 395 396 /* 397 * MEMO: After this function, there're two states of streams: 398 * - None streams are running. 399 * - All streams are running. 400 */ 401 void snd_dice_stream_stop_duplex(struct snd_dice *dice) 402 { 403 struct reg_params tx_params, rx_params; 404 405 if (dice->substreams_counter > 0) 406 return; 407 408 snd_dice_transaction_clear_enable(dice); 409 410 if (get_register_params(dice, &tx_params, &rx_params) == 0) { 411 stop_streams(dice, AMDTP_IN_STREAM, &tx_params); 412 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); 413 } 414 415 release_resources(dice); 416 } 417 418 static int init_stream(struct snd_dice *dice, enum amdtp_stream_direction dir, 419 unsigned int index) 420 { 421 struct amdtp_stream *stream; 422 struct fw_iso_resources *resources; 423 int err; 424 425 if (dir == AMDTP_IN_STREAM) { 426 stream = &dice->tx_stream[index]; 427 resources = &dice->tx_resources[index]; 428 } else { 429 stream = &dice->rx_stream[index]; 430 resources = &dice->rx_resources[index]; 431 } 432 433 err = fw_iso_resources_init(resources, dice->unit); 434 if (err < 0) 435 goto end; 436 resources->channels_mask = 0x00000000ffffffffuLL; 437 438 err = amdtp_am824_init(stream, dice->unit, dir, CIP_BLOCKING); 439 if (err < 0) { 440 amdtp_stream_destroy(stream); 441 fw_iso_resources_destroy(resources); 442 } 443 end: 444 return err; 445 } 446 447 /* 448 * This function should be called before starting streams or after stopping 449 * streams. 450 */ 451 static void destroy_stream(struct snd_dice *dice, 452 enum amdtp_stream_direction dir, 453 unsigned int index) 454 { 455 struct amdtp_stream *stream; 456 struct fw_iso_resources *resources; 457 458 if (dir == AMDTP_IN_STREAM) { 459 stream = &dice->tx_stream[index]; 460 resources = &dice->tx_resources[index]; 461 } else { 462 stream = &dice->rx_stream[index]; 463 resources = &dice->rx_resources[index]; 464 } 465 466 amdtp_stream_destroy(stream); 467 fw_iso_resources_destroy(resources); 468 } 469 470 int snd_dice_stream_init_duplex(struct snd_dice *dice) 471 { 472 int i, err; 473 474 for (i = 0; i < MAX_STREAMS; i++) { 475 err = init_stream(dice, AMDTP_IN_STREAM, i); 476 if (err < 0) { 477 for (; i >= 0; i--) 478 destroy_stream(dice, AMDTP_OUT_STREAM, i); 479 goto end; 480 } 481 } 482 483 for (i = 0; i < MAX_STREAMS; i++) { 484 err = init_stream(dice, AMDTP_OUT_STREAM, i); 485 if (err < 0) { 486 for (; i >= 0; i--) 487 destroy_stream(dice, AMDTP_OUT_STREAM, i); 488 for (i = 0; i < MAX_STREAMS; i++) 489 destroy_stream(dice, AMDTP_IN_STREAM, i); 490 break; 491 } 492 } 493 end: 494 return err; 495 } 496 497 void snd_dice_stream_destroy_duplex(struct snd_dice *dice) 498 { 499 unsigned int i; 500 501 for (i = 0; i < MAX_STREAMS; i++) { 502 destroy_stream(dice, AMDTP_IN_STREAM, i); 503 destroy_stream(dice, AMDTP_OUT_STREAM, i); 504 } 505 } 506 507 void snd_dice_stream_update_duplex(struct snd_dice *dice) 508 { 509 struct reg_params tx_params, rx_params; 510 511 /* 512 * On a bus reset, the DICE firmware disables streaming and then goes 513 * off contemplating its own navel for hundreds of milliseconds before 514 * it can react to any of our attempts to reenable streaming. This 515 * means that we lose synchronization anyway, so we force our streams 516 * to stop so that the application can restart them in an orderly 517 * manner. 518 */ 519 dice->global_enabled = false; 520 521 if (get_register_params(dice, &tx_params, &rx_params) == 0) { 522 stop_streams(dice, AMDTP_IN_STREAM, &tx_params); 523 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); 524 } 525 } 526 527 int snd_dice_stream_detect_current_formats(struct snd_dice *dice) 528 { 529 unsigned int rate; 530 enum snd_dice_rate_mode mode; 531 __be32 reg[2]; 532 struct reg_params tx_params, rx_params; 533 int i; 534 int err; 535 536 /* If extended protocol is available, detect detail spec. */ 537 err = snd_dice_detect_extension_formats(dice); 538 if (err >= 0) 539 return err; 540 541 /* 542 * Available stream format is restricted at current mode of sampling 543 * clock. 544 */ 545 err = snd_dice_transaction_get_rate(dice, &rate); 546 if (err < 0) 547 return err; 548 549 err = snd_dice_stream_get_rate_mode(dice, rate, &mode); 550 if (err < 0) 551 return err; 552 553 /* 554 * Just after owning the unit (GLOBAL_OWNER), the unit can return 555 * invalid stream formats. Selecting clock parameters have an effect 556 * for the unit to refine it. 557 */ 558 err = ensure_phase_lock(dice); 559 if (err < 0) 560 return err; 561 562 err = get_register_params(dice, &tx_params, &rx_params); 563 if (err < 0) 564 return err; 565 566 for (i = 0; i < tx_params.count; ++i) { 567 err = snd_dice_transaction_read_tx(dice, 568 tx_params.size * i + TX_NUMBER_AUDIO, 569 reg, sizeof(reg)); 570 if (err < 0) 571 return err; 572 dice->tx_pcm_chs[i][mode] = be32_to_cpu(reg[0]); 573 dice->tx_midi_ports[i] = max_t(unsigned int, 574 be32_to_cpu(reg[1]), dice->tx_midi_ports[i]); 575 } 576 for (i = 0; i < rx_params.count; ++i) { 577 err = snd_dice_transaction_read_rx(dice, 578 rx_params.size * i + RX_NUMBER_AUDIO, 579 reg, sizeof(reg)); 580 if (err < 0) 581 return err; 582 dice->rx_pcm_chs[i][mode] = be32_to_cpu(reg[0]); 583 dice->rx_midi_ports[i] = max_t(unsigned int, 584 be32_to_cpu(reg[1]), dice->rx_midi_ports[i]); 585 } 586 587 return 0; 588 } 589 590 static void dice_lock_changed(struct snd_dice *dice) 591 { 592 dice->dev_lock_changed = true; 593 wake_up(&dice->hwdep_wait); 594 } 595 596 int snd_dice_stream_lock_try(struct snd_dice *dice) 597 { 598 int err; 599 600 spin_lock_irq(&dice->lock); 601 602 if (dice->dev_lock_count < 0) { 603 err = -EBUSY; 604 goto out; 605 } 606 607 if (dice->dev_lock_count++ == 0) 608 dice_lock_changed(dice); 609 err = 0; 610 out: 611 spin_unlock_irq(&dice->lock); 612 return err; 613 } 614 615 void snd_dice_stream_lock_release(struct snd_dice *dice) 616 { 617 spin_lock_irq(&dice->lock); 618 619 if (WARN_ON(dice->dev_lock_count <= 0)) 620 goto out; 621 622 if (--dice->dev_lock_count == 0) 623 dice_lock_changed(dice); 624 out: 625 spin_unlock_irq(&dice->lock); 626 } 627