1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * dice_stream.c - a part of driver for DICE based devices 4 * 5 * Copyright (c) Clemens Ladisch <clemens@ladisch.de> 6 * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp> 7 */ 8 9 #include "dice.h" 10 11 #define CALLBACK_TIMEOUT 200 12 #define NOTIFICATION_TIMEOUT_MS (2 * MSEC_PER_SEC) 13 14 struct reg_params { 15 unsigned int count; 16 unsigned int size; 17 }; 18 19 const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = { 20 /* mode 0 */ 21 [0] = 32000, 22 [1] = 44100, 23 [2] = 48000, 24 /* mode 1 */ 25 [3] = 88200, 26 [4] = 96000, 27 /* mode 2 */ 28 [5] = 176400, 29 [6] = 192000, 30 }; 31 32 int snd_dice_stream_get_rate_mode(struct snd_dice *dice, unsigned int rate, 33 enum snd_dice_rate_mode *mode) 34 { 35 /* Corresponding to each entry in snd_dice_rates. */ 36 static const enum snd_dice_rate_mode modes[] = { 37 [0] = SND_DICE_RATE_MODE_LOW, 38 [1] = SND_DICE_RATE_MODE_LOW, 39 [2] = SND_DICE_RATE_MODE_LOW, 40 [3] = SND_DICE_RATE_MODE_MIDDLE, 41 [4] = SND_DICE_RATE_MODE_MIDDLE, 42 [5] = SND_DICE_RATE_MODE_HIGH, 43 [6] = SND_DICE_RATE_MODE_HIGH, 44 }; 45 int i; 46 47 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); i++) { 48 if (!(dice->clock_caps & BIT(i))) 49 continue; 50 if (snd_dice_rates[i] != rate) 51 continue; 52 53 *mode = modes[i]; 54 return 0; 55 } 56 57 return -EINVAL; 58 } 59 60 /* 61 * This operation has an effect to synchronize GLOBAL_STATUS/GLOBAL_SAMPLE_RATE 62 * to GLOBAL_STATUS. Especially, just after powering on, these are different. 63 */ 64 static int ensure_phase_lock(struct snd_dice *dice, unsigned int rate) 65 { 66 __be32 reg, nominal; 67 u32 data; 68 int i; 69 int err; 70 71 err = snd_dice_transaction_read_global(dice, GLOBAL_CLOCK_SELECT, 72 ®, sizeof(reg)); 73 if (err < 0) 74 return err; 75 76 data = be32_to_cpu(reg); 77 78 data &= ~CLOCK_RATE_MASK; 79 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); ++i) { 80 if (snd_dice_rates[i] == rate) 81 break; 82 } 83 if (i == ARRAY_SIZE(snd_dice_rates)) 84 return -EINVAL; 85 data |= i << CLOCK_RATE_SHIFT; 86 87 if (completion_done(&dice->clock_accepted)) 88 reinit_completion(&dice->clock_accepted); 89 90 reg = cpu_to_be32(data); 91 err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT, 92 ®, sizeof(reg)); 93 if (err < 0) 94 return err; 95 96 if (wait_for_completion_timeout(&dice->clock_accepted, 97 msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0) { 98 /* 99 * Old versions of Dice firmware transfer no notification when 100 * the same clock status as current one is set. In this case, 101 * just check current clock status. 102 */ 103 err = snd_dice_transaction_read_global(dice, GLOBAL_STATUS, 104 &nominal, sizeof(nominal)); 105 if (err < 0) 106 return err; 107 if (!(be32_to_cpu(nominal) & STATUS_SOURCE_LOCKED)) 108 return -ETIMEDOUT; 109 } 110 111 return 0; 112 } 113 114 static int get_register_params(struct snd_dice *dice, 115 struct reg_params *tx_params, 116 struct reg_params *rx_params) 117 { 118 __be32 reg[2]; 119 int err; 120 121 err = snd_dice_transaction_read_tx(dice, TX_NUMBER, reg, sizeof(reg)); 122 if (err < 0) 123 return err; 124 tx_params->count = 125 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS); 126 tx_params->size = be32_to_cpu(reg[1]) * 4; 127 128 err = snd_dice_transaction_read_rx(dice, RX_NUMBER, reg, sizeof(reg)); 129 if (err < 0) 130 return err; 131 rx_params->count = 132 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS); 133 rx_params->size = be32_to_cpu(reg[1]) * 4; 134 135 return 0; 136 } 137 138 static void release_resources(struct snd_dice *dice) 139 { 140 unsigned int i; 141 142 for (i = 0; i < MAX_STREAMS; i++) { 143 if (amdtp_stream_running(&dice->tx_stream[i])) { 144 amdtp_stream_pcm_abort(&dice->tx_stream[i]); 145 amdtp_stream_stop(&dice->tx_stream[i]); 146 } 147 if (amdtp_stream_running(&dice->rx_stream[i])) { 148 amdtp_stream_pcm_abort(&dice->rx_stream[i]); 149 amdtp_stream_stop(&dice->rx_stream[i]); 150 } 151 152 fw_iso_resources_free(&dice->tx_resources[i]); 153 fw_iso_resources_free(&dice->rx_resources[i]); 154 } 155 } 156 157 static void stop_streams(struct snd_dice *dice, enum amdtp_stream_direction dir, 158 struct reg_params *params) 159 { 160 __be32 reg; 161 unsigned int i; 162 163 for (i = 0; i < params->count; i++) { 164 reg = cpu_to_be32((u32)-1); 165 if (dir == AMDTP_IN_STREAM) { 166 snd_dice_transaction_write_tx(dice, 167 params->size * i + TX_ISOCHRONOUS, 168 ®, sizeof(reg)); 169 } else { 170 snd_dice_transaction_write_rx(dice, 171 params->size * i + RX_ISOCHRONOUS, 172 ®, sizeof(reg)); 173 } 174 } 175 } 176 177 static int keep_resources(struct snd_dice *dice, 178 enum amdtp_stream_direction dir, unsigned int index, 179 unsigned int rate, unsigned int pcm_chs, 180 unsigned int midi_ports) 181 { 182 struct amdtp_stream *stream; 183 struct fw_iso_resources *resources; 184 bool double_pcm_frames; 185 unsigned int i; 186 int err; 187 188 if (dir == AMDTP_IN_STREAM) { 189 stream = &dice->tx_stream[index]; 190 resources = &dice->tx_resources[index]; 191 } else { 192 stream = &dice->rx_stream[index]; 193 resources = &dice->rx_resources[index]; 194 } 195 196 /* 197 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in 198 * one data block of AMDTP packet. Thus sampling transfer frequency is 199 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are 200 * transferred on AMDTP packets at 96 kHz. Two successive samples of a 201 * channel are stored consecutively in the packet. This quirk is called 202 * as 'Dual Wire'. 203 * For this quirk, blocking mode is required and PCM buffer size should 204 * be aligned to SYT_INTERVAL. 205 */ 206 double_pcm_frames = rate > 96000; 207 if (double_pcm_frames) { 208 rate /= 2; 209 pcm_chs *= 2; 210 } 211 212 err = amdtp_am824_set_parameters(stream, rate, pcm_chs, midi_ports, 213 double_pcm_frames); 214 if (err < 0) 215 return err; 216 217 if (double_pcm_frames) { 218 pcm_chs /= 2; 219 220 for (i = 0; i < pcm_chs; i++) { 221 amdtp_am824_set_pcm_position(stream, i, i * 2); 222 amdtp_am824_set_pcm_position(stream, i + pcm_chs, 223 i * 2 + 1); 224 } 225 } 226 227 return fw_iso_resources_allocate(resources, 228 amdtp_stream_get_max_payload(stream), 229 fw_parent_device(dice->unit)->max_speed); 230 } 231 232 static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir, 233 unsigned int rate, struct reg_params *params) 234 { 235 __be32 reg[2]; 236 enum snd_dice_rate_mode mode; 237 unsigned int i, pcm_chs, midi_ports; 238 struct amdtp_stream *streams; 239 struct fw_iso_resources *resources; 240 struct fw_device *fw_dev = fw_parent_device(dice->unit); 241 int err = 0; 242 243 if (dir == AMDTP_IN_STREAM) { 244 streams = dice->tx_stream; 245 resources = dice->tx_resources; 246 } else { 247 streams = dice->rx_stream; 248 resources = dice->rx_resources; 249 } 250 251 err = snd_dice_stream_get_rate_mode(dice, rate, &mode); 252 if (err < 0) 253 return err; 254 255 for (i = 0; i < params->count; i++) { 256 unsigned int pcm_cache; 257 unsigned int midi_cache; 258 259 if (dir == AMDTP_IN_STREAM) { 260 pcm_cache = dice->tx_pcm_chs[i][mode]; 261 midi_cache = dice->tx_midi_ports[i]; 262 err = snd_dice_transaction_read_tx(dice, 263 params->size * i + TX_NUMBER_AUDIO, 264 reg, sizeof(reg)); 265 } else { 266 pcm_cache = dice->rx_pcm_chs[i][mode]; 267 midi_cache = dice->rx_midi_ports[i]; 268 err = snd_dice_transaction_read_rx(dice, 269 params->size * i + RX_NUMBER_AUDIO, 270 reg, sizeof(reg)); 271 } 272 if (err < 0) 273 return err; 274 pcm_chs = be32_to_cpu(reg[0]); 275 midi_ports = be32_to_cpu(reg[1]); 276 277 /* These are important for developer of this driver. */ 278 if (pcm_chs != pcm_cache || midi_ports != midi_cache) { 279 dev_info(&dice->unit->device, 280 "cache mismatch: pcm: %u:%u, midi: %u:%u\n", 281 pcm_chs, pcm_cache, midi_ports, midi_cache); 282 return -EPROTO; 283 } 284 285 err = keep_resources(dice, dir, i, rate, pcm_chs, midi_ports); 286 if (err < 0) 287 return err; 288 289 reg[0] = cpu_to_be32(resources[i].channel); 290 if (dir == AMDTP_IN_STREAM) { 291 err = snd_dice_transaction_write_tx(dice, 292 params->size * i + TX_ISOCHRONOUS, 293 reg, sizeof(reg[0])); 294 } else { 295 err = snd_dice_transaction_write_rx(dice, 296 params->size * i + RX_ISOCHRONOUS, 297 reg, sizeof(reg[0])); 298 } 299 if (err < 0) 300 return err; 301 302 if (dir == AMDTP_IN_STREAM) { 303 reg[0] = cpu_to_be32(fw_dev->max_speed); 304 err = snd_dice_transaction_write_tx(dice, 305 params->size * i + TX_SPEED, 306 reg, sizeof(reg[0])); 307 if (err < 0) 308 return err; 309 } 310 311 err = amdtp_stream_start(&streams[i], resources[i].channel, 312 fw_dev->max_speed); 313 if (err < 0) 314 return err; 315 } 316 317 return err; 318 } 319 320 static int start_duplex_streams(struct snd_dice *dice, unsigned int rate) 321 { 322 struct reg_params tx_params, rx_params; 323 int i; 324 int err; 325 326 err = get_register_params(dice, &tx_params, &rx_params); 327 if (err < 0) 328 return err; 329 330 /* Stop transmission. */ 331 stop_streams(dice, AMDTP_IN_STREAM, &tx_params); 332 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); 333 snd_dice_transaction_clear_enable(dice); 334 release_resources(dice); 335 336 err = ensure_phase_lock(dice, rate); 337 if (err < 0) { 338 dev_err(&dice->unit->device, "fail to ensure phase lock\n"); 339 return err; 340 } 341 342 /* Likely to have changed stream formats. */ 343 err = get_register_params(dice, &tx_params, &rx_params); 344 if (err < 0) 345 return err; 346 347 /* Start both streams. */ 348 err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params); 349 if (err < 0) 350 goto error; 351 err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params); 352 if (err < 0) 353 goto error; 354 355 err = snd_dice_transaction_set_enable(dice); 356 if (err < 0) { 357 dev_err(&dice->unit->device, "fail to enable interface\n"); 358 goto error; 359 } 360 361 for (i = 0; i < MAX_STREAMS; i++) { 362 if ((i < tx_params.count && 363 !amdtp_stream_wait_callback(&dice->tx_stream[i], 364 CALLBACK_TIMEOUT)) || 365 (i < rx_params.count && 366 !amdtp_stream_wait_callback(&dice->rx_stream[i], 367 CALLBACK_TIMEOUT))) { 368 err = -ETIMEDOUT; 369 goto error; 370 } 371 } 372 373 return 0; 374 error: 375 stop_streams(dice, AMDTP_IN_STREAM, &tx_params); 376 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); 377 snd_dice_transaction_clear_enable(dice); 378 release_resources(dice); 379 return err; 380 } 381 382 /* 383 * MEMO: After this function, there're two states of streams: 384 * - None streams are running. 385 * - All streams are running. 386 */ 387 int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate) 388 { 389 unsigned int curr_rate; 390 unsigned int i; 391 enum snd_dice_rate_mode mode; 392 int err; 393 394 if (dice->substreams_counter == 0) 395 return -EIO; 396 397 /* Check sampling transmission frequency. */ 398 err = snd_dice_transaction_get_rate(dice, &curr_rate); 399 if (err < 0) { 400 dev_err(&dice->unit->device, 401 "fail to get sampling rate\n"); 402 return err; 403 } 404 if (rate == 0) 405 rate = curr_rate; 406 if (rate != curr_rate) 407 goto restart; 408 409 /* Check error of packet streaming. */ 410 for (i = 0; i < MAX_STREAMS; ++i) { 411 if (amdtp_streaming_error(&dice->tx_stream[i])) 412 break; 413 if (amdtp_streaming_error(&dice->rx_stream[i])) 414 break; 415 } 416 if (i < MAX_STREAMS) 417 goto restart; 418 419 /* Check required streams are running or not. */ 420 err = snd_dice_stream_get_rate_mode(dice, rate, &mode); 421 if (err < 0) 422 return err; 423 for (i = 0; i < MAX_STREAMS; ++i) { 424 if (dice->tx_pcm_chs[i][mode] > 0 && 425 !amdtp_stream_running(&dice->tx_stream[i])) 426 break; 427 if (dice->rx_pcm_chs[i][mode] > 0 && 428 !amdtp_stream_running(&dice->rx_stream[i])) 429 break; 430 } 431 if (i < MAX_STREAMS) 432 goto restart; 433 434 return 0; 435 restart: 436 return start_duplex_streams(dice, rate); 437 } 438 439 /* 440 * MEMO: After this function, there're two states of streams: 441 * - None streams are running. 442 * - All streams are running. 443 */ 444 void snd_dice_stream_stop_duplex(struct snd_dice *dice) 445 { 446 struct reg_params tx_params, rx_params; 447 448 if (dice->substreams_counter > 0) 449 return; 450 451 snd_dice_transaction_clear_enable(dice); 452 453 if (get_register_params(dice, &tx_params, &rx_params) == 0) { 454 stop_streams(dice, AMDTP_IN_STREAM, &tx_params); 455 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); 456 } 457 458 release_resources(dice); 459 } 460 461 static int init_stream(struct snd_dice *dice, enum amdtp_stream_direction dir, 462 unsigned int index) 463 { 464 struct amdtp_stream *stream; 465 struct fw_iso_resources *resources; 466 int err; 467 468 if (dir == AMDTP_IN_STREAM) { 469 stream = &dice->tx_stream[index]; 470 resources = &dice->tx_resources[index]; 471 } else { 472 stream = &dice->rx_stream[index]; 473 resources = &dice->rx_resources[index]; 474 } 475 476 err = fw_iso_resources_init(resources, dice->unit); 477 if (err < 0) 478 goto end; 479 resources->channels_mask = 0x00000000ffffffffuLL; 480 481 err = amdtp_am824_init(stream, dice->unit, dir, CIP_BLOCKING); 482 if (err < 0) { 483 amdtp_stream_destroy(stream); 484 fw_iso_resources_destroy(resources); 485 } 486 end: 487 return err; 488 } 489 490 /* 491 * This function should be called before starting streams or after stopping 492 * streams. 493 */ 494 static void destroy_stream(struct snd_dice *dice, 495 enum amdtp_stream_direction dir, 496 unsigned int index) 497 { 498 struct amdtp_stream *stream; 499 struct fw_iso_resources *resources; 500 501 if (dir == AMDTP_IN_STREAM) { 502 stream = &dice->tx_stream[index]; 503 resources = &dice->tx_resources[index]; 504 } else { 505 stream = &dice->rx_stream[index]; 506 resources = &dice->rx_resources[index]; 507 } 508 509 amdtp_stream_destroy(stream); 510 fw_iso_resources_destroy(resources); 511 } 512 513 int snd_dice_stream_init_duplex(struct snd_dice *dice) 514 { 515 int i, err; 516 517 for (i = 0; i < MAX_STREAMS; i++) { 518 err = init_stream(dice, AMDTP_IN_STREAM, i); 519 if (err < 0) { 520 for (; i >= 0; i--) 521 destroy_stream(dice, AMDTP_IN_STREAM, i); 522 goto end; 523 } 524 } 525 526 for (i = 0; i < MAX_STREAMS; i++) { 527 err = init_stream(dice, AMDTP_OUT_STREAM, i); 528 if (err < 0) { 529 for (; i >= 0; i--) 530 destroy_stream(dice, AMDTP_OUT_STREAM, i); 531 for (i = 0; i < MAX_STREAMS; i++) 532 destroy_stream(dice, AMDTP_IN_STREAM, i); 533 break; 534 } 535 } 536 end: 537 return err; 538 } 539 540 void snd_dice_stream_destroy_duplex(struct snd_dice *dice) 541 { 542 unsigned int i; 543 544 for (i = 0; i < MAX_STREAMS; i++) { 545 destroy_stream(dice, AMDTP_IN_STREAM, i); 546 destroy_stream(dice, AMDTP_OUT_STREAM, i); 547 } 548 } 549 550 void snd_dice_stream_update_duplex(struct snd_dice *dice) 551 { 552 struct reg_params tx_params, rx_params; 553 554 /* 555 * On a bus reset, the DICE firmware disables streaming and then goes 556 * off contemplating its own navel for hundreds of milliseconds before 557 * it can react to any of our attempts to reenable streaming. This 558 * means that we lose synchronization anyway, so we force our streams 559 * to stop so that the application can restart them in an orderly 560 * manner. 561 */ 562 dice->global_enabled = false; 563 564 if (get_register_params(dice, &tx_params, &rx_params) == 0) { 565 stop_streams(dice, AMDTP_IN_STREAM, &tx_params); 566 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); 567 } 568 } 569 570 int snd_dice_stream_detect_current_formats(struct snd_dice *dice) 571 { 572 unsigned int rate; 573 enum snd_dice_rate_mode mode; 574 __be32 reg[2]; 575 struct reg_params tx_params, rx_params; 576 int i; 577 int err; 578 579 /* If extended protocol is available, detect detail spec. */ 580 err = snd_dice_detect_extension_formats(dice); 581 if (err >= 0) 582 return err; 583 584 /* 585 * Available stream format is restricted at current mode of sampling 586 * clock. 587 */ 588 err = snd_dice_transaction_get_rate(dice, &rate); 589 if (err < 0) 590 return err; 591 592 err = snd_dice_stream_get_rate_mode(dice, rate, &mode); 593 if (err < 0) 594 return err; 595 596 /* 597 * Just after owning the unit (GLOBAL_OWNER), the unit can return 598 * invalid stream formats. Selecting clock parameters have an effect 599 * for the unit to refine it. 600 */ 601 err = ensure_phase_lock(dice, rate); 602 if (err < 0) 603 return err; 604 605 err = get_register_params(dice, &tx_params, &rx_params); 606 if (err < 0) 607 return err; 608 609 for (i = 0; i < tx_params.count; ++i) { 610 err = snd_dice_transaction_read_tx(dice, 611 tx_params.size * i + TX_NUMBER_AUDIO, 612 reg, sizeof(reg)); 613 if (err < 0) 614 return err; 615 dice->tx_pcm_chs[i][mode] = be32_to_cpu(reg[0]); 616 dice->tx_midi_ports[i] = max_t(unsigned int, 617 be32_to_cpu(reg[1]), dice->tx_midi_ports[i]); 618 } 619 for (i = 0; i < rx_params.count; ++i) { 620 err = snd_dice_transaction_read_rx(dice, 621 rx_params.size * i + RX_NUMBER_AUDIO, 622 reg, sizeof(reg)); 623 if (err < 0) 624 return err; 625 dice->rx_pcm_chs[i][mode] = be32_to_cpu(reg[0]); 626 dice->rx_midi_ports[i] = max_t(unsigned int, 627 be32_to_cpu(reg[1]), dice->rx_midi_ports[i]); 628 } 629 630 return 0; 631 } 632 633 static void dice_lock_changed(struct snd_dice *dice) 634 { 635 dice->dev_lock_changed = true; 636 wake_up(&dice->hwdep_wait); 637 } 638 639 int snd_dice_stream_lock_try(struct snd_dice *dice) 640 { 641 int err; 642 643 spin_lock_irq(&dice->lock); 644 645 if (dice->dev_lock_count < 0) { 646 err = -EBUSY; 647 goto out; 648 } 649 650 if (dice->dev_lock_count++ == 0) 651 dice_lock_changed(dice); 652 err = 0; 653 out: 654 spin_unlock_irq(&dice->lock); 655 return err; 656 } 657 658 void snd_dice_stream_lock_release(struct snd_dice *dice) 659 { 660 spin_lock_irq(&dice->lock); 661 662 if (WARN_ON(dice->dev_lock_count <= 0)) 663 goto out; 664 665 if (--dice->dev_lock_count == 0) 666 dice_lock_changed(dice); 667 out: 668 spin_unlock_irq(&dice->lock); 669 } 670