1 /*
2  * dice_stream.c - a part of driver for DICE based devices
3  *
4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5  * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp>
6  *
7  * Licensed under the terms of the GNU General Public License, version 2.
8  */
9 
10 #include "dice.h"
11 
12 #define	CALLBACK_TIMEOUT	200
13 #define NOTIFICATION_TIMEOUT_MS	(2 * MSEC_PER_SEC)
14 
15 struct reg_params {
16 	unsigned int count;
17 	unsigned int size;
18 };
19 
20 const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = {
21 	/* mode 0 */
22 	[0] =  32000,
23 	[1] =  44100,
24 	[2] =  48000,
25 	/* mode 1 */
26 	[3] =  88200,
27 	[4] =  96000,
28 	/* mode 2 */
29 	[5] = 176400,
30 	[6] = 192000,
31 };
32 
33 int snd_dice_stream_get_rate_mode(struct snd_dice *dice, unsigned int rate,
34 				  enum snd_dice_rate_mode *mode)
35 {
36 	/* Corresponding to each entry in snd_dice_rates. */
37 	static const enum snd_dice_rate_mode modes[] = {
38 		[0] = SND_DICE_RATE_MODE_LOW,
39 		[1] = SND_DICE_RATE_MODE_LOW,
40 		[2] = SND_DICE_RATE_MODE_LOW,
41 		[3] = SND_DICE_RATE_MODE_MIDDLE,
42 		[4] = SND_DICE_RATE_MODE_MIDDLE,
43 		[5] = SND_DICE_RATE_MODE_HIGH,
44 		[6] = SND_DICE_RATE_MODE_HIGH,
45 	};
46 	int i;
47 
48 	for (i = 0; i < ARRAY_SIZE(snd_dice_rates); i++) {
49 		if (!(dice->clock_caps & BIT(i)))
50 			continue;
51 		if (snd_dice_rates[i] != rate)
52 			continue;
53 
54 		*mode = modes[i];
55 		return 0;
56 	}
57 
58 	return -EINVAL;
59 }
60 
61 /*
62  * This operation has an effect to synchronize GLOBAL_STATUS/GLOBAL_SAMPLE_RATE
63  * to GLOBAL_STATUS. Especially, just after powering on, these are different.
64  */
65 static int ensure_phase_lock(struct snd_dice *dice)
66 {
67 	__be32 reg, nominal;
68 	int err;
69 
70 	err = snd_dice_transaction_read_global(dice, GLOBAL_CLOCK_SELECT,
71 					       &reg, sizeof(reg));
72 	if (err < 0)
73 		return err;
74 
75 	if (completion_done(&dice->clock_accepted))
76 		reinit_completion(&dice->clock_accepted);
77 
78 	err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT,
79 						&reg, sizeof(reg));
80 	if (err < 0)
81 		return err;
82 
83 	if (wait_for_completion_timeout(&dice->clock_accepted,
84 			msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0) {
85 		/*
86 		 * Old versions of Dice firmware transfer no notification when
87 		 * the same clock status as current one is set. In this case,
88 		 * just check current clock status.
89 		 */
90 		err = snd_dice_transaction_read_global(dice, GLOBAL_STATUS,
91 						&nominal, sizeof(nominal));
92 		if (err < 0)
93 			return err;
94 		if (!(be32_to_cpu(nominal) & STATUS_SOURCE_LOCKED))
95 			return -ETIMEDOUT;
96 	}
97 
98 	return 0;
99 }
100 
101 static int get_register_params(struct snd_dice *dice,
102 			       struct reg_params *tx_params,
103 			       struct reg_params *rx_params)
104 {
105 	__be32 reg[2];
106 	int err;
107 
108 	err = snd_dice_transaction_read_tx(dice, TX_NUMBER, reg, sizeof(reg));
109 	if (err < 0)
110 		return err;
111 	tx_params->count =
112 			min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
113 	tx_params->size = be32_to_cpu(reg[1]) * 4;
114 
115 	err = snd_dice_transaction_read_rx(dice, RX_NUMBER, reg, sizeof(reg));
116 	if (err < 0)
117 		return err;
118 	rx_params->count =
119 			min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
120 	rx_params->size = be32_to_cpu(reg[1]) * 4;
121 
122 	return 0;
123 }
124 
125 static void release_resources(struct snd_dice *dice)
126 {
127 	unsigned int i;
128 
129 	for (i = 0; i < MAX_STREAMS; i++) {
130 		if (amdtp_stream_running(&dice->tx_stream[i])) {
131 			amdtp_stream_pcm_abort(&dice->tx_stream[i]);
132 			amdtp_stream_stop(&dice->tx_stream[i]);
133 		}
134 		if (amdtp_stream_running(&dice->rx_stream[i])) {
135 			amdtp_stream_pcm_abort(&dice->rx_stream[i]);
136 			amdtp_stream_stop(&dice->rx_stream[i]);
137 		}
138 
139 		fw_iso_resources_free(&dice->tx_resources[i]);
140 		fw_iso_resources_free(&dice->rx_resources[i]);
141 	}
142 }
143 
144 static void stop_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
145 			 struct reg_params *params)
146 {
147 	__be32 reg;
148 	unsigned int i;
149 
150 	for (i = 0; i < params->count; i++) {
151 		reg = cpu_to_be32((u32)-1);
152 		if (dir == AMDTP_IN_STREAM) {
153 			snd_dice_transaction_write_tx(dice,
154 					params->size * i + TX_ISOCHRONOUS,
155 					&reg, sizeof(reg));
156 		} else {
157 			snd_dice_transaction_write_rx(dice,
158 					params->size * i + RX_ISOCHRONOUS,
159 					&reg, sizeof(reg));
160 		}
161 	}
162 }
163 
164 static int keep_resources(struct snd_dice *dice,
165 			  enum amdtp_stream_direction dir, unsigned int index,
166 			  unsigned int rate, unsigned int pcm_chs,
167 			  unsigned int midi_ports)
168 {
169 	struct amdtp_stream *stream;
170 	struct fw_iso_resources *resources;
171 	bool double_pcm_frames;
172 	unsigned int i;
173 	int err;
174 
175 	if (dir == AMDTP_IN_STREAM) {
176 		stream = &dice->tx_stream[index];
177 		resources = &dice->tx_resources[index];
178 	} else {
179 		stream = &dice->rx_stream[index];
180 		resources = &dice->rx_resources[index];
181 	}
182 
183 	/*
184 	 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
185 	 * one data block of AMDTP packet. Thus sampling transfer frequency is
186 	 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
187 	 * transferred on AMDTP packets at 96 kHz. Two successive samples of a
188 	 * channel are stored consecutively in the packet. This quirk is called
189 	 * as 'Dual Wire'.
190 	 * For this quirk, blocking mode is required and PCM buffer size should
191 	 * be aligned to SYT_INTERVAL.
192 	 */
193 	double_pcm_frames = rate > 96000;
194 	if (double_pcm_frames) {
195 		rate /= 2;
196 		pcm_chs *= 2;
197 	}
198 
199 	err = amdtp_am824_set_parameters(stream, rate, pcm_chs, midi_ports,
200 					 double_pcm_frames);
201 	if (err < 0)
202 		return err;
203 
204 	if (double_pcm_frames) {
205 		pcm_chs /= 2;
206 
207 		for (i = 0; i < pcm_chs; i++) {
208 			amdtp_am824_set_pcm_position(stream, i, i * 2);
209 			amdtp_am824_set_pcm_position(stream, i + pcm_chs,
210 						     i * 2 + 1);
211 		}
212 	}
213 
214 	return fw_iso_resources_allocate(resources,
215 				amdtp_stream_get_max_payload(stream),
216 				fw_parent_device(dice->unit)->max_speed);
217 }
218 
219 static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
220 			 unsigned int rate, struct reg_params *params)
221 {
222 	__be32 reg[2];
223 	unsigned int i, pcm_chs, midi_ports;
224 	struct amdtp_stream *streams;
225 	struct fw_iso_resources *resources;
226 	struct fw_device *fw_dev = fw_parent_device(dice->unit);
227 	int err = 0;
228 
229 	if (dir == AMDTP_IN_STREAM) {
230 		streams = dice->tx_stream;
231 		resources = dice->tx_resources;
232 	} else {
233 		streams = dice->rx_stream;
234 		resources = dice->rx_resources;
235 	}
236 
237 	for (i = 0; i < params->count; i++) {
238 		if (dir == AMDTP_IN_STREAM) {
239 			err = snd_dice_transaction_read_tx(dice,
240 					params->size * i + TX_NUMBER_AUDIO,
241 					reg, sizeof(reg));
242 		} else {
243 			err = snd_dice_transaction_read_rx(dice,
244 					params->size * i + RX_NUMBER_AUDIO,
245 					reg, sizeof(reg));
246 		}
247 		if (err < 0)
248 			return err;
249 		pcm_chs = be32_to_cpu(reg[0]);
250 		midi_ports = be32_to_cpu(reg[1]);
251 
252 		err = keep_resources(dice, dir, i, rate, pcm_chs, midi_ports);
253 		if (err < 0)
254 			return err;
255 
256 		reg[0] = cpu_to_be32(resources[i].channel);
257 		if (dir == AMDTP_IN_STREAM) {
258 			err = snd_dice_transaction_write_tx(dice,
259 					params->size * i + TX_ISOCHRONOUS,
260 					reg, sizeof(reg[0]));
261 		} else {
262 			err = snd_dice_transaction_write_rx(dice,
263 					params->size * i + RX_ISOCHRONOUS,
264 					reg, sizeof(reg[0]));
265 		}
266 		if (err < 0)
267 			return err;
268 
269 		if (dir == AMDTP_IN_STREAM) {
270 			reg[0] = cpu_to_be32(fw_dev->max_speed);
271 			err = snd_dice_transaction_write_tx(dice,
272 					params->size * i + TX_SPEED,
273 					reg, sizeof(reg[0]));
274 			if (err < 0)
275 				return err;
276 		}
277 
278 		err = amdtp_stream_start(&streams[i], resources[i].channel,
279 					 fw_dev->max_speed);
280 		if (err < 0)
281 			return err;
282 	}
283 
284 	return err;
285 }
286 
287 static int start_duplex_streams(struct snd_dice *dice, unsigned int rate)
288 {
289 	struct reg_params tx_params, rx_params;
290 	int i;
291 	int err;
292 
293 	err = get_register_params(dice, &tx_params, &rx_params);
294 	if (err < 0)
295 		return err;
296 
297 	/* Stop transmission. */
298 	stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
299 	stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
300 	snd_dice_transaction_clear_enable(dice);
301 	release_resources(dice);
302 
303 	err = ensure_phase_lock(dice);
304 	if (err < 0) {
305 		dev_err(&dice->unit->device, "fail to ensure phase lock\n");
306 		return err;
307 	}
308 
309 	/* Start both streams. */
310 	err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params);
311 	if (err < 0)
312 		goto error;
313 	err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params);
314 	if (err < 0)
315 		goto error;
316 
317 	err = snd_dice_transaction_set_enable(dice);
318 	if (err < 0) {
319 		dev_err(&dice->unit->device, "fail to enable interface\n");
320 		goto error;
321 	}
322 
323 	for (i = 0; i < MAX_STREAMS; i++) {
324 		if ((i < tx_params.count &&
325 		    !amdtp_stream_wait_callback(&dice->tx_stream[i],
326 						CALLBACK_TIMEOUT)) ||
327 		    (i < rx_params.count &&
328 		     !amdtp_stream_wait_callback(&dice->rx_stream[i],
329 						 CALLBACK_TIMEOUT))) {
330 			err = -ETIMEDOUT;
331 			goto error;
332 		}
333 	}
334 
335 	return 0;
336 error:
337 	stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
338 	stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
339 	snd_dice_transaction_clear_enable(dice);
340 	release_resources(dice);
341 	return err;
342 }
343 
344 /*
345  * MEMO: After this function, there're two states of streams:
346  *  - None streams are running.
347  *  - All streams are running.
348  */
349 int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate)
350 {
351 	unsigned int curr_rate;
352 	unsigned int i;
353 	enum snd_dice_rate_mode mode;
354 	int err;
355 
356 	if (dice->substreams_counter == 0)
357 		return -EIO;
358 
359 	/* Check sampling transmission frequency. */
360 	err = snd_dice_transaction_get_rate(dice, &curr_rate);
361 	if (err < 0) {
362 		dev_err(&dice->unit->device,
363 			"fail to get sampling rate\n");
364 		return err;
365 	}
366 	if (rate == 0)
367 		rate = curr_rate;
368 	if (rate != curr_rate)
369 		return -EINVAL;
370 
371 	/* Check error of packet streaming. */
372 	for (i = 0; i < MAX_STREAMS; ++i) {
373 		if (amdtp_streaming_error(&dice->tx_stream[i]))
374 			break;
375 		if (amdtp_streaming_error(&dice->rx_stream[i]))
376 			break;
377 	}
378 	if (i < MAX_STREAMS)
379 		goto restart;
380 
381 	/* Check required streams are running or not. */
382 	err = snd_dice_stream_get_rate_mode(dice, rate, &mode);
383 	if (err < 0)
384 		return err;
385 	for (i = 0; i < MAX_STREAMS; ++i) {
386 		if (dice->tx_pcm_chs[i][mode] > 0 &&
387 		    !amdtp_stream_running(&dice->tx_stream[i]))
388 			break;
389 		if (dice->rx_pcm_chs[i][mode] > 0 &&
390 		    !amdtp_stream_running(&dice->rx_stream[i]))
391 			break;
392 	}
393 	if (i < MAX_STREAMS)
394 		goto restart;
395 
396 	return 0;
397 restart:
398 	return start_duplex_streams(dice, rate);
399 }
400 
401 /*
402  * MEMO: After this function, there're two states of streams:
403  *  - None streams are running.
404  *  - All streams are running.
405  */
406 void snd_dice_stream_stop_duplex(struct snd_dice *dice)
407 {
408 	struct reg_params tx_params, rx_params;
409 
410 	if (dice->substreams_counter > 0)
411 		return;
412 
413 	snd_dice_transaction_clear_enable(dice);
414 
415 	if (get_register_params(dice, &tx_params, &rx_params) == 0) {
416 		stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
417 		stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
418 	}
419 
420 	release_resources(dice);
421 }
422 
423 static int init_stream(struct snd_dice *dice, enum amdtp_stream_direction dir,
424 		       unsigned int index)
425 {
426 	struct amdtp_stream *stream;
427 	struct fw_iso_resources *resources;
428 	int err;
429 
430 	if (dir == AMDTP_IN_STREAM) {
431 		stream = &dice->tx_stream[index];
432 		resources = &dice->tx_resources[index];
433 	} else {
434 		stream = &dice->rx_stream[index];
435 		resources = &dice->rx_resources[index];
436 	}
437 
438 	err = fw_iso_resources_init(resources, dice->unit);
439 	if (err < 0)
440 		goto end;
441 	resources->channels_mask = 0x00000000ffffffffuLL;
442 
443 	err = amdtp_am824_init(stream, dice->unit, dir, CIP_BLOCKING);
444 	if (err < 0) {
445 		amdtp_stream_destroy(stream);
446 		fw_iso_resources_destroy(resources);
447 	}
448 end:
449 	return err;
450 }
451 
452 /*
453  * This function should be called before starting streams or after stopping
454  * streams.
455  */
456 static void destroy_stream(struct snd_dice *dice,
457 			   enum amdtp_stream_direction dir,
458 			   unsigned int index)
459 {
460 	struct amdtp_stream *stream;
461 	struct fw_iso_resources *resources;
462 
463 	if (dir == AMDTP_IN_STREAM) {
464 		stream = &dice->tx_stream[index];
465 		resources = &dice->tx_resources[index];
466 	} else {
467 		stream = &dice->rx_stream[index];
468 		resources = &dice->rx_resources[index];
469 	}
470 
471 	amdtp_stream_destroy(stream);
472 	fw_iso_resources_destroy(resources);
473 }
474 
475 int snd_dice_stream_init_duplex(struct snd_dice *dice)
476 {
477 	int i, err;
478 
479 	for (i = 0; i < MAX_STREAMS; i++) {
480 		err = init_stream(dice, AMDTP_IN_STREAM, i);
481 		if (err < 0) {
482 			for (; i >= 0; i--)
483 				destroy_stream(dice, AMDTP_OUT_STREAM, i);
484 			goto end;
485 		}
486 	}
487 
488 	for (i = 0; i < MAX_STREAMS; i++) {
489 		err = init_stream(dice, AMDTP_OUT_STREAM, i);
490 		if (err < 0) {
491 			for (; i >= 0; i--)
492 				destroy_stream(dice, AMDTP_OUT_STREAM, i);
493 			for (i = 0; i < MAX_STREAMS; i++)
494 				destroy_stream(dice, AMDTP_IN_STREAM, i);
495 			break;
496 		}
497 	}
498 end:
499 	return err;
500 }
501 
502 void snd_dice_stream_destroy_duplex(struct snd_dice *dice)
503 {
504 	unsigned int i;
505 
506 	for (i = 0; i < MAX_STREAMS; i++) {
507 		destroy_stream(dice, AMDTP_IN_STREAM, i);
508 		destroy_stream(dice, AMDTP_OUT_STREAM, i);
509 	}
510 }
511 
512 void snd_dice_stream_update_duplex(struct snd_dice *dice)
513 {
514 	struct reg_params tx_params, rx_params;
515 
516 	/*
517 	 * On a bus reset, the DICE firmware disables streaming and then goes
518 	 * off contemplating its own navel for hundreds of milliseconds before
519 	 * it can react to any of our attempts to reenable streaming.  This
520 	 * means that we lose synchronization anyway, so we force our streams
521 	 * to stop so that the application can restart them in an orderly
522 	 * manner.
523 	 */
524 	dice->global_enabled = false;
525 
526 	if (get_register_params(dice, &tx_params, &rx_params) == 0) {
527 		stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
528 		stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
529 	}
530 }
531 
532 int snd_dice_stream_detect_current_formats(struct snd_dice *dice)
533 {
534 	unsigned int rate;
535 	enum snd_dice_rate_mode mode;
536 	__be32 reg[2];
537 	struct reg_params tx_params, rx_params;
538 	int i;
539 	int err;
540 
541 	/* If extended protocol is available, detect detail spec. */
542 	err = snd_dice_detect_extension_formats(dice);
543 	if (err >= 0)
544 		return err;
545 
546 	/*
547 	 * Available stream format is restricted at current mode of sampling
548 	 * clock.
549 	 */
550 	err = snd_dice_transaction_get_rate(dice, &rate);
551 	if (err < 0)
552 		return err;
553 
554 	err = snd_dice_stream_get_rate_mode(dice, rate, &mode);
555 	if (err < 0)
556 		return err;
557 
558 	/*
559 	 * Just after owning the unit (GLOBAL_OWNER), the unit can return
560 	 * invalid stream formats. Selecting clock parameters have an effect
561 	 * for the unit to refine it.
562 	 */
563 	err = ensure_phase_lock(dice);
564 	if (err < 0)
565 		return err;
566 
567 	err = get_register_params(dice, &tx_params, &rx_params);
568 	if (err < 0)
569 		return err;
570 
571 	for (i = 0; i < tx_params.count; ++i) {
572 		err = snd_dice_transaction_read_tx(dice,
573 				tx_params.size * i + TX_NUMBER_AUDIO,
574 				reg, sizeof(reg));
575 		if (err < 0)
576 			return err;
577 		dice->tx_pcm_chs[i][mode] = be32_to_cpu(reg[0]);
578 		dice->tx_midi_ports[i] = max_t(unsigned int,
579 				be32_to_cpu(reg[1]), dice->tx_midi_ports[i]);
580 	}
581 	for (i = 0; i < rx_params.count; ++i) {
582 		err = snd_dice_transaction_read_rx(dice,
583 				rx_params.size * i + RX_NUMBER_AUDIO,
584 				reg, sizeof(reg));
585 		if (err < 0)
586 			return err;
587 		dice->rx_pcm_chs[i][mode] = be32_to_cpu(reg[0]);
588 		dice->rx_midi_ports[i] = max_t(unsigned int,
589 				be32_to_cpu(reg[1]), dice->rx_midi_ports[i]);
590 	}
591 
592 	return 0;
593 }
594 
595 static void dice_lock_changed(struct snd_dice *dice)
596 {
597 	dice->dev_lock_changed = true;
598 	wake_up(&dice->hwdep_wait);
599 }
600 
601 int snd_dice_stream_lock_try(struct snd_dice *dice)
602 {
603 	int err;
604 
605 	spin_lock_irq(&dice->lock);
606 
607 	if (dice->dev_lock_count < 0) {
608 		err = -EBUSY;
609 		goto out;
610 	}
611 
612 	if (dice->dev_lock_count++ == 0)
613 		dice_lock_changed(dice);
614 	err = 0;
615 out:
616 	spin_unlock_irq(&dice->lock);
617 	return err;
618 }
619 
620 void snd_dice_stream_lock_release(struct snd_dice *dice)
621 {
622 	spin_lock_irq(&dice->lock);
623 
624 	if (WARN_ON(dice->dev_lock_count <= 0))
625 		goto out;
626 
627 	if (--dice->dev_lock_count == 0)
628 		dice_lock_changed(dice);
629 out:
630 	spin_unlock_irq(&dice->lock);
631 }
632