1 /* 2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c 3 * which contain: 4 * 5 * Author: Nicolas Pitre 6 * Created: Dec 02, 2004 7 * Copyright: MontaVista Software Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/platform_device.h> 16 #include <linux/interrupt.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 20 #include <sound/ac97_codec.h> 21 #include <sound/pxa2xx-lib.h> 22 23 #include <asm/irq.h> 24 #include <mach/regs-ac97.h> 25 #include <mach/pxa2xx-gpio.h> 26 #include <mach/audio.h> 27 28 static DEFINE_MUTEX(car_mutex); 29 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); 30 static volatile long gsr_bits; 31 static struct clk *ac97_clk; 32 static struct clk *ac97conf_clk; 33 static int reset_gpio; 34 35 /* 36 * Beware PXA27x bugs: 37 * 38 * o Slot 12 read from modem space will hang controller. 39 * o CDONE, SDONE interrupt fails after any slot 12 IO. 40 * 41 * We therefore have an hybrid approach for waiting on SDONE (interrupt or 42 * 1 jiffy timeout if interrupt never comes). 43 */ 44 45 enum { 46 RESETGPIO_FORCE_HIGH, 47 RESETGPIO_FORCE_LOW, 48 RESETGPIO_NORMAL_ALTFUNC 49 }; 50 51 /** 52 * set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA 53 * @mode: chosen action 54 * 55 * As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line 56 * must be done to insure proper work of AC97 reset line. This function 57 * computes the correct gpio_mode for further use by reset functions, and 58 * applied the change through pxa_gpio_mode. 59 */ 60 static void set_resetgpio_mode(int resetgpio_action) 61 { 62 int mode = 0; 63 64 if (reset_gpio) 65 switch (resetgpio_action) { 66 case RESETGPIO_NORMAL_ALTFUNC: 67 if (reset_gpio == 113) 68 mode = 113 | GPIO_OUT | GPIO_DFLT_LOW; 69 if (reset_gpio == 95) 70 mode = 95 | GPIO_ALT_FN_1_OUT; 71 break; 72 case RESETGPIO_FORCE_LOW: 73 mode = reset_gpio | GPIO_OUT | GPIO_DFLT_LOW; 74 break; 75 case RESETGPIO_FORCE_HIGH: 76 mode = reset_gpio | GPIO_OUT | GPIO_DFLT_HIGH; 77 break; 78 }; 79 80 if (mode) 81 pxa_gpio_mode(mode); 82 } 83 84 unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 85 { 86 unsigned short val = -1; 87 volatile u32 *reg_addr; 88 89 mutex_lock(&car_mutex); 90 91 /* set up primary or secondary codec space */ 92 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) 93 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 94 else 95 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 96 reg_addr += (reg >> 1); 97 98 /* start read access across the ac97 link */ 99 GSR = GSR_CDONE | GSR_SDONE; 100 gsr_bits = 0; 101 val = *reg_addr; 102 if (reg == AC97_GPIO_STATUS) 103 goto out; 104 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 && 105 !((GSR | gsr_bits) & GSR_SDONE)) { 106 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n", 107 __func__, reg, GSR | gsr_bits); 108 val = -1; 109 goto out; 110 } 111 112 /* valid data now */ 113 GSR = GSR_CDONE | GSR_SDONE; 114 gsr_bits = 0; 115 val = *reg_addr; 116 /* but we've just started another cycle... */ 117 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 118 119 out: mutex_unlock(&car_mutex); 120 return val; 121 } 122 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read); 123 124 void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 125 unsigned short val) 126 { 127 volatile u32 *reg_addr; 128 129 mutex_lock(&car_mutex); 130 131 /* set up primary or secondary codec space */ 132 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) 133 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 134 else 135 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 136 reg_addr += (reg >> 1); 137 138 GSR = GSR_CDONE | GSR_SDONE; 139 gsr_bits = 0; 140 *reg_addr = val; 141 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 && 142 !((GSR | gsr_bits) & GSR_CDONE)) 143 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n", 144 __func__, reg, GSR | gsr_bits); 145 146 mutex_unlock(&car_mutex); 147 } 148 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write); 149 150 #ifdef CONFIG_PXA25x 151 static inline void pxa_ac97_warm_pxa25x(void) 152 { 153 gsr_bits = 0; 154 155 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN; 156 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 157 } 158 159 static inline void pxa_ac97_cold_pxa25x(void) 160 { 161 GCR &= GCR_COLD_RST; /* clear everything but nCRST */ 162 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ 163 164 gsr_bits = 0; 165 166 GCR = GCR_COLD_RST; 167 GCR |= GCR_CDONE_IE|GCR_SDONE_IE; 168 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 169 } 170 #endif 171 172 #ifdef CONFIG_PXA27x 173 static inline void pxa_ac97_warm_pxa27x(void) 174 { 175 gsr_bits = 0; 176 177 /* warm reset broken on Bulverde, 178 so manually keep AC97 reset high */ 179 set_resetgpio_mode(RESETGPIO_FORCE_HIGH); 180 udelay(10); 181 GCR |= GCR_WARM_RST; 182 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC); 183 udelay(500); 184 } 185 186 static inline void pxa_ac97_cold_pxa27x(void) 187 { 188 GCR &= GCR_COLD_RST; /* clear everything but nCRST */ 189 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ 190 191 gsr_bits = 0; 192 193 /* PXA27x Developers Manual section 13.5.2.2.1 */ 194 clk_enable(ac97conf_clk); 195 udelay(5); 196 clk_disable(ac97conf_clk); 197 GCR = GCR_COLD_RST; 198 udelay(50); 199 } 200 #endif 201 202 #ifdef CONFIG_PXA3xx 203 static inline void pxa_ac97_warm_pxa3xx(void) 204 { 205 int timeout = 100; 206 207 gsr_bits = 0; 208 209 /* Can't use interrupts */ 210 GCR |= GCR_WARM_RST; 211 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) 212 mdelay(1); 213 } 214 215 static inline void pxa_ac97_cold_pxa3xx(void) 216 { 217 int timeout = 1000; 218 219 /* Hold CLKBPB for 100us */ 220 GCR = 0; 221 GCR = GCR_CLKBPB; 222 udelay(100); 223 GCR = 0; 224 225 GCR &= GCR_COLD_RST; /* clear everything but nCRST */ 226 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ 227 228 gsr_bits = 0; 229 230 /* Can't use interrupts on PXA3xx */ 231 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 232 233 GCR = GCR_WARM_RST | GCR_COLD_RST; 234 while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--) 235 mdelay(10); 236 } 237 #endif 238 239 bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97) 240 { 241 #ifdef CONFIG_PXA25x 242 if (cpu_is_pxa25x()) 243 pxa_ac97_warm_pxa25x(); 244 else 245 #endif 246 #ifdef CONFIG_PXA27x 247 if (cpu_is_pxa27x()) 248 pxa_ac97_warm_pxa27x(); 249 else 250 #endif 251 #ifdef CONFIG_PXA3xx 252 if (cpu_is_pxa3xx()) 253 pxa_ac97_warm_pxa3xx(); 254 else 255 #endif 256 BUG(); 257 258 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) { 259 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", 260 __func__, gsr_bits); 261 262 return false; 263 } 264 265 return true; 266 } 267 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset); 268 269 bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97) 270 { 271 #ifdef CONFIG_PXA25x 272 if (cpu_is_pxa25x()) 273 pxa_ac97_cold_pxa25x(); 274 else 275 #endif 276 #ifdef CONFIG_PXA27x 277 if (cpu_is_pxa27x()) 278 pxa_ac97_cold_pxa27x(); 279 else 280 #endif 281 #ifdef CONFIG_PXA3xx 282 if (cpu_is_pxa3xx()) 283 pxa_ac97_cold_pxa3xx(); 284 else 285 #endif 286 BUG(); 287 288 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) { 289 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", 290 __func__, gsr_bits); 291 292 return false; 293 } 294 295 return true; 296 } 297 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset); 298 299 300 void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97) 301 { 302 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 303 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 304 } 305 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset); 306 307 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) 308 { 309 long status; 310 311 status = GSR; 312 if (status) { 313 GSR = status; 314 gsr_bits |= status; 315 wake_up(&gsr_wq); 316 317 /* Although we don't use those we still need to clear them 318 since they tend to spuriously trigger when MMC is used 319 (hardware bug? go figure)... */ 320 if (cpu_is_pxa27x()) { 321 MISR = MISR_EOC; 322 PISR = PISR_EOC; 323 MCSR = MCSR_EOC; 324 } 325 326 return IRQ_HANDLED; 327 } 328 329 return IRQ_NONE; 330 } 331 332 #ifdef CONFIG_PM 333 int pxa2xx_ac97_hw_suspend(void) 334 { 335 GCR |= GCR_ACLINK_OFF; 336 clk_disable(ac97_clk); 337 return 0; 338 } 339 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend); 340 341 int pxa2xx_ac97_hw_resume(void) 342 { 343 if (cpu_is_pxa25x() || cpu_is_pxa27x()) { 344 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 345 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 346 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 347 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 348 } 349 if (cpu_is_pxa27x()) { 350 /* Use GPIO 113 or 95 as AC97 Reset on Bulverde */ 351 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC); 352 } 353 clk_enable(ac97_clk); 354 return 0; 355 } 356 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume); 357 #endif 358 359 int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev) 360 { 361 int ret; 362 struct pxa2xx_ac97_platform_data *pdata = dev->dev.platform_data; 363 364 if (pdata) { 365 switch (pdata->reset_gpio) { 366 case 95: 367 case 113: 368 reset_gpio = pdata->reset_gpio; 369 break; 370 case 0: 371 reset_gpio = 113; 372 break; 373 case -1: 374 break; 375 default: 376 dev_err(&dev->dev, "Invalid reset GPIO %d\n", 377 pdata->reset_gpio); 378 } 379 } else { 380 if (cpu_is_pxa27x()) 381 reset_gpio = 113; 382 } 383 384 if (cpu_is_pxa25x() || cpu_is_pxa27x()) { 385 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 386 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 387 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 388 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 389 } 390 391 if (cpu_is_pxa27x()) { 392 /* Use GPIO 113 as AC97 Reset on Bulverde */ 393 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC); 394 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK"); 395 if (IS_ERR(ac97conf_clk)) { 396 ret = PTR_ERR(ac97conf_clk); 397 ac97conf_clk = NULL; 398 goto err_conf; 399 } 400 } 401 402 ac97_clk = clk_get(&dev->dev, "AC97CLK"); 403 if (IS_ERR(ac97_clk)) { 404 ret = PTR_ERR(ac97_clk); 405 ac97_clk = NULL; 406 goto err_clk; 407 } 408 409 ret = clk_enable(ac97_clk); 410 if (ret) 411 goto err_clk2; 412 413 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); 414 if (ret < 0) 415 goto err_irq; 416 417 return 0; 418 419 err_irq: 420 GCR |= GCR_ACLINK_OFF; 421 err_clk2: 422 clk_put(ac97_clk); 423 ac97_clk = NULL; 424 err_clk: 425 if (ac97conf_clk) { 426 clk_put(ac97conf_clk); 427 ac97conf_clk = NULL; 428 } 429 err_conf: 430 return ret; 431 } 432 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe); 433 434 void pxa2xx_ac97_hw_remove(struct platform_device *dev) 435 { 436 GCR |= GCR_ACLINK_OFF; 437 free_irq(IRQ_AC97, NULL); 438 if (ac97conf_clk) { 439 clk_put(ac97conf_clk); 440 ac97conf_clk = NULL; 441 } 442 clk_disable(ac97_clk); 443 clk_put(ac97_clk); 444 ac97_clk = NULL; 445 } 446 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove); 447 448 MODULE_AUTHOR("Nicolas Pitre"); 449 MODULE_DESCRIPTION("Intel/Marvell PXA sound library"); 450 MODULE_LICENSE("GPL"); 451 452