1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. 6 * 7 * Documentation: ARM DDI 0173B 8 */ 9 #include <linux/module.h> 10 #include <linux/delay.h> 11 #include <linux/init.h> 12 #include <linux/ioport.h> 13 #include <linux/device.h> 14 #include <linux/spinlock.h> 15 #include <linux/interrupt.h> 16 #include <linux/err.h> 17 #include <linux/amba/bus.h> 18 #include <linux/io.h> 19 20 #include <sound/core.h> 21 #include <sound/initval.h> 22 #include <sound/ac97_codec.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 26 #include "aaci.h" 27 28 #define DRIVER_NAME "aaci-pl041" 29 30 #define FRAME_PERIOD_US 21 31 32 /* 33 * PM support is not complete. Turn it off. 34 */ 35 #undef CONFIG_PM 36 37 static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) 38 { 39 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); 40 41 /* 42 * Ensure that the slot 1/2 RX registers are empty. 43 */ 44 v = readl(aaci->base + AACI_SLFR); 45 if (v & SLFR_2RXV) 46 readl(aaci->base + AACI_SL2RX); 47 if (v & SLFR_1RXV) 48 readl(aaci->base + AACI_SL1RX); 49 50 if (maincr != readl(aaci->base + AACI_MAINCR)) { 51 writel(maincr, aaci->base + AACI_MAINCR); 52 readl(aaci->base + AACI_MAINCR); 53 udelay(1); 54 } 55 } 56 57 /* 58 * P29: 59 * The recommended use of programming the external codec through slot 1 60 * and slot 2 data is to use the channels during setup routines and the 61 * slot register at any other time. The data written into slot 1, slot 2 62 * and slot 12 registers is transmitted only when their corresponding 63 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR 64 * register. 65 */ 66 static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 67 unsigned short val) 68 { 69 struct aaci *aaci = ac97->private_data; 70 int timeout; 71 u32 v; 72 73 if (ac97->num >= 4) 74 return; 75 76 mutex_lock(&aaci->ac97_sem); 77 78 aaci_ac97_select_codec(aaci, ac97); 79 80 /* 81 * P54: You must ensure that AACI_SL2TX is always written 82 * to, if required, before data is written to AACI_SL1TX. 83 */ 84 writel(val << 4, aaci->base + AACI_SL2TX); 85 writel(reg << 12, aaci->base + AACI_SL1TX); 86 87 /* Initially, wait one frame period */ 88 udelay(FRAME_PERIOD_US); 89 90 /* And then wait an additional eight frame periods for it to be sent */ 91 timeout = FRAME_PERIOD_US * 8; 92 do { 93 udelay(1); 94 v = readl(aaci->base + AACI_SLFR); 95 } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout); 96 97 if (v & (SLFR_1TXB|SLFR_2TXB)) 98 dev_err(&aaci->dev->dev, 99 "timeout waiting for write to complete\n"); 100 101 mutex_unlock(&aaci->ac97_sem); 102 } 103 104 /* 105 * Read an AC'97 register. 106 */ 107 static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 108 { 109 struct aaci *aaci = ac97->private_data; 110 int timeout, retries = 10; 111 u32 v; 112 113 if (ac97->num >= 4) 114 return ~0; 115 116 mutex_lock(&aaci->ac97_sem); 117 118 aaci_ac97_select_codec(aaci, ac97); 119 120 /* 121 * Write the register address to slot 1. 122 */ 123 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); 124 125 /* Initially, wait one frame period */ 126 udelay(FRAME_PERIOD_US); 127 128 /* And then wait an additional eight frame periods for it to be sent */ 129 timeout = FRAME_PERIOD_US * 8; 130 do { 131 udelay(1); 132 v = readl(aaci->base + AACI_SLFR); 133 } while ((v & SLFR_1TXB) && --timeout); 134 135 if (v & SLFR_1TXB) { 136 dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n"); 137 v = ~0; 138 goto out; 139 } 140 141 /* Now wait for the response frame */ 142 udelay(FRAME_PERIOD_US); 143 144 /* And then wait an additional eight frame periods for data */ 145 timeout = FRAME_PERIOD_US * 8; 146 do { 147 udelay(1); 148 cond_resched(); 149 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); 150 } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout); 151 152 if (v != (SLFR_1RXV|SLFR_2RXV)) { 153 dev_err(&aaci->dev->dev, "timeout on RX valid\n"); 154 v = ~0; 155 goto out; 156 } 157 158 do { 159 v = readl(aaci->base + AACI_SL1RX) >> 12; 160 if (v == reg) { 161 v = readl(aaci->base + AACI_SL2RX) >> 4; 162 break; 163 } else if (--retries) { 164 dev_warn(&aaci->dev->dev, 165 "ac97 read back fail. retry\n"); 166 continue; 167 } else { 168 dev_warn(&aaci->dev->dev, 169 "wrong ac97 register read back (%x != %x)\n", 170 v, reg); 171 v = ~0; 172 } 173 } while (retries); 174 out: 175 mutex_unlock(&aaci->ac97_sem); 176 return v; 177 } 178 179 static inline void 180 aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask) 181 { 182 u32 val; 183 int timeout = 5000; 184 185 do { 186 udelay(1); 187 val = readl(aacirun->base + AACI_SR); 188 } while (val & mask && timeout--); 189 } 190 191 192 193 /* 194 * Interrupt support. 195 */ 196 static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask) 197 { 198 if (mask & ISR_ORINTR) { 199 dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel); 200 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); 201 } 202 203 if (mask & ISR_RXTOINTR) { 204 dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel); 205 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); 206 } 207 208 if (mask & ISR_RXINTR) { 209 struct aaci_runtime *aacirun = &aaci->capture; 210 bool period_elapsed = false; 211 void *ptr; 212 213 if (!aacirun->substream || !aacirun->start) { 214 dev_warn(&aaci->dev->dev, "RX interrupt???\n"); 215 writel(0, aacirun->base + AACI_IE); 216 return; 217 } 218 219 spin_lock(&aacirun->lock); 220 221 ptr = aacirun->ptr; 222 do { 223 unsigned int len = aacirun->fifo_bytes; 224 u32 val; 225 226 if (aacirun->bytes <= 0) { 227 aacirun->bytes += aacirun->period; 228 period_elapsed = true; 229 } 230 if (!(aacirun->cr & CR_EN)) 231 break; 232 233 val = readl(aacirun->base + AACI_SR); 234 if (!(val & SR_RXHF)) 235 break; 236 if (!(val & SR_RXFF)) 237 len >>= 1; 238 239 aacirun->bytes -= len; 240 241 /* reading 16 bytes at a time */ 242 for( ; len > 0; len -= 16) { 243 asm( 244 "ldmia %1, {r0, r1, r2, r3}\n\t" 245 "stmia %0!, {r0, r1, r2, r3}" 246 : "+r" (ptr) 247 : "r" (aacirun->fifo) 248 : "r0", "r1", "r2", "r3", "cc"); 249 250 if (ptr >= aacirun->end) 251 ptr = aacirun->start; 252 } 253 } while(1); 254 255 aacirun->ptr = ptr; 256 257 spin_unlock(&aacirun->lock); 258 259 if (period_elapsed) 260 snd_pcm_period_elapsed(aacirun->substream); 261 } 262 263 if (mask & ISR_URINTR) { 264 dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel); 265 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); 266 } 267 268 if (mask & ISR_TXINTR) { 269 struct aaci_runtime *aacirun = &aaci->playback; 270 bool period_elapsed = false; 271 void *ptr; 272 273 if (!aacirun->substream || !aacirun->start) { 274 dev_warn(&aaci->dev->dev, "TX interrupt???\n"); 275 writel(0, aacirun->base + AACI_IE); 276 return; 277 } 278 279 spin_lock(&aacirun->lock); 280 281 ptr = aacirun->ptr; 282 do { 283 unsigned int len = aacirun->fifo_bytes; 284 u32 val; 285 286 if (aacirun->bytes <= 0) { 287 aacirun->bytes += aacirun->period; 288 period_elapsed = true; 289 } 290 if (!(aacirun->cr & CR_EN)) 291 break; 292 293 val = readl(aacirun->base + AACI_SR); 294 if (!(val & SR_TXHE)) 295 break; 296 if (!(val & SR_TXFE)) 297 len >>= 1; 298 299 aacirun->bytes -= len; 300 301 /* writing 16 bytes at a time */ 302 for ( ; len > 0; len -= 16) { 303 asm( 304 "ldmia %0!, {r0, r1, r2, r3}\n\t" 305 "stmia %1, {r0, r1, r2, r3}" 306 : "+r" (ptr) 307 : "r" (aacirun->fifo) 308 : "r0", "r1", "r2", "r3", "cc"); 309 310 if (ptr >= aacirun->end) 311 ptr = aacirun->start; 312 } 313 } while (1); 314 315 aacirun->ptr = ptr; 316 317 spin_unlock(&aacirun->lock); 318 319 if (period_elapsed) 320 snd_pcm_period_elapsed(aacirun->substream); 321 } 322 } 323 324 static irqreturn_t aaci_irq(int irq, void *devid) 325 { 326 struct aaci *aaci = devid; 327 u32 mask; 328 int i; 329 330 mask = readl(aaci->base + AACI_ALLINTS); 331 if (mask) { 332 u32 m = mask; 333 for (i = 0; i < 4; i++, m >>= 7) { 334 if (m & 0x7f) { 335 aaci_fifo_irq(aaci, i, m); 336 } 337 } 338 } 339 340 return mask ? IRQ_HANDLED : IRQ_NONE; 341 } 342 343 344 345 /* 346 * ALSA support. 347 */ 348 static const struct snd_pcm_hardware aaci_hw_info = { 349 .info = SNDRV_PCM_INFO_MMAP | 350 SNDRV_PCM_INFO_MMAP_VALID | 351 SNDRV_PCM_INFO_INTERLEAVED | 352 SNDRV_PCM_INFO_BLOCK_TRANSFER | 353 SNDRV_PCM_INFO_RESUME, 354 355 /* 356 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit 357 * words. It also doesn't support 12-bit at all. 358 */ 359 .formats = SNDRV_PCM_FMTBIT_S16_LE, 360 361 /* rates are setup from the AC'97 codec */ 362 .channels_min = 2, 363 .channels_max = 2, 364 .buffer_bytes_max = 64 * 1024, 365 .period_bytes_min = 256, 366 .period_bytes_max = PAGE_SIZE, 367 .periods_min = 4, 368 .periods_max = PAGE_SIZE / 16, 369 }; 370 371 /* 372 * We can support two and four channel audio. Unfortunately 373 * six channel audio requires a non-standard channel ordering: 374 * 2 -> FL(3), FR(4) 375 * 4 -> FL(3), FR(4), SL(7), SR(8) 376 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) 377 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual) 378 * This requires an ALSA configuration file to correct. 379 */ 380 static int aaci_rule_channels(struct snd_pcm_hw_params *p, 381 struct snd_pcm_hw_rule *rule) 382 { 383 static unsigned int channel_list[] = { 2, 4, 6 }; 384 struct aaci *aaci = rule->private; 385 unsigned int mask = 1 << 0, slots; 386 387 /* pcms[0] is the our 5.1 PCM instance. */ 388 slots = aaci->ac97_bus->pcms[0].r[0].slots; 389 if (slots & (1 << AC97_SLOT_PCM_SLEFT)) { 390 mask |= 1 << 1; 391 if (slots & (1 << AC97_SLOT_LFE)) 392 mask |= 1 << 2; 393 } 394 395 return snd_interval_list(hw_param_interval(p, rule->var), 396 ARRAY_SIZE(channel_list), channel_list, mask); 397 } 398 399 static int aaci_pcm_open(struct snd_pcm_substream *substream) 400 { 401 struct snd_pcm_runtime *runtime = substream->runtime; 402 struct aaci *aaci = substream->private_data; 403 struct aaci_runtime *aacirun; 404 int ret = 0; 405 406 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 407 aacirun = &aaci->playback; 408 } else { 409 aacirun = &aaci->capture; 410 } 411 412 aacirun->substream = substream; 413 runtime->private_data = aacirun; 414 runtime->hw = aaci_hw_info; 415 runtime->hw.rates = aacirun->pcm->rates; 416 snd_pcm_limit_hw_rates(runtime); 417 418 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 419 runtime->hw.channels_max = 6; 420 421 /* Add rule describing channel dependency. */ 422 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 423 SNDRV_PCM_HW_PARAM_CHANNELS, 424 aaci_rule_channels, aaci, 425 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 426 if (ret) 427 return ret; 428 429 if (aacirun->pcm->r[1].slots) 430 snd_ac97_pcm_double_rate_rules(runtime); 431 } 432 433 /* 434 * ALSA wants the byte-size of the FIFOs. As we only support 435 * 16-bit samples, this is twice the FIFO depth irrespective 436 * of whether it's in compact mode or not. 437 */ 438 runtime->hw.fifo_size = aaci->fifo_depth * 2; 439 440 mutex_lock(&aaci->irq_lock); 441 if (!aaci->users++) { 442 ret = request_irq(aaci->dev->irq[0], aaci_irq, 443 IRQF_SHARED, DRIVER_NAME, aaci); 444 if (ret != 0) 445 aaci->users--; 446 } 447 mutex_unlock(&aaci->irq_lock); 448 449 return ret; 450 } 451 452 453 /* 454 * Common ALSA stuff 455 */ 456 static int aaci_pcm_close(struct snd_pcm_substream *substream) 457 { 458 struct aaci *aaci = substream->private_data; 459 struct aaci_runtime *aacirun = substream->runtime->private_data; 460 461 WARN_ON(aacirun->cr & CR_EN); 462 463 aacirun->substream = NULL; 464 465 mutex_lock(&aaci->irq_lock); 466 if (!--aaci->users) 467 free_irq(aaci->dev->irq[0], aaci); 468 mutex_unlock(&aaci->irq_lock); 469 470 return 0; 471 } 472 473 static int aaci_pcm_hw_free(struct snd_pcm_substream *substream) 474 { 475 struct aaci_runtime *aacirun = substream->runtime->private_data; 476 477 /* 478 * This must not be called with the device enabled. 479 */ 480 WARN_ON(aacirun->cr & CR_EN); 481 482 if (aacirun->pcm_open) 483 snd_ac97_pcm_close(aacirun->pcm); 484 aacirun->pcm_open = 0; 485 486 return 0; 487 } 488 489 /* Channel to slot mask */ 490 static const u32 channels_to_slotmask[] = { 491 [2] = CR_SL3 | CR_SL4, 492 [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8, 493 [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9, 494 }; 495 496 static int aaci_pcm_hw_params(struct snd_pcm_substream *substream, 497 struct snd_pcm_hw_params *params) 498 { 499 struct aaci_runtime *aacirun = substream->runtime->private_data; 500 struct aaci *aaci = substream->private_data; 501 unsigned int channels = params_channels(params); 502 unsigned int rate = params_rate(params); 503 int dbl = rate > 48000; 504 int err; 505 506 aaci_pcm_hw_free(substream); 507 if (aacirun->pcm_open) { 508 snd_ac97_pcm_close(aacirun->pcm); 509 aacirun->pcm_open = 0; 510 } 511 512 /* channels is already limited to 2, 4, or 6 by aaci_rule_channels */ 513 if (dbl && channels != 2) 514 return -EINVAL; 515 516 err = snd_ac97_pcm_open(aacirun->pcm, rate, channels, 517 aacirun->pcm->r[dbl].slots); 518 519 aacirun->pcm_open = err == 0; 520 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; 521 aacirun->cr |= channels_to_slotmask[channels + dbl * 2]; 522 523 /* 524 * fifo_bytes is the number of bytes we transfer to/from 525 * the FIFO, including padding. So that's x4. As we're 526 * in compact mode, the FIFO is half the size. 527 */ 528 aacirun->fifo_bytes = aaci->fifo_depth * 4 / 2; 529 530 return err; 531 } 532 533 static int aaci_pcm_prepare(struct snd_pcm_substream *substream) 534 { 535 struct snd_pcm_runtime *runtime = substream->runtime; 536 struct aaci_runtime *aacirun = runtime->private_data; 537 538 aacirun->period = snd_pcm_lib_period_bytes(substream); 539 aacirun->start = runtime->dma_area; 540 aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream); 541 aacirun->ptr = aacirun->start; 542 aacirun->bytes = aacirun->period; 543 544 return 0; 545 } 546 547 static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream) 548 { 549 struct snd_pcm_runtime *runtime = substream->runtime; 550 struct aaci_runtime *aacirun = runtime->private_data; 551 ssize_t bytes = aacirun->ptr - aacirun->start; 552 553 return bytes_to_frames(runtime, bytes); 554 } 555 556 557 /* 558 * Playback specific ALSA stuff 559 */ 560 static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun) 561 { 562 u32 ie; 563 564 ie = readl(aacirun->base + AACI_IE); 565 ie &= ~(IE_URIE|IE_TXIE); 566 writel(ie, aacirun->base + AACI_IE); 567 aacirun->cr &= ~CR_EN; 568 aaci_chan_wait_ready(aacirun, SR_TXB); 569 writel(aacirun->cr, aacirun->base + AACI_TXCR); 570 } 571 572 static void aaci_pcm_playback_start(struct aaci_runtime *aacirun) 573 { 574 u32 ie; 575 576 aaci_chan_wait_ready(aacirun, SR_TXB); 577 aacirun->cr |= CR_EN; 578 579 ie = readl(aacirun->base + AACI_IE); 580 ie |= IE_URIE | IE_TXIE; 581 writel(ie, aacirun->base + AACI_IE); 582 writel(aacirun->cr, aacirun->base + AACI_TXCR); 583 } 584 585 static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) 586 { 587 struct aaci_runtime *aacirun = substream->runtime->private_data; 588 unsigned long flags; 589 int ret = 0; 590 591 spin_lock_irqsave(&aacirun->lock, flags); 592 593 switch (cmd) { 594 case SNDRV_PCM_TRIGGER_START: 595 aaci_pcm_playback_start(aacirun); 596 break; 597 598 case SNDRV_PCM_TRIGGER_RESUME: 599 aaci_pcm_playback_start(aacirun); 600 break; 601 602 case SNDRV_PCM_TRIGGER_STOP: 603 aaci_pcm_playback_stop(aacirun); 604 break; 605 606 case SNDRV_PCM_TRIGGER_SUSPEND: 607 aaci_pcm_playback_stop(aacirun); 608 break; 609 610 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 611 break; 612 613 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 614 break; 615 616 default: 617 ret = -EINVAL; 618 } 619 620 spin_unlock_irqrestore(&aacirun->lock, flags); 621 622 return ret; 623 } 624 625 static const struct snd_pcm_ops aaci_playback_ops = { 626 .open = aaci_pcm_open, 627 .close = aaci_pcm_close, 628 .ioctl = snd_pcm_lib_ioctl, 629 .hw_params = aaci_pcm_hw_params, 630 .hw_free = aaci_pcm_hw_free, 631 .prepare = aaci_pcm_prepare, 632 .trigger = aaci_pcm_playback_trigger, 633 .pointer = aaci_pcm_pointer, 634 }; 635 636 static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun) 637 { 638 u32 ie; 639 640 aaci_chan_wait_ready(aacirun, SR_RXB); 641 642 ie = readl(aacirun->base + AACI_IE); 643 ie &= ~(IE_ORIE | IE_RXIE); 644 writel(ie, aacirun->base+AACI_IE); 645 646 aacirun->cr &= ~CR_EN; 647 648 writel(aacirun->cr, aacirun->base + AACI_RXCR); 649 } 650 651 static void aaci_pcm_capture_start(struct aaci_runtime *aacirun) 652 { 653 u32 ie; 654 655 aaci_chan_wait_ready(aacirun, SR_RXB); 656 657 #ifdef DEBUG 658 /* RX Timeout value: bits 28:17 in RXCR */ 659 aacirun->cr |= 0xf << 17; 660 #endif 661 662 aacirun->cr |= CR_EN; 663 writel(aacirun->cr, aacirun->base + AACI_RXCR); 664 665 ie = readl(aacirun->base + AACI_IE); 666 ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full 667 writel(ie, aacirun->base + AACI_IE); 668 } 669 670 static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) 671 { 672 struct aaci_runtime *aacirun = substream->runtime->private_data; 673 unsigned long flags; 674 int ret = 0; 675 676 spin_lock_irqsave(&aacirun->lock, flags); 677 678 switch (cmd) { 679 case SNDRV_PCM_TRIGGER_START: 680 aaci_pcm_capture_start(aacirun); 681 break; 682 683 case SNDRV_PCM_TRIGGER_RESUME: 684 aaci_pcm_capture_start(aacirun); 685 break; 686 687 case SNDRV_PCM_TRIGGER_STOP: 688 aaci_pcm_capture_stop(aacirun); 689 break; 690 691 case SNDRV_PCM_TRIGGER_SUSPEND: 692 aaci_pcm_capture_stop(aacirun); 693 break; 694 695 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 696 break; 697 698 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 699 break; 700 701 default: 702 ret = -EINVAL; 703 } 704 705 spin_unlock_irqrestore(&aacirun->lock, flags); 706 707 return ret; 708 } 709 710 static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream) 711 { 712 struct snd_pcm_runtime *runtime = substream->runtime; 713 struct aaci *aaci = substream->private_data; 714 715 aaci_pcm_prepare(substream); 716 717 /* allow changing of sample rate */ 718 aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */ 719 aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); 720 aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate); 721 722 /* Record select: Mic: 0, Aux: 3, Line: 4 */ 723 aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404); 724 725 return 0; 726 } 727 728 static const struct snd_pcm_ops aaci_capture_ops = { 729 .open = aaci_pcm_open, 730 .close = aaci_pcm_close, 731 .ioctl = snd_pcm_lib_ioctl, 732 .hw_params = aaci_pcm_hw_params, 733 .hw_free = aaci_pcm_hw_free, 734 .prepare = aaci_pcm_capture_prepare, 735 .trigger = aaci_pcm_capture_trigger, 736 .pointer = aaci_pcm_pointer, 737 }; 738 739 /* 740 * Power Management. 741 */ 742 #ifdef CONFIG_PM 743 static int aaci_do_suspend(struct snd_card *card) 744 { 745 struct aaci *aaci = card->private_data; 746 snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); 747 return 0; 748 } 749 750 static int aaci_do_resume(struct snd_card *card) 751 { 752 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 753 return 0; 754 } 755 756 static int aaci_suspend(struct device *dev) 757 { 758 struct snd_card *card = dev_get_drvdata(dev); 759 return card ? aaci_do_suspend(card) : 0; 760 } 761 762 static int aaci_resume(struct device *dev) 763 { 764 struct snd_card *card = dev_get_drvdata(dev); 765 return card ? aaci_do_resume(card) : 0; 766 } 767 768 static SIMPLE_DEV_PM_OPS(aaci_dev_pm_ops, aaci_suspend, aaci_resume); 769 #define AACI_DEV_PM_OPS (&aaci_dev_pm_ops) 770 #else 771 #define AACI_DEV_PM_OPS NULL 772 #endif 773 774 775 static const struct ac97_pcm ac97_defs[] = { 776 [0] = { /* Front PCM */ 777 .exclusive = 1, 778 .r = { 779 [0] = { 780 .slots = (1 << AC97_SLOT_PCM_LEFT) | 781 (1 << AC97_SLOT_PCM_RIGHT) | 782 (1 << AC97_SLOT_PCM_CENTER) | 783 (1 << AC97_SLOT_PCM_SLEFT) | 784 (1 << AC97_SLOT_PCM_SRIGHT) | 785 (1 << AC97_SLOT_LFE), 786 }, 787 [1] = { 788 .slots = (1 << AC97_SLOT_PCM_LEFT) | 789 (1 << AC97_SLOT_PCM_RIGHT) | 790 (1 << AC97_SLOT_PCM_LEFT_0) | 791 (1 << AC97_SLOT_PCM_RIGHT_0), 792 }, 793 }, 794 }, 795 [1] = { /* PCM in */ 796 .stream = 1, 797 .exclusive = 1, 798 .r = { 799 [0] = { 800 .slots = (1 << AC97_SLOT_PCM_LEFT) | 801 (1 << AC97_SLOT_PCM_RIGHT), 802 }, 803 }, 804 }, 805 [2] = { /* Mic in */ 806 .stream = 1, 807 .exclusive = 1, 808 .r = { 809 [0] = { 810 .slots = (1 << AC97_SLOT_MIC), 811 }, 812 }, 813 } 814 }; 815 816 static struct snd_ac97_bus_ops aaci_bus_ops = { 817 .write = aaci_ac97_write, 818 .read = aaci_ac97_read, 819 }; 820 821 static int aaci_probe_ac97(struct aaci *aaci) 822 { 823 struct snd_ac97_template ac97_template; 824 struct snd_ac97_bus *ac97_bus; 825 struct snd_ac97 *ac97; 826 int ret; 827 828 /* 829 * Assert AACIRESET for 2us 830 */ 831 writel(0, aaci->base + AACI_RESET); 832 udelay(2); 833 writel(RESET_NRST, aaci->base + AACI_RESET); 834 835 /* 836 * Give the AC'97 codec more than enough time 837 * to wake up. (42us = ~2 frames at 48kHz.) 838 */ 839 udelay(FRAME_PERIOD_US * 2); 840 841 ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); 842 if (ret) 843 goto out; 844 845 ac97_bus->clock = 48000; 846 aaci->ac97_bus = ac97_bus; 847 848 memset(&ac97_template, 0, sizeof(struct snd_ac97_template)); 849 ac97_template.private_data = aaci; 850 ac97_template.num = 0; 851 ac97_template.scaps = AC97_SCAP_SKIP_MODEM; 852 853 ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97); 854 if (ret) 855 goto out; 856 aaci->ac97 = ac97; 857 858 /* 859 * Disable AC97 PC Beep input on audio codecs. 860 */ 861 if (ac97_is_audio(ac97)) 862 snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e); 863 864 ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs); 865 if (ret) 866 goto out; 867 868 aaci->playback.pcm = &ac97_bus->pcms[0]; 869 aaci->capture.pcm = &ac97_bus->pcms[1]; 870 871 out: 872 return ret; 873 } 874 875 static void aaci_free_card(struct snd_card *card) 876 { 877 struct aaci *aaci = card->private_data; 878 879 iounmap(aaci->base); 880 } 881 882 static struct aaci *aaci_init_card(struct amba_device *dev) 883 { 884 struct aaci *aaci; 885 struct snd_card *card; 886 int err; 887 888 err = snd_card_new(&dev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 889 THIS_MODULE, sizeof(struct aaci), &card); 890 if (err < 0) 891 return NULL; 892 893 card->private_free = aaci_free_card; 894 895 strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver)); 896 strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname)); 897 snprintf(card->longname, sizeof(card->longname), 898 "%s PL%03x rev%u at 0x%08llx, irq %d", 899 card->shortname, amba_part(dev), amba_rev(dev), 900 (unsigned long long)dev->res.start, dev->irq[0]); 901 902 aaci = card->private_data; 903 mutex_init(&aaci->ac97_sem); 904 mutex_init(&aaci->irq_lock); 905 aaci->card = card; 906 aaci->dev = dev; 907 908 /* Set MAINCR to allow slot 1 and 2 data IO */ 909 aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN | 910 MAINCR_SL2RXEN | MAINCR_SL2TXEN; 911 912 return aaci; 913 } 914 915 static int aaci_init_pcm(struct aaci *aaci) 916 { 917 struct snd_pcm *pcm; 918 int ret; 919 920 ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm); 921 if (ret == 0) { 922 aaci->pcm = pcm; 923 pcm->private_data = aaci; 924 pcm->info_flags = 0; 925 926 strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); 927 928 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops); 929 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops); 930 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 931 aaci->card->dev, 932 0, 64 * 1024); 933 } 934 935 return ret; 936 } 937 938 static unsigned int aaci_size_fifo(struct aaci *aaci) 939 { 940 struct aaci_runtime *aacirun = &aaci->playback; 941 int i; 942 943 /* 944 * Enable the channel, but don't assign it to any slots, so 945 * it won't empty onto the AC'97 link. 946 */ 947 writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); 948 949 for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++) 950 writel(0, aacirun->fifo); 951 952 writel(0, aacirun->base + AACI_TXCR); 953 954 /* 955 * Re-initialise the AACI after the FIFO depth test, to 956 * ensure that the FIFOs are empty. Unfortunately, merely 957 * disabling the channel doesn't clear the FIFO. 958 */ 959 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); 960 readl(aaci->base + AACI_MAINCR); 961 udelay(1); 962 writel(aaci->maincr, aaci->base + AACI_MAINCR); 963 964 /* 965 * If we hit 4096 entries, we failed. Go back to the specified 966 * fifo depth. 967 */ 968 if (i == 4096) 969 i = 8; 970 971 return i; 972 } 973 974 static int aaci_probe(struct amba_device *dev, 975 const struct amba_id *id) 976 { 977 struct aaci *aaci; 978 int ret, i; 979 980 ret = amba_request_regions(dev, NULL); 981 if (ret) 982 return ret; 983 984 aaci = aaci_init_card(dev); 985 if (!aaci) { 986 ret = -ENOMEM; 987 goto out; 988 } 989 990 aaci->base = ioremap(dev->res.start, resource_size(&dev->res)); 991 if (!aaci->base) { 992 ret = -ENOMEM; 993 goto out; 994 } 995 996 /* 997 * Playback uses AACI channel 0 998 */ 999 spin_lock_init(&aaci->playback.lock); 1000 aaci->playback.base = aaci->base + AACI_CSCH1; 1001 aaci->playback.fifo = aaci->base + AACI_DR1; 1002 1003 /* 1004 * Capture uses AACI channel 0 1005 */ 1006 spin_lock_init(&aaci->capture.lock); 1007 aaci->capture.base = aaci->base + AACI_CSCH1; 1008 aaci->capture.fifo = aaci->base + AACI_DR1; 1009 1010 for (i = 0; i < 4; i++) { 1011 void __iomem *base = aaci->base + i * 0x14; 1012 1013 writel(0, base + AACI_IE); 1014 writel(0, base + AACI_TXCR); 1015 writel(0, base + AACI_RXCR); 1016 } 1017 1018 writel(0x1fff, aaci->base + AACI_INTCLR); 1019 writel(aaci->maincr, aaci->base + AACI_MAINCR); 1020 /* 1021 * Fix: ac97 read back fail errors by reading 1022 * from any arbitrary aaci register. 1023 */ 1024 readl(aaci->base + AACI_CSCH1); 1025 ret = aaci_probe_ac97(aaci); 1026 if (ret) 1027 goto out; 1028 1029 /* 1030 * Size the FIFOs (must be multiple of 16). 1031 * This is the number of entries in the FIFO. 1032 */ 1033 aaci->fifo_depth = aaci_size_fifo(aaci); 1034 if (aaci->fifo_depth & 15) { 1035 printk(KERN_WARNING "AACI: FIFO depth %d not supported\n", 1036 aaci->fifo_depth); 1037 ret = -ENODEV; 1038 goto out; 1039 } 1040 1041 ret = aaci_init_pcm(aaci); 1042 if (ret) 1043 goto out; 1044 1045 ret = snd_card_register(aaci->card); 1046 if (ret == 0) { 1047 dev_info(&dev->dev, "%s\n", aaci->card->longname); 1048 dev_info(&dev->dev, "FIFO %u entries\n", aaci->fifo_depth); 1049 amba_set_drvdata(dev, aaci->card); 1050 return ret; 1051 } 1052 1053 out: 1054 if (aaci) 1055 snd_card_free(aaci->card); 1056 amba_release_regions(dev); 1057 return ret; 1058 } 1059 1060 static int aaci_remove(struct amba_device *dev) 1061 { 1062 struct snd_card *card = amba_get_drvdata(dev); 1063 1064 if (card) { 1065 struct aaci *aaci = card->private_data; 1066 writel(0, aaci->base + AACI_MAINCR); 1067 1068 snd_card_free(card); 1069 amba_release_regions(dev); 1070 } 1071 1072 return 0; 1073 } 1074 1075 static struct amba_id aaci_ids[] = { 1076 { 1077 .id = 0x00041041, 1078 .mask = 0x000fffff, 1079 }, 1080 { 0, 0 }, 1081 }; 1082 1083 MODULE_DEVICE_TABLE(amba, aaci_ids); 1084 1085 static struct amba_driver aaci_driver = { 1086 .drv = { 1087 .name = DRIVER_NAME, 1088 .pm = AACI_DEV_PM_OPS, 1089 }, 1090 .probe = aaci_probe, 1091 .remove = aaci_remove, 1092 .id_table = aaci_ids, 1093 }; 1094 1095 module_amba_driver(aaci_driver); 1096 1097 MODULE_LICENSE("GPL"); 1098 MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver"); 1099