1 /* 2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Documentation: ARM DDI 0173B 11 */ 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/ioport.h> 16 #include <linux/device.h> 17 #include <linux/spinlock.h> 18 #include <linux/interrupt.h> 19 #include <linux/err.h> 20 #include <linux/amba/bus.h> 21 #include <linux/io.h> 22 23 #include <sound/core.h> 24 #include <sound/initval.h> 25 #include <sound/ac97_codec.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 29 #include "aaci.h" 30 31 #define DRIVER_NAME "aaci-pl041" 32 33 #define FRAME_PERIOD_US 21 34 35 /* 36 * PM support is not complete. Turn it off. 37 */ 38 #undef CONFIG_PM 39 40 static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) 41 { 42 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); 43 44 /* 45 * Ensure that the slot 1/2 RX registers are empty. 46 */ 47 v = readl(aaci->base + AACI_SLFR); 48 if (v & SLFR_2RXV) 49 readl(aaci->base + AACI_SL2RX); 50 if (v & SLFR_1RXV) 51 readl(aaci->base + AACI_SL1RX); 52 53 if (maincr != readl(aaci->base + AACI_MAINCR)) { 54 writel(maincr, aaci->base + AACI_MAINCR); 55 readl(aaci->base + AACI_MAINCR); 56 udelay(1); 57 } 58 } 59 60 /* 61 * P29: 62 * The recommended use of programming the external codec through slot 1 63 * and slot 2 data is to use the channels during setup routines and the 64 * slot register at any other time. The data written into slot 1, slot 2 65 * and slot 12 registers is transmitted only when their corresponding 66 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR 67 * register. 68 */ 69 static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 70 unsigned short val) 71 { 72 struct aaci *aaci = ac97->private_data; 73 int timeout; 74 u32 v; 75 76 if (ac97->num >= 4) 77 return; 78 79 mutex_lock(&aaci->ac97_sem); 80 81 aaci_ac97_select_codec(aaci, ac97); 82 83 /* 84 * P54: You must ensure that AACI_SL2TX is always written 85 * to, if required, before data is written to AACI_SL1TX. 86 */ 87 writel(val << 4, aaci->base + AACI_SL2TX); 88 writel(reg << 12, aaci->base + AACI_SL1TX); 89 90 /* Initially, wait one frame period */ 91 udelay(FRAME_PERIOD_US); 92 93 /* And then wait an additional eight frame periods for it to be sent */ 94 timeout = FRAME_PERIOD_US * 8; 95 do { 96 udelay(1); 97 v = readl(aaci->base + AACI_SLFR); 98 } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout); 99 100 if (v & (SLFR_1TXB|SLFR_2TXB)) 101 dev_err(&aaci->dev->dev, 102 "timeout waiting for write to complete\n"); 103 104 mutex_unlock(&aaci->ac97_sem); 105 } 106 107 /* 108 * Read an AC'97 register. 109 */ 110 static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 111 { 112 struct aaci *aaci = ac97->private_data; 113 int timeout, retries = 10; 114 u32 v; 115 116 if (ac97->num >= 4) 117 return ~0; 118 119 mutex_lock(&aaci->ac97_sem); 120 121 aaci_ac97_select_codec(aaci, ac97); 122 123 /* 124 * Write the register address to slot 1. 125 */ 126 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); 127 128 /* Initially, wait one frame period */ 129 udelay(FRAME_PERIOD_US); 130 131 /* And then wait an additional eight frame periods for it to be sent */ 132 timeout = FRAME_PERIOD_US * 8; 133 do { 134 udelay(1); 135 v = readl(aaci->base + AACI_SLFR); 136 } while ((v & SLFR_1TXB) && --timeout); 137 138 if (v & SLFR_1TXB) { 139 dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n"); 140 v = ~0; 141 goto out; 142 } 143 144 /* Now wait for the response frame */ 145 udelay(FRAME_PERIOD_US); 146 147 /* And then wait an additional eight frame periods for data */ 148 timeout = FRAME_PERIOD_US * 8; 149 do { 150 udelay(1); 151 cond_resched(); 152 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); 153 } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout); 154 155 if (v != (SLFR_1RXV|SLFR_2RXV)) { 156 dev_err(&aaci->dev->dev, "timeout on RX valid\n"); 157 v = ~0; 158 goto out; 159 } 160 161 do { 162 v = readl(aaci->base + AACI_SL1RX) >> 12; 163 if (v == reg) { 164 v = readl(aaci->base + AACI_SL2RX) >> 4; 165 break; 166 } else if (--retries) { 167 dev_warn(&aaci->dev->dev, 168 "ac97 read back fail. retry\n"); 169 continue; 170 } else { 171 dev_warn(&aaci->dev->dev, 172 "wrong ac97 register read back (%x != %x)\n", 173 v, reg); 174 v = ~0; 175 } 176 } while (retries); 177 out: 178 mutex_unlock(&aaci->ac97_sem); 179 return v; 180 } 181 182 static inline void 183 aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask) 184 { 185 u32 val; 186 int timeout = 5000; 187 188 do { 189 udelay(1); 190 val = readl(aacirun->base + AACI_SR); 191 } while (val & mask && timeout--); 192 } 193 194 195 196 /* 197 * Interrupt support. 198 */ 199 static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask) 200 { 201 if (mask & ISR_ORINTR) { 202 dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel); 203 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); 204 } 205 206 if (mask & ISR_RXTOINTR) { 207 dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel); 208 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); 209 } 210 211 if (mask & ISR_RXINTR) { 212 struct aaci_runtime *aacirun = &aaci->capture; 213 void *ptr; 214 215 if (!aacirun->substream || !aacirun->start) { 216 dev_warn(&aaci->dev->dev, "RX interrupt???\n"); 217 writel(0, aacirun->base + AACI_IE); 218 return; 219 } 220 221 spin_lock(&aacirun->lock); 222 223 ptr = aacirun->ptr; 224 do { 225 unsigned int len = aacirun->fifosz; 226 u32 val; 227 228 if (aacirun->bytes <= 0) { 229 aacirun->bytes += aacirun->period; 230 aacirun->ptr = ptr; 231 spin_unlock(&aacirun->lock); 232 snd_pcm_period_elapsed(aacirun->substream); 233 spin_lock(&aacirun->lock); 234 } 235 if (!(aacirun->cr & CR_EN)) 236 break; 237 238 val = readl(aacirun->base + AACI_SR); 239 if (!(val & SR_RXHF)) 240 break; 241 if (!(val & SR_RXFF)) 242 len >>= 1; 243 244 aacirun->bytes -= len; 245 246 /* reading 16 bytes at a time */ 247 for( ; len > 0; len -= 16) { 248 asm( 249 "ldmia %1, {r0, r1, r2, r3}\n\t" 250 "stmia %0!, {r0, r1, r2, r3}" 251 : "+r" (ptr) 252 : "r" (aacirun->fifo) 253 : "r0", "r1", "r2", "r3", "cc"); 254 255 if (ptr >= aacirun->end) 256 ptr = aacirun->start; 257 } 258 } while(1); 259 260 aacirun->ptr = ptr; 261 262 spin_unlock(&aacirun->lock); 263 } 264 265 if (mask & ISR_URINTR) { 266 dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel); 267 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); 268 } 269 270 if (mask & ISR_TXINTR) { 271 struct aaci_runtime *aacirun = &aaci->playback; 272 void *ptr; 273 274 if (!aacirun->substream || !aacirun->start) { 275 dev_warn(&aaci->dev->dev, "TX interrupt???\n"); 276 writel(0, aacirun->base + AACI_IE); 277 return; 278 } 279 280 spin_lock(&aacirun->lock); 281 282 ptr = aacirun->ptr; 283 do { 284 unsigned int len = aacirun->fifosz; 285 u32 val; 286 287 if (aacirun->bytes <= 0) { 288 aacirun->bytes += aacirun->period; 289 aacirun->ptr = ptr; 290 spin_unlock(&aacirun->lock); 291 snd_pcm_period_elapsed(aacirun->substream); 292 spin_lock(&aacirun->lock); 293 } 294 if (!(aacirun->cr & CR_EN)) 295 break; 296 297 val = readl(aacirun->base + AACI_SR); 298 if (!(val & SR_TXHE)) 299 break; 300 if (!(val & SR_TXFE)) 301 len >>= 1; 302 303 aacirun->bytes -= len; 304 305 /* writing 16 bytes at a time */ 306 for ( ; len > 0; len -= 16) { 307 asm( 308 "ldmia %0!, {r0, r1, r2, r3}\n\t" 309 "stmia %1, {r0, r1, r2, r3}" 310 : "+r" (ptr) 311 : "r" (aacirun->fifo) 312 : "r0", "r1", "r2", "r3", "cc"); 313 314 if (ptr >= aacirun->end) 315 ptr = aacirun->start; 316 } 317 } while (1); 318 319 aacirun->ptr = ptr; 320 321 spin_unlock(&aacirun->lock); 322 } 323 } 324 325 static irqreturn_t aaci_irq(int irq, void *devid) 326 { 327 struct aaci *aaci = devid; 328 u32 mask; 329 int i; 330 331 mask = readl(aaci->base + AACI_ALLINTS); 332 if (mask) { 333 u32 m = mask; 334 for (i = 0; i < 4; i++, m >>= 7) { 335 if (m & 0x7f) { 336 aaci_fifo_irq(aaci, i, m); 337 } 338 } 339 } 340 341 return mask ? IRQ_HANDLED : IRQ_NONE; 342 } 343 344 345 346 /* 347 * ALSA support. 348 */ 349 static struct snd_pcm_hardware aaci_hw_info = { 350 .info = SNDRV_PCM_INFO_MMAP | 351 SNDRV_PCM_INFO_MMAP_VALID | 352 SNDRV_PCM_INFO_INTERLEAVED | 353 SNDRV_PCM_INFO_BLOCK_TRANSFER | 354 SNDRV_PCM_INFO_RESUME, 355 356 /* 357 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit 358 * words. It also doesn't support 12-bit at all. 359 */ 360 .formats = SNDRV_PCM_FMTBIT_S16_LE, 361 362 /* rates are setup from the AC'97 codec */ 363 .channels_min = 2, 364 .channels_max = 6, 365 .buffer_bytes_max = 64 * 1024, 366 .period_bytes_min = 256, 367 .period_bytes_max = PAGE_SIZE, 368 .periods_min = 4, 369 .periods_max = PAGE_SIZE / 16, 370 }; 371 372 static int __aaci_pcm_open(struct aaci *aaci, 373 struct snd_pcm_substream *substream, 374 struct aaci_runtime *aacirun) 375 { 376 struct snd_pcm_runtime *runtime = substream->runtime; 377 int ret; 378 379 aacirun->substream = substream; 380 runtime->private_data = aacirun; 381 runtime->hw = aaci_hw_info; 382 runtime->hw.rates = aacirun->pcm->rates; 383 snd_pcm_limit_hw_rates(runtime); 384 385 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 386 aacirun->pcm->r[1].slots) 387 snd_ac97_pcm_double_rate_rules(runtime); 388 389 /* 390 * FIXME: ALSA specifies fifo_size in bytes. If we're in normal 391 * mode, each 32-bit word contains one sample. If we're in 392 * compact mode, each 32-bit word contains two samples, effectively 393 * halving the FIFO size. However, we don't know for sure which 394 * we'll be using at this point. We set this to the lower limit. 395 */ 396 runtime->hw.fifo_size = aaci->fifosize * 2; 397 398 ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED, 399 DRIVER_NAME, aaci); 400 if (ret) 401 goto out; 402 403 return 0; 404 405 out: 406 return ret; 407 } 408 409 410 /* 411 * Common ALSA stuff 412 */ 413 static int aaci_pcm_close(struct snd_pcm_substream *substream) 414 { 415 struct aaci *aaci = substream->private_data; 416 struct aaci_runtime *aacirun = substream->runtime->private_data; 417 418 WARN_ON(aacirun->cr & CR_EN); 419 420 aacirun->substream = NULL; 421 free_irq(aaci->dev->irq[0], aaci); 422 423 return 0; 424 } 425 426 static int aaci_pcm_hw_free(struct snd_pcm_substream *substream) 427 { 428 struct aaci_runtime *aacirun = substream->runtime->private_data; 429 430 /* 431 * This must not be called with the device enabled. 432 */ 433 WARN_ON(aacirun->cr & CR_EN); 434 435 if (aacirun->pcm_open) 436 snd_ac97_pcm_close(aacirun->pcm); 437 aacirun->pcm_open = 0; 438 439 /* 440 * Clear out the DMA and any allocated buffers. 441 */ 442 snd_pcm_lib_free_pages(substream); 443 444 return 0; 445 } 446 447 static int aaci_pcm_hw_params(struct snd_pcm_substream *substream, 448 struct aaci_runtime *aacirun, 449 struct snd_pcm_hw_params *params) 450 { 451 int err; 452 struct aaci *aaci = substream->private_data; 453 454 aaci_pcm_hw_free(substream); 455 if (aacirun->pcm_open) { 456 snd_ac97_pcm_close(aacirun->pcm); 457 aacirun->pcm_open = 0; 458 } 459 460 err = snd_pcm_lib_malloc_pages(substream, 461 params_buffer_bytes(params)); 462 if (err >= 0) { 463 unsigned int rate = params_rate(params); 464 int dbl = rate > 48000; 465 466 err = snd_ac97_pcm_open(aacirun->pcm, rate, 467 params_channels(params), 468 aacirun->pcm->r[dbl].slots); 469 470 aacirun->pcm_open = err == 0; 471 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; 472 aacirun->fifosz = aaci->fifosize * 4; 473 474 if (aacirun->cr & CR_COMPACT) 475 aacirun->fifosz >>= 1; 476 } 477 478 return err; 479 } 480 481 static int aaci_pcm_prepare(struct snd_pcm_substream *substream) 482 { 483 struct snd_pcm_runtime *runtime = substream->runtime; 484 struct aaci_runtime *aacirun = runtime->private_data; 485 486 aacirun->start = runtime->dma_area; 487 aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream); 488 aacirun->ptr = aacirun->start; 489 aacirun->period = 490 aacirun->bytes = frames_to_bytes(runtime, runtime->period_size); 491 492 return 0; 493 } 494 495 static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream) 496 { 497 struct snd_pcm_runtime *runtime = substream->runtime; 498 struct aaci_runtime *aacirun = runtime->private_data; 499 ssize_t bytes = aacirun->ptr - aacirun->start; 500 501 return bytes_to_frames(runtime, bytes); 502 } 503 504 505 /* 506 * Playback specific ALSA stuff 507 */ 508 static const u32 channels_to_txmask[] = { 509 [2] = CR_SL3 | CR_SL4, 510 [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8, 511 [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9, 512 }; 513 514 /* 515 * We can support two and four channel audio. Unfortunately 516 * six channel audio requires a non-standard channel ordering: 517 * 2 -> FL(3), FR(4) 518 * 4 -> FL(3), FR(4), SL(7), SR(8) 519 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) 520 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual) 521 * This requires an ALSA configuration file to correct. 522 */ 523 static unsigned int channel_list[] = { 2, 4, 6 }; 524 525 static int 526 aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule) 527 { 528 struct aaci *aaci = rule->private; 529 unsigned int chan_mask = 1 << 0, slots; 530 531 /* 532 * pcms[0] is the our 5.1 PCM instance. 533 */ 534 slots = aaci->ac97_bus->pcms[0].r[0].slots; 535 if (slots & (1 << AC97_SLOT_PCM_SLEFT)) { 536 chan_mask |= 1 << 1; 537 if (slots & (1 << AC97_SLOT_LFE)) 538 chan_mask |= 1 << 2; 539 } 540 541 return snd_interval_list(hw_param_interval(p, rule->var), 542 ARRAY_SIZE(channel_list), channel_list, 543 chan_mask); 544 } 545 546 static int aaci_pcm_open(struct snd_pcm_substream *substream) 547 { 548 struct aaci *aaci = substream->private_data; 549 int ret; 550 551 /* 552 * Add rule describing channel dependency. 553 */ 554 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 555 SNDRV_PCM_HW_PARAM_CHANNELS, 556 aaci_rule_channels, aaci, 557 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 558 if (ret) 559 return ret; 560 561 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 562 ret = __aaci_pcm_open(aaci, substream, &aaci->playback); 563 } else { 564 ret = __aaci_pcm_open(aaci, substream, &aaci->capture); 565 } 566 return ret; 567 } 568 569 static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream, 570 struct snd_pcm_hw_params *params) 571 { 572 struct aaci_runtime *aacirun = substream->runtime->private_data; 573 unsigned int channels = params_channels(params); 574 int ret; 575 576 WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) || 577 !channels_to_txmask[channels]); 578 579 ret = aaci_pcm_hw_params(substream, aacirun, params); 580 581 /* 582 * Enable FIFO, compact mode, 16 bits per sample. 583 * FIXME: double rate slots? 584 */ 585 if (ret >= 0) 586 aacirun->cr |= channels_to_txmask[channels]; 587 588 return ret; 589 } 590 591 static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun) 592 { 593 u32 ie; 594 595 ie = readl(aacirun->base + AACI_IE); 596 ie &= ~(IE_URIE|IE_TXIE); 597 writel(ie, aacirun->base + AACI_IE); 598 aacirun->cr &= ~CR_EN; 599 aaci_chan_wait_ready(aacirun, SR_TXB); 600 writel(aacirun->cr, aacirun->base + AACI_TXCR); 601 } 602 603 static void aaci_pcm_playback_start(struct aaci_runtime *aacirun) 604 { 605 u32 ie; 606 607 aaci_chan_wait_ready(aacirun, SR_TXB); 608 aacirun->cr |= CR_EN; 609 610 ie = readl(aacirun->base + AACI_IE); 611 ie |= IE_URIE | IE_TXIE; 612 writel(ie, aacirun->base + AACI_IE); 613 writel(aacirun->cr, aacirun->base + AACI_TXCR); 614 } 615 616 static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) 617 { 618 struct aaci_runtime *aacirun = substream->runtime->private_data; 619 unsigned long flags; 620 int ret = 0; 621 622 spin_lock_irqsave(&aacirun->lock, flags); 623 624 switch (cmd) { 625 case SNDRV_PCM_TRIGGER_START: 626 aaci_pcm_playback_start(aacirun); 627 break; 628 629 case SNDRV_PCM_TRIGGER_RESUME: 630 aaci_pcm_playback_start(aacirun); 631 break; 632 633 case SNDRV_PCM_TRIGGER_STOP: 634 aaci_pcm_playback_stop(aacirun); 635 break; 636 637 case SNDRV_PCM_TRIGGER_SUSPEND: 638 aaci_pcm_playback_stop(aacirun); 639 break; 640 641 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 642 break; 643 644 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 645 break; 646 647 default: 648 ret = -EINVAL; 649 } 650 651 spin_unlock_irqrestore(&aacirun->lock, flags); 652 653 return ret; 654 } 655 656 static struct snd_pcm_ops aaci_playback_ops = { 657 .open = aaci_pcm_open, 658 .close = aaci_pcm_close, 659 .ioctl = snd_pcm_lib_ioctl, 660 .hw_params = aaci_pcm_playback_hw_params, 661 .hw_free = aaci_pcm_hw_free, 662 .prepare = aaci_pcm_prepare, 663 .trigger = aaci_pcm_playback_trigger, 664 .pointer = aaci_pcm_pointer, 665 }; 666 667 static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream, 668 struct snd_pcm_hw_params *params) 669 { 670 struct aaci_runtime *aacirun = substream->runtime->private_data; 671 int ret; 672 673 ret = aaci_pcm_hw_params(substream, aacirun, params); 674 if (ret >= 0) 675 /* Line in record: slot 3 and 4 */ 676 aacirun->cr |= CR_SL3 | CR_SL4; 677 678 return ret; 679 } 680 681 static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun) 682 { 683 u32 ie; 684 685 aaci_chan_wait_ready(aacirun, SR_RXB); 686 687 ie = readl(aacirun->base + AACI_IE); 688 ie &= ~(IE_ORIE | IE_RXIE); 689 writel(ie, aacirun->base+AACI_IE); 690 691 aacirun->cr &= ~CR_EN; 692 693 writel(aacirun->cr, aacirun->base + AACI_RXCR); 694 } 695 696 static void aaci_pcm_capture_start(struct aaci_runtime *aacirun) 697 { 698 u32 ie; 699 700 aaci_chan_wait_ready(aacirun, SR_RXB); 701 702 #ifdef DEBUG 703 /* RX Timeout value: bits 28:17 in RXCR */ 704 aacirun->cr |= 0xf << 17; 705 #endif 706 707 aacirun->cr |= CR_EN; 708 writel(aacirun->cr, aacirun->base + AACI_RXCR); 709 710 ie = readl(aacirun->base + AACI_IE); 711 ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full 712 writel(ie, aacirun->base + AACI_IE); 713 } 714 715 static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) 716 { 717 struct aaci_runtime *aacirun = substream->runtime->private_data; 718 unsigned long flags; 719 int ret = 0; 720 721 spin_lock_irqsave(&aacirun->lock, flags); 722 723 switch (cmd) { 724 case SNDRV_PCM_TRIGGER_START: 725 aaci_pcm_capture_start(aacirun); 726 break; 727 728 case SNDRV_PCM_TRIGGER_RESUME: 729 aaci_pcm_capture_start(aacirun); 730 break; 731 732 case SNDRV_PCM_TRIGGER_STOP: 733 aaci_pcm_capture_stop(aacirun); 734 break; 735 736 case SNDRV_PCM_TRIGGER_SUSPEND: 737 aaci_pcm_capture_stop(aacirun); 738 break; 739 740 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 741 break; 742 743 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 744 break; 745 746 default: 747 ret = -EINVAL; 748 } 749 750 spin_unlock_irqrestore(&aacirun->lock, flags); 751 752 return ret; 753 } 754 755 static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream) 756 { 757 struct snd_pcm_runtime *runtime = substream->runtime; 758 struct aaci *aaci = substream->private_data; 759 760 aaci_pcm_prepare(substream); 761 762 /* allow changing of sample rate */ 763 aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */ 764 aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); 765 aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate); 766 767 /* Record select: Mic: 0, Aux: 3, Line: 4 */ 768 aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404); 769 770 return 0; 771 } 772 773 static struct snd_pcm_ops aaci_capture_ops = { 774 .open = aaci_pcm_open, 775 .close = aaci_pcm_close, 776 .ioctl = snd_pcm_lib_ioctl, 777 .hw_params = aaci_pcm_capture_hw_params, 778 .hw_free = aaci_pcm_hw_free, 779 .prepare = aaci_pcm_capture_prepare, 780 .trigger = aaci_pcm_capture_trigger, 781 .pointer = aaci_pcm_pointer, 782 }; 783 784 /* 785 * Power Management. 786 */ 787 #ifdef CONFIG_PM 788 static int aaci_do_suspend(struct snd_card *card, unsigned int state) 789 { 790 struct aaci *aaci = card->private_data; 791 snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); 792 snd_pcm_suspend_all(aaci->pcm); 793 return 0; 794 } 795 796 static int aaci_do_resume(struct snd_card *card, unsigned int state) 797 { 798 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 799 return 0; 800 } 801 802 static int aaci_suspend(struct amba_device *dev, pm_message_t state) 803 { 804 struct snd_card *card = amba_get_drvdata(dev); 805 return card ? aaci_do_suspend(card) : 0; 806 } 807 808 static int aaci_resume(struct amba_device *dev) 809 { 810 struct snd_card *card = amba_get_drvdata(dev); 811 return card ? aaci_do_resume(card) : 0; 812 } 813 #else 814 #define aaci_do_suspend NULL 815 #define aaci_do_resume NULL 816 #define aaci_suspend NULL 817 #define aaci_resume NULL 818 #endif 819 820 821 static struct ac97_pcm ac97_defs[] __devinitdata = { 822 [0] = { /* Front PCM */ 823 .exclusive = 1, 824 .r = { 825 [0] = { 826 .slots = (1 << AC97_SLOT_PCM_LEFT) | 827 (1 << AC97_SLOT_PCM_RIGHT) | 828 (1 << AC97_SLOT_PCM_CENTER) | 829 (1 << AC97_SLOT_PCM_SLEFT) | 830 (1 << AC97_SLOT_PCM_SRIGHT) | 831 (1 << AC97_SLOT_LFE), 832 }, 833 [1] = { 834 .slots = (1 << AC97_SLOT_PCM_LEFT) | 835 (1 << AC97_SLOT_PCM_RIGHT) | 836 (1 << AC97_SLOT_PCM_LEFT_0) | 837 (1 << AC97_SLOT_PCM_RIGHT_0), 838 }, 839 }, 840 }, 841 [1] = { /* PCM in */ 842 .stream = 1, 843 .exclusive = 1, 844 .r = { 845 [0] = { 846 .slots = (1 << AC97_SLOT_PCM_LEFT) | 847 (1 << AC97_SLOT_PCM_RIGHT), 848 }, 849 }, 850 }, 851 [2] = { /* Mic in */ 852 .stream = 1, 853 .exclusive = 1, 854 .r = { 855 [0] = { 856 .slots = (1 << AC97_SLOT_MIC), 857 }, 858 }, 859 } 860 }; 861 862 static struct snd_ac97_bus_ops aaci_bus_ops = { 863 .write = aaci_ac97_write, 864 .read = aaci_ac97_read, 865 }; 866 867 static int __devinit aaci_probe_ac97(struct aaci *aaci) 868 { 869 struct snd_ac97_template ac97_template; 870 struct snd_ac97_bus *ac97_bus; 871 struct snd_ac97 *ac97; 872 int ret; 873 874 /* 875 * Assert AACIRESET for 2us 876 */ 877 writel(0, aaci->base + AACI_RESET); 878 udelay(2); 879 writel(RESET_NRST, aaci->base + AACI_RESET); 880 881 /* 882 * Give the AC'97 codec more than enough time 883 * to wake up. (42us = ~2 frames at 48kHz.) 884 */ 885 udelay(FRAME_PERIOD_US * 2); 886 887 ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); 888 if (ret) 889 goto out; 890 891 ac97_bus->clock = 48000; 892 aaci->ac97_bus = ac97_bus; 893 894 memset(&ac97_template, 0, sizeof(struct snd_ac97_template)); 895 ac97_template.private_data = aaci; 896 ac97_template.num = 0; 897 ac97_template.scaps = AC97_SCAP_SKIP_MODEM; 898 899 ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97); 900 if (ret) 901 goto out; 902 aaci->ac97 = ac97; 903 904 /* 905 * Disable AC97 PC Beep input on audio codecs. 906 */ 907 if (ac97_is_audio(ac97)) 908 snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e); 909 910 ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs); 911 if (ret) 912 goto out; 913 914 aaci->playback.pcm = &ac97_bus->pcms[0]; 915 aaci->capture.pcm = &ac97_bus->pcms[1]; 916 917 out: 918 return ret; 919 } 920 921 static void aaci_free_card(struct snd_card *card) 922 { 923 struct aaci *aaci = card->private_data; 924 if (aaci->base) 925 iounmap(aaci->base); 926 } 927 928 static struct aaci * __devinit aaci_init_card(struct amba_device *dev) 929 { 930 struct aaci *aaci; 931 struct snd_card *card; 932 int err; 933 934 err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 935 THIS_MODULE, sizeof(struct aaci), &card); 936 if (err < 0) 937 return NULL; 938 939 card->private_free = aaci_free_card; 940 941 strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver)); 942 strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname)); 943 snprintf(card->longname, sizeof(card->longname), 944 "%s at 0x%016llx, irq %d", 945 card->shortname, (unsigned long long)dev->res.start, 946 dev->irq[0]); 947 948 aaci = card->private_data; 949 mutex_init(&aaci->ac97_sem); 950 aaci->card = card; 951 aaci->dev = dev; 952 953 /* Set MAINCR to allow slot 1 and 2 data IO */ 954 aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN | 955 MAINCR_SL2RXEN | MAINCR_SL2TXEN; 956 957 return aaci; 958 } 959 960 static int __devinit aaci_init_pcm(struct aaci *aaci) 961 { 962 struct snd_pcm *pcm; 963 int ret; 964 965 ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm); 966 if (ret == 0) { 967 aaci->pcm = pcm; 968 pcm->private_data = aaci; 969 pcm->info_flags = 0; 970 971 strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); 972 973 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops); 974 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops); 975 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 976 NULL, 0, 64 * 1024); 977 } 978 979 return ret; 980 } 981 982 static unsigned int __devinit aaci_size_fifo(struct aaci *aaci) 983 { 984 struct aaci_runtime *aacirun = &aaci->playback; 985 int i; 986 987 writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); 988 989 for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++) 990 writel(0, aacirun->fifo); 991 992 writel(0, aacirun->base + AACI_TXCR); 993 994 /* 995 * Re-initialise the AACI after the FIFO depth test, to 996 * ensure that the FIFOs are empty. Unfortunately, merely 997 * disabling the channel doesn't clear the FIFO. 998 */ 999 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); 1000 readl(aaci->base + AACI_MAINCR); 1001 udelay(1); 1002 writel(aaci->maincr, aaci->base + AACI_MAINCR); 1003 1004 /* 1005 * If we hit 4096, we failed. Go back to the specified 1006 * fifo depth. 1007 */ 1008 if (i == 4096) 1009 i = 8; 1010 1011 return i; 1012 } 1013 1014 static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id) 1015 { 1016 struct aaci *aaci; 1017 int ret, i; 1018 1019 ret = amba_request_regions(dev, NULL); 1020 if (ret) 1021 return ret; 1022 1023 aaci = aaci_init_card(dev); 1024 if (!aaci) { 1025 ret = -ENOMEM; 1026 goto out; 1027 } 1028 1029 aaci->base = ioremap(dev->res.start, resource_size(&dev->res)); 1030 if (!aaci->base) { 1031 ret = -ENOMEM; 1032 goto out; 1033 } 1034 1035 /* 1036 * Playback uses AACI channel 0 1037 */ 1038 spin_lock_init(&aaci->playback.lock); 1039 aaci->playback.base = aaci->base + AACI_CSCH1; 1040 aaci->playback.fifo = aaci->base + AACI_DR1; 1041 1042 /* 1043 * Capture uses AACI channel 0 1044 */ 1045 spin_lock_init(&aaci->capture.lock); 1046 aaci->capture.base = aaci->base + AACI_CSCH1; 1047 aaci->capture.fifo = aaci->base + AACI_DR1; 1048 1049 for (i = 0; i < 4; i++) { 1050 void __iomem *base = aaci->base + i * 0x14; 1051 1052 writel(0, base + AACI_IE); 1053 writel(0, base + AACI_TXCR); 1054 writel(0, base + AACI_RXCR); 1055 } 1056 1057 writel(0x1fff, aaci->base + AACI_INTCLR); 1058 writel(aaci->maincr, aaci->base + AACI_MAINCR); 1059 /* 1060 * Fix: ac97 read back fail errors by reading 1061 * from any arbitrary aaci register. 1062 */ 1063 readl(aaci->base + AACI_CSCH1); 1064 ret = aaci_probe_ac97(aaci); 1065 if (ret) 1066 goto out; 1067 1068 /* 1069 * Size the FIFOs (must be multiple of 16). 1070 */ 1071 aaci->fifosize = aaci_size_fifo(aaci); 1072 if (aaci->fifosize & 15) { 1073 printk(KERN_WARNING "AACI: fifosize = %d not supported\n", 1074 aaci->fifosize); 1075 ret = -ENODEV; 1076 goto out; 1077 } 1078 1079 ret = aaci_init_pcm(aaci); 1080 if (ret) 1081 goto out; 1082 1083 snd_card_set_dev(aaci->card, &dev->dev); 1084 1085 ret = snd_card_register(aaci->card); 1086 if (ret == 0) { 1087 dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname, 1088 aaci->fifosize); 1089 amba_set_drvdata(dev, aaci->card); 1090 return ret; 1091 } 1092 1093 out: 1094 if (aaci) 1095 snd_card_free(aaci->card); 1096 amba_release_regions(dev); 1097 return ret; 1098 } 1099 1100 static int __devexit aaci_remove(struct amba_device *dev) 1101 { 1102 struct snd_card *card = amba_get_drvdata(dev); 1103 1104 amba_set_drvdata(dev, NULL); 1105 1106 if (card) { 1107 struct aaci *aaci = card->private_data; 1108 writel(0, aaci->base + AACI_MAINCR); 1109 1110 snd_card_free(card); 1111 amba_release_regions(dev); 1112 } 1113 1114 return 0; 1115 } 1116 1117 static struct amba_id aaci_ids[] = { 1118 { 1119 .id = 0x00041041, 1120 .mask = 0x000fffff, 1121 }, 1122 { 0, 0 }, 1123 }; 1124 1125 static struct amba_driver aaci_driver = { 1126 .drv = { 1127 .name = DRIVER_NAME, 1128 }, 1129 .probe = aaci_probe, 1130 .remove = __devexit_p(aaci_remove), 1131 .suspend = aaci_suspend, 1132 .resume = aaci_resume, 1133 .id_table = aaci_ids, 1134 }; 1135 1136 static int __init aaci_init(void) 1137 { 1138 return amba_driver_register(&aaci_driver); 1139 } 1140 1141 static void __exit aaci_exit(void) 1142 { 1143 amba_driver_unregister(&aaci_driver); 1144 } 1145 1146 module_init(aaci_init); 1147 module_exit(aaci_exit); 1148 1149 MODULE_LICENSE("GPL"); 1150 MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver"); 1151