1775f1f7eSMax Filippov// SPDX-License-Identifier: GPL-2.0
2775f1f7eSMax Filippov/dts-v1/;
3775f1f7eSMax Filippov
4775f1f7eSMax Filippov/ {
5775f1f7eSMax Filippov	compatible = "cdns,xtensa-iss";
6775f1f7eSMax Filippov	#address-cells = <1>;
7775f1f7eSMax Filippov	#size-cells = <1>;
8775f1f7eSMax Filippov	interrupt-parent = <&pic>;
9775f1f7eSMax Filippov
10775f1f7eSMax Filippov	chosen {
11775f1f7eSMax Filippov		bootargs = "console=ttyS0,115200n8 debug";
12775f1f7eSMax Filippov	};
13775f1f7eSMax Filippov
14775f1f7eSMax Filippov	memory@0 {
15775f1f7eSMax Filippov		device_type = "memory";
16775f1f7eSMax Filippov		reg = <0x00000000 0x80000000>;
17775f1f7eSMax Filippov	};
18775f1f7eSMax Filippov
19775f1f7eSMax Filippov	cpus {
20775f1f7eSMax Filippov		#address-cells = <1>;
21775f1f7eSMax Filippov		#size-cells = <0>;
22775f1f7eSMax Filippov		cpu@0 {
23775f1f7eSMax Filippov			compatible = "cdns,xtensa-cpu";
24775f1f7eSMax Filippov			reg = <0>;
25775f1f7eSMax Filippov			clocks = <&osc>;
26775f1f7eSMax Filippov		};
27775f1f7eSMax Filippov	};
28775f1f7eSMax Filippov
29775f1f7eSMax Filippov	clocks {
30775f1f7eSMax Filippov		osc: osc {
31775f1f7eSMax Filippov			#clock-cells = <0>;
32775f1f7eSMax Filippov			compatible = "fixed-clock";
33775f1f7eSMax Filippov			clock-frequency = <40000000>;
34775f1f7eSMax Filippov		};
35775f1f7eSMax Filippov	};
36775f1f7eSMax Filippov
37775f1f7eSMax Filippov	pic: pic {
38775f1f7eSMax Filippov		compatible = "cdns,xtensa-pic";
39775f1f7eSMax Filippov		/* one cell: internal irq number,
40775f1f7eSMax Filippov		 * two cells: second cell == 0: internal irq number
41775f1f7eSMax Filippov		 *            second cell == 1: external irq number
42775f1f7eSMax Filippov		 */
43775f1f7eSMax Filippov		#address-cells = <0>;
44775f1f7eSMax Filippov		#interrupt-cells = <2>;
45775f1f7eSMax Filippov		interrupt-controller;
46775f1f7eSMax Filippov	};
47775f1f7eSMax Filippov
48775f1f7eSMax Filippov	pci {
49775f1f7eSMax Filippov		compatible = "pci-host-ecam-generic";
50775f1f7eSMax Filippov		device_type = "pci";
51775f1f7eSMax Filippov		#address-cells = <3>;
52775f1f7eSMax Filippov		#size-cells = <2>;
53775f1f7eSMax Filippov		#interrupt-cells = <0x1>;
54775f1f7eSMax Filippov
55775f1f7eSMax Filippov		bus-range = <0x0 0x3f>;
56775f1f7eSMax Filippov		reg = <0xc0000000 0x04000000>;
57775f1f7eSMax Filippov
58775f1f7eSMax Filippov		     // BUS_ADDRESS(3)  CPU_PHYSICAL(1)  SIZE(2)
59775f1f7eSMax Filippov		ranges = <0x01000000 0x0 0xc4000000  0xc4000000  0x0 0x04000000>,
60775f1f7eSMax Filippov			 <0x02000000 0x0 0xc8000000  0xc8000000  0x0 0x18000000>;
61775f1f7eSMax Filippov
62775f1f7eSMax Filippov		     // PCI_DEVICE(3)  INT#(1)  CONTROLLER(PHANDLE)  CONTROLLER_DATA(2)
63775f1f7eSMax Filippov		interrupt-map = <
64775f1f7eSMax Filippov			0x0000 0x0 0x0  0x1  &pic  0x0 0x1
65775f1f7eSMax Filippov			0x0800 0x0 0x0  0x1  &pic  0x1 0x1
66775f1f7eSMax Filippov			0x1000 0x0 0x0  0x1  &pic  0x2 0x1
67775f1f7eSMax Filippov			0x1800 0x0 0x0  0x1  &pic  0x3 0x1
68775f1f7eSMax Filippov			>;
69775f1f7eSMax Filippov
70775f1f7eSMax Filippov		interrupt-map-mask = <0x1800 0x0 0x0  0x7>;
71775f1f7eSMax Filippov	};
72775f1f7eSMax Filippov};
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