1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 223c2b932SScott Telford/dts-v1/; 323c2b932SScott Telford 423c2b932SScott Telford/ { 523c2b932SScott Telford compatible = "cdns,xtensa-xtfpga"; 623c2b932SScott Telford #address-cells = <1>; 723c2b932SScott Telford #size-cells = <1>; 823c2b932SScott Telford interrupt-parent = <&pic>; 923c2b932SScott Telford 1023c2b932SScott Telford chosen { 11bebbc4bcSScott Telford bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel"; 1223c2b932SScott Telford }; 1323c2b932SScott Telford 1423c2b932SScott Telford memory@0 { 1523c2b932SScott Telford device_type = "memory"; 1623c2b932SScott Telford reg = <0x00000000 0x40000000>; 1723c2b932SScott Telford }; 1823c2b932SScott Telford 1923c2b932SScott Telford cpus { 2023c2b932SScott Telford #address-cells = <1>; 2123c2b932SScott Telford #size-cells = <0>; 2223c2b932SScott Telford cpu@0 { 2323c2b932SScott Telford compatible = "cdns,xtensa-cpu"; 2423c2b932SScott Telford reg = <0>; 2523c2b932SScott Telford }; 2623c2b932SScott Telford }; 2723c2b932SScott Telford 2823c2b932SScott Telford pic: pic { 2923c2b932SScott Telford compatible = "cdns,xtensa-pic"; 3023c2b932SScott Telford #interrupt-cells = <2>; 3123c2b932SScott Telford interrupt-controller; 3223c2b932SScott Telford }; 3323c2b932SScott Telford 3423c2b932SScott Telford clocks { 3523c2b932SScott Telford osc: main-oscillator { 3623c2b932SScott Telford #clock-cells = <0>; 3723c2b932SScott Telford compatible = "fixed-clock"; 3823c2b932SScott Telford }; 3923c2b932SScott Telford }; 4023c2b932SScott Telford 4123c2b932SScott Telford soc { 4223c2b932SScott Telford #address-cells = <1>; 4323c2b932SScott Telford #size-cells = <1>; 4423c2b932SScott Telford compatible = "simple-bus"; 4523c2b932SScott Telford ranges = <0x00000000 0xf0000000 0x10000000>; 4623c2b932SScott Telford 4723c2b932SScott Telford uart0: serial@0d000000 { 4823c2b932SScott Telford compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 4923c2b932SScott Telford clocks = <&osc>, <&osc>; 5023c2b932SScott Telford clock-names = "uart_clk", "pclk"; 5123c2b932SScott Telford reg = <0x0d000000 0x1000>; 5223c2b932SScott Telford interrupts = <0 1>; 5323c2b932SScott Telford }; 5423c2b932SScott Telford }; 5523c2b932SScott Telford}; 56