1c35f1b87SPaul Walmsley// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2c35f1b87SPaul Walmsley/* Copyright (c) 2018-2019 SiFive, Inc */
3c35f1b87SPaul Walmsley
4c35f1b87SPaul Walmsley#include "fu540-c000.dtsi"
5c35f1b87SPaul Walmsley
6c35f1b87SPaul Walmsley/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
7c35f1b87SPaul Walmsley#define RTCCLK_FREQ		1000000
8c35f1b87SPaul Walmsley
9c35f1b87SPaul Walmsley/ {
10c35f1b87SPaul Walmsley	#address-cells = <2>;
11c35f1b87SPaul Walmsley	#size-cells = <2>;
12c35f1b87SPaul Walmsley	model = "SiFive HiFive Unleashed A00";
13c35f1b87SPaul Walmsley	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
14c35f1b87SPaul Walmsley
15c35f1b87SPaul Walmsley	chosen {
16c35f1b87SPaul Walmsley	};
17c35f1b87SPaul Walmsley
18c35f1b87SPaul Walmsley	cpus {
19c35f1b87SPaul Walmsley		timebase-frequency = <RTCCLK_FREQ>;
20c35f1b87SPaul Walmsley	};
21c35f1b87SPaul Walmsley
22c35f1b87SPaul Walmsley	memory@80000000 {
23c35f1b87SPaul Walmsley		device_type = "memory";
24c35f1b87SPaul Walmsley		reg = <0x0 0x80000000 0x2 0x00000000>;
25c35f1b87SPaul Walmsley	};
26c35f1b87SPaul Walmsley
27c35f1b87SPaul Walmsley	soc {
28c35f1b87SPaul Walmsley	};
29c35f1b87SPaul Walmsley
30c35f1b87SPaul Walmsley	hfclk: hfclk {
31c35f1b87SPaul Walmsley		#clock-cells = <0>;
32c35f1b87SPaul Walmsley		compatible = "fixed-clock";
33c35f1b87SPaul Walmsley		clock-frequency = <33333333>;
34c35f1b87SPaul Walmsley		clock-output-names = "hfclk";
35c35f1b87SPaul Walmsley	};
36c35f1b87SPaul Walmsley
37c35f1b87SPaul Walmsley	rtcclk: rtcclk {
38c35f1b87SPaul Walmsley		#clock-cells = <0>;
39c35f1b87SPaul Walmsley		compatible = "fixed-clock";
40c35f1b87SPaul Walmsley		clock-frequency = <RTCCLK_FREQ>;
41c35f1b87SPaul Walmsley		clock-output-names = "rtcclk";
42c35f1b87SPaul Walmsley	};
43c35f1b87SPaul Walmsley};
44c35f1b87SPaul Walmsley
4545b03df2SYash Shah&uart0 {
4645b03df2SYash Shah	status = "okay";
4745b03df2SYash Shah};
4845b03df2SYash Shah
4945b03df2SYash Shah&uart1 {
5045b03df2SYash Shah	status = "okay";
5145b03df2SYash Shah};
5245b03df2SYash Shah
5345b03df2SYash Shah&i2c0 {
5445b03df2SYash Shah	status = "okay";
5545b03df2SYash Shah};
5645b03df2SYash Shah
57c35f1b87SPaul Walmsley&qspi0 {
5845b03df2SYash Shah	status = "okay";
59c35f1b87SPaul Walmsley	flash@0 {
60c35f1b87SPaul Walmsley		compatible = "issi,is25wp256", "jedec,spi-nor";
61c35f1b87SPaul Walmsley		reg = <0>;
62c35f1b87SPaul Walmsley		spi-max-frequency = <50000000>;
63c35f1b87SPaul Walmsley		m25p,fast-read;
64c35f1b87SPaul Walmsley		spi-tx-bus-width = <4>;
65c35f1b87SPaul Walmsley		spi-rx-bus-width = <4>;
66c35f1b87SPaul Walmsley	};
67c35f1b87SPaul Walmsley};
68c35f1b87SPaul Walmsley
69c35f1b87SPaul Walmsley&qspi2 {
70c35f1b87SPaul Walmsley	status = "okay";
71c35f1b87SPaul Walmsley	mmc@0 {
72c35f1b87SPaul Walmsley		compatible = "mmc-spi-slot";
73c35f1b87SPaul Walmsley		reg = <0>;
74c35f1b87SPaul Walmsley		spi-max-frequency = <20000000>;
75c35f1b87SPaul Walmsley		voltage-ranges = <3300 3300>;
76c35f1b87SPaul Walmsley		disable-wp;
77c35f1b87SPaul Walmsley	};
78c35f1b87SPaul Walmsley};
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