1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2018-2019 SiFive, Inc */ 3 4/dts-v1/; 5 6#include <dt-bindings/clock/sifive-fu540-prci.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu540-c000", "sifive,fu540"; 12 13 aliases { 14 serial0 = &uart0; 15 serial1 = &uart1; 16 }; 17 18 chosen { 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 timebase-frequency = <1000000>; 25 cpu0: cpu@0 { 26 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 27 device_type = "cpu"; 28 i-cache-block-size = <64>; 29 i-cache-sets = <128>; 30 i-cache-size = <16384>; 31 reg = <0>; 32 riscv,isa = "rv64imac"; 33 status = "disabled"; 34 cpu0_intc: interrupt-controller { 35 #interrupt-cells = <1>; 36 compatible = "riscv,cpu-intc"; 37 interrupt-controller; 38 }; 39 }; 40 cpu1: cpu@1 { 41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 42 d-cache-block-size = <64>; 43 d-cache-sets = <64>; 44 d-cache-size = <32768>; 45 d-tlb-sets = <1>; 46 d-tlb-size = <32>; 47 device_type = "cpu"; 48 i-cache-block-size = <64>; 49 i-cache-sets = <64>; 50 i-cache-size = <32768>; 51 i-tlb-sets = <1>; 52 i-tlb-size = <32>; 53 mmu-type = "riscv,sv39"; 54 reg = <1>; 55 riscv,isa = "rv64imafdc"; 56 tlb-split; 57 cpu1_intc: interrupt-controller { 58 #interrupt-cells = <1>; 59 compatible = "riscv,cpu-intc"; 60 interrupt-controller; 61 }; 62 }; 63 cpu2: cpu@2 { 64 clock-frequency = <0>; 65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 66 d-cache-block-size = <64>; 67 d-cache-sets = <64>; 68 d-cache-size = <32768>; 69 d-tlb-sets = <1>; 70 d-tlb-size = <32>; 71 device_type = "cpu"; 72 i-cache-block-size = <64>; 73 i-cache-sets = <64>; 74 i-cache-size = <32768>; 75 i-tlb-sets = <1>; 76 i-tlb-size = <32>; 77 mmu-type = "riscv,sv39"; 78 reg = <2>; 79 riscv,isa = "rv64imafdc"; 80 tlb-split; 81 cpu2_intc: interrupt-controller { 82 #interrupt-cells = <1>; 83 compatible = "riscv,cpu-intc"; 84 interrupt-controller; 85 }; 86 }; 87 cpu3: cpu@3 { 88 clock-frequency = <0>; 89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 90 d-cache-block-size = <64>; 91 d-cache-sets = <64>; 92 d-cache-size = <32768>; 93 d-tlb-sets = <1>; 94 d-tlb-size = <32>; 95 device_type = "cpu"; 96 i-cache-block-size = <64>; 97 i-cache-sets = <64>; 98 i-cache-size = <32768>; 99 i-tlb-sets = <1>; 100 i-tlb-size = <32>; 101 mmu-type = "riscv,sv39"; 102 reg = <3>; 103 riscv,isa = "rv64imafdc"; 104 tlb-split; 105 cpu3_intc: interrupt-controller { 106 #interrupt-cells = <1>; 107 compatible = "riscv,cpu-intc"; 108 interrupt-controller; 109 }; 110 }; 111 cpu4: cpu@4 { 112 clock-frequency = <0>; 113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 114 d-cache-block-size = <64>; 115 d-cache-sets = <64>; 116 d-cache-size = <32768>; 117 d-tlb-sets = <1>; 118 d-tlb-size = <32>; 119 device_type = "cpu"; 120 i-cache-block-size = <64>; 121 i-cache-sets = <64>; 122 i-cache-size = <32768>; 123 i-tlb-sets = <1>; 124 i-tlb-size = <32>; 125 mmu-type = "riscv,sv39"; 126 reg = <4>; 127 riscv,isa = "rv64imafdc"; 128 tlb-split; 129 cpu4_intc: interrupt-controller { 130 #interrupt-cells = <1>; 131 compatible = "riscv,cpu-intc"; 132 interrupt-controller; 133 }; 134 }; 135 }; 136 soc { 137 #address-cells = <2>; 138 #size-cells = <2>; 139 compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; 140 ranges; 141 plic0: interrupt-controller@c000000 { 142 #interrupt-cells = <1>; 143 compatible = "sifive,plic-1.0.0"; 144 reg = <0x0 0xc000000 0x0 0x4000000>; 145 riscv,ndev = <53>; 146 interrupt-controller; 147 interrupts-extended = < 148 &cpu0_intc 0xffffffff 149 &cpu1_intc 0xffffffff &cpu1_intc 9 150 &cpu2_intc 0xffffffff &cpu2_intc 9 151 &cpu3_intc 0xffffffff &cpu3_intc 9 152 &cpu4_intc 0xffffffff &cpu4_intc 9>; 153 }; 154 prci: clock-controller@10000000 { 155 compatible = "sifive,fu540-c000-prci"; 156 reg = <0x0 0x10000000 0x0 0x1000>; 157 clocks = <&hfclk>, <&rtcclk>; 158 #clock-cells = <1>; 159 }; 160 uart0: serial@10010000 { 161 compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 162 reg = <0x0 0x10010000 0x0 0x1000>; 163 interrupt-parent = <&plic0>; 164 interrupts = <4>; 165 clocks = <&prci PRCI_CLK_TLCLK>; 166 status = "disabled"; 167 }; 168 uart1: serial@10011000 { 169 compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 170 reg = <0x0 0x10011000 0x0 0x1000>; 171 interrupt-parent = <&plic0>; 172 interrupts = <5>; 173 clocks = <&prci PRCI_CLK_TLCLK>; 174 status = "disabled"; 175 }; 176 i2c0: i2c@10030000 { 177 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; 178 reg = <0x0 0x10030000 0x0 0x1000>; 179 interrupt-parent = <&plic0>; 180 interrupts = <50>; 181 clocks = <&prci PRCI_CLK_TLCLK>; 182 reg-shift = <2>; 183 reg-io-width = <1>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 status = "disabled"; 187 }; 188 qspi0: spi@10040000 { 189 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 190 reg = <0x0 0x10040000 0x0 0x1000 191 0x0 0x20000000 0x0 0x10000000>; 192 interrupt-parent = <&plic0>; 193 interrupts = <51>; 194 clocks = <&prci PRCI_CLK_TLCLK>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 status = "disabled"; 198 }; 199 qspi1: spi@10041000 { 200 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 201 reg = <0x0 0x10041000 0x0 0x1000 202 0x0 0x30000000 0x0 0x10000000>; 203 interrupt-parent = <&plic0>; 204 interrupts = <52>; 205 clocks = <&prci PRCI_CLK_TLCLK>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 status = "disabled"; 209 }; 210 qspi2: spi@10050000 { 211 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 212 reg = <0x0 0x10050000 0x0 0x1000>; 213 interrupt-parent = <&plic0>; 214 interrupts = <6>; 215 clocks = <&prci PRCI_CLK_TLCLK>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 status = "disabled"; 219 }; 220 }; 221}; 222