1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4/ {
5	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
6		     "microchip,mpfs";
7
8	core_pwm0: pwm@41000000 {
9		compatible = "microchip,corepwm-rtl-v4";
10		reg = <0x0 0x41000000 0x0 0xF0>;
11		microchip,sync-update-mask = /bits/ 32 <0>;
12		#pwm-cells = <2>;
13		clocks = <&fabric_clk3>;
14		status = "disabled";
15	};
16
17	i2c2: i2c@44000000 {
18		compatible = "microchip,corei2c-rtl-v7";
19		reg = <0x0 0x44000000 0x0 0x1000>;
20		#address-cells = <1>;
21		#size-cells = <0>;
22		clocks = <&fabric_clk3>;
23		interrupt-parent = <&plic>;
24		interrupts = <122>;
25		clock-frequency = <100000>;
26		status = "disabled";
27	};
28
29	fabric_clk3: fabric-clk3 {
30		compatible = "fixed-clock";
31		#clock-cells = <0>;
32		clock-frequency = <62500000>;
33	};
34
35	fabric_clk1: fabric-clk1 {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <125000000>;
39	};
40
41	pcie: pcie@3000000000 {
42		compatible = "microchip,pcie-host-1.0";
43		#address-cells = <0x3>;
44		#interrupt-cells = <0x1>;
45		#size-cells = <0x2>;
46		device_type = "pci";
47		reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
48		reg-names = "cfg", "apb";
49		bus-range = <0x0 0x7f>;
50		interrupt-parent = <&plic>;
51		interrupts = <119>;
52		interrupt-map = <0 0 0 1 &pcie_intc 0>,
53				<0 0 0 2 &pcie_intc 1>,
54				<0 0 0 3 &pcie_intc 2>,
55				<0 0 0 4 &pcie_intc 3>;
56		interrupt-map-mask = <0 0 0 7>;
57		clocks = <&fabric_clk1>, <&fabric_clk3>;
58		clock-names = "fic1", "fic3";
59		ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
60		dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
61		msi-parent = <&pcie>;
62		msi-controller;
63		status = "disabled";
64		pcie_intc: interrupt-controller {
65			#address-cells = <0>;
66			#interrupt-cells = <1>;
67			interrupt-controller;
68		};
69	};
70};
71