1317bf653SNate Case/* 2317bf653SNate Case * Copyright (C) 2008 Extreme Engineering Solutions, Inc. 3317bf653SNate Case * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. 4317bf653SNate Case * 5317bf653SNate Case * XPedite5370 3U VPX single-board computer based on MPC8572E 6317bf653SNate Case * 7317bf653SNate Case * This is free software; you can redistribute it and/or modify 8317bf653SNate Case * it under the terms of the GNU General Public License version 2 as 9317bf653SNate Case * published by the Free Software Foundation. 10317bf653SNate Case */ 11317bf653SNate Case 12317bf653SNate Case/dts-v1/; 13317bf653SNate Case/ { 14317bf653SNate Case model = "xes,xpedite5370"; 15317bf653SNate Case compatible = "xes,xpedite5370", "xes,MPC8572"; 16317bf653SNate Case #address-cells = <2>; 17317bf653SNate Case #size-cells = <2>; 18317bf653SNate Case 19317bf653SNate Case aliases { 20317bf653SNate Case ethernet0 = &enet0; 21317bf653SNate Case ethernet1 = &enet1; 22317bf653SNate Case serial0 = &serial0; 23317bf653SNate Case serial1 = &serial1; 24317bf653SNate Case pci1 = &pci1; 25317bf653SNate Case pci2 = &pci2; 26317bf653SNate Case }; 27317bf653SNate Case 28317bf653SNate Case cpus { 29317bf653SNate Case #address-cells = <1>; 30317bf653SNate Case #size-cells = <0>; 31317bf653SNate Case 32317bf653SNate Case PowerPC,8572@0 { 33317bf653SNate Case device_type = "cpu"; 34317bf653SNate Case reg = <0x0>; 35317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 36317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 37317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 38317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 39317bf653SNate Case timebase-frequency = <0>; 40317bf653SNate Case bus-frequency = <0>; 41317bf653SNate Case clock-frequency = <0>; 42317bf653SNate Case next-level-cache = <&L2>; 43317bf653SNate Case }; 44317bf653SNate Case 45317bf653SNate Case PowerPC,8572@1 { 46317bf653SNate Case device_type = "cpu"; 47317bf653SNate Case reg = <0x1>; 48317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 49317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 50317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 51317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 52317bf653SNate Case timebase-frequency = <0>; 53317bf653SNate Case bus-frequency = <0>; 54317bf653SNate Case clock-frequency = <0>; 55317bf653SNate Case next-level-cache = <&L2>; 56317bf653SNate Case }; 57317bf653SNate Case }; 58317bf653SNate Case 59317bf653SNate Case memory { 60317bf653SNate Case device_type = "memory"; 61317bf653SNate Case reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot 62317bf653SNate Case }; 63317bf653SNate Case 64317bf653SNate Case localbus@ef005000 { 65317bf653SNate Case #address-cells = <2>; 66317bf653SNate Case #size-cells = <1>; 67317bf653SNate Case compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 68317bf653SNate Case reg = <0 0xef005000 0 0x1000>; 69317bf653SNate Case interrupts = <19 2>; 70317bf653SNate Case interrupt-parent = <&mpic>; 71317bf653SNate Case /* Local bus region mappings */ 72317bf653SNate Case ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ 73317bf653SNate Case 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ 74317bf653SNate Case 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ 75317bf653SNate Case 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ 76317bf653SNate Case 77317bf653SNate Case nor-boot@0,0 { 78317bf653SNate Case compatible = "amd,s29gl01gp", "cfi-flash"; 79317bf653SNate Case bank-width = <2>; 80317bf653SNate Case reg = <0 0 0x8000000>; /* 128MB */ 81317bf653SNate Case #address-cells = <1>; 82317bf653SNate Case #size-cells = <1>; 83317bf653SNate Case partition@0 { 84317bf653SNate Case label = "Primary user space"; 85317bf653SNate Case reg = <0x00000000 0x6f00000>; /* 111 MB */ 86317bf653SNate Case }; 87317bf653SNate Case partition@6f00000 { 88317bf653SNate Case label = "Primary kernel"; 89317bf653SNate Case reg = <0x6f00000 0x1000000>; /* 16 MB */ 90317bf653SNate Case }; 91317bf653SNate Case partition@7f00000 { 92317bf653SNate Case label = "Primary DTB"; 93317bf653SNate Case reg = <0x7f00000 0x40000>; /* 256 KB */ 94317bf653SNate Case }; 95317bf653SNate Case partition@7f40000 { 96317bf653SNate Case label = "Primary U-Boot environment"; 97317bf653SNate Case reg = <0x7f40000 0x40000>; /* 256 KB */ 98317bf653SNate Case }; 99317bf653SNate Case partition@7f80000 { 100317bf653SNate Case label = "Primary U-Boot"; 101317bf653SNate Case reg = <0x7f80000 0x80000>; /* 512 KB */ 102317bf653SNate Case read-only; 103317bf653SNate Case }; 104317bf653SNate Case }; 105317bf653SNate Case 106317bf653SNate Case nor-alternate@1,0 { 107317bf653SNate Case compatible = "amd,s29gl01gp", "cfi-flash"; 108317bf653SNate Case bank-width = <2>; 109317bf653SNate Case //reg = <0xf0000000 0x08000000>; /* 128MB */ 110317bf653SNate Case reg = <1 0 0x8000000>; /* 128MB */ 111317bf653SNate Case #address-cells = <1>; 112317bf653SNate Case #size-cells = <1>; 113317bf653SNate Case partition@0 { 114317bf653SNate Case label = "Secondary user space"; 115317bf653SNate Case reg = <0x00000000 0x6f00000>; /* 111 MB */ 116317bf653SNate Case }; 117317bf653SNate Case partition@6f00000 { 118317bf653SNate Case label = "Secondary kernel"; 119317bf653SNate Case reg = <0x6f00000 0x1000000>; /* 16 MB */ 120317bf653SNate Case }; 121317bf653SNate Case partition@7f00000 { 122317bf653SNate Case label = "Secondary DTB"; 123317bf653SNate Case reg = <0x7f00000 0x40000>; /* 256 KB */ 124317bf653SNate Case }; 125317bf653SNate Case partition@7f40000 { 126317bf653SNate Case label = "Secondary U-Boot environment"; 127317bf653SNate Case reg = <0x7f40000 0x40000>; /* 256 KB */ 128317bf653SNate Case }; 129317bf653SNate Case partition@7f80000 { 130317bf653SNate Case label = "Secondary U-Boot"; 131317bf653SNate Case reg = <0x7f80000 0x80000>; /* 512 KB */ 132317bf653SNate Case read-only; 133317bf653SNate Case }; 134317bf653SNate Case }; 135317bf653SNate Case 136317bf653SNate Case nand@2,0 { 137317bf653SNate Case #address-cells = <1>; 138317bf653SNate Case #size-cells = <1>; 139317bf653SNate Case /* 140317bf653SNate Case * Actual part could be ST Micro NAND08GW3B2A (1 GB), 141317bf653SNate Case * Micron MT29F8G08DAA (2x 512 MB), or Micron 142317bf653SNate Case * MT29F16G08FAA (2x 1 GB), depending on the build 143317bf653SNate Case * configuration 144317bf653SNate Case */ 145317bf653SNate Case compatible = "fsl,mpc8572-fcm-nand", 146317bf653SNate Case "fsl,elbc-fcm-nand"; 147317bf653SNate Case reg = <2 0 0x40000>; 148317bf653SNate Case /* U-Boot should fix this up if chip size > 1 GB */ 149317bf653SNate Case partition@0 { 150317bf653SNate Case label = "NAND Filesystem"; 151317bf653SNate Case reg = <0 0x40000000>; 152317bf653SNate Case }; 153317bf653SNate Case }; 154317bf653SNate Case 155317bf653SNate Case }; 156317bf653SNate Case 157317bf653SNate Case soc8572@ef000000 { 158317bf653SNate Case #address-cells = <1>; 159317bf653SNate Case #size-cells = <1>; 160317bf653SNate Case device_type = "soc"; 161317bf653SNate Case compatible = "fsl,mpc8572-immr", "simple-bus"; 162317bf653SNate Case ranges = <0x0 0 0xef000000 0x100000>; 163317bf653SNate Case bus-frequency = <0>; // Filled out by uboot. 164317bf653SNate Case 165317bf653SNate Case ecm-law@0 { 166317bf653SNate Case compatible = "fsl,ecm-law"; 167317bf653SNate Case reg = <0x0 0x1000>; 168317bf653SNate Case fsl,num-laws = <12>; 169317bf653SNate Case }; 170317bf653SNate Case 171317bf653SNate Case ecm@1000 { 172317bf653SNate Case compatible = "fsl,mpc8572-ecm", "fsl,ecm"; 173317bf653SNate Case reg = <0x1000 0x1000>; 174317bf653SNate Case interrupts = <17 2>; 175317bf653SNate Case interrupt-parent = <&mpic>; 176317bf653SNate Case }; 177317bf653SNate Case 178317bf653SNate Case memory-controller@2000 { 179317bf653SNate Case compatible = "fsl,mpc8572-memory-controller"; 180317bf653SNate Case reg = <0x2000 0x1000>; 181317bf653SNate Case interrupt-parent = <&mpic>; 182317bf653SNate Case interrupts = <18 2>; 183317bf653SNate Case }; 184317bf653SNate Case 185317bf653SNate Case memory-controller@6000 { 186317bf653SNate Case compatible = "fsl,mpc8572-memory-controller"; 187317bf653SNate Case reg = <0x6000 0x1000>; 188317bf653SNate Case interrupt-parent = <&mpic>; 189317bf653SNate Case interrupts = <18 2>; 190317bf653SNate Case }; 191317bf653SNate Case 192317bf653SNate Case L2: l2-cache-controller@20000 { 193317bf653SNate Case compatible = "fsl,mpc8572-l2-cache-controller"; 194317bf653SNate Case reg = <0x20000 0x1000>; 195317bf653SNate Case cache-line-size = <32>; // 32 bytes 196317bf653SNate Case cache-size = <0x100000>; // L2, 1M 197317bf653SNate Case interrupt-parent = <&mpic>; 198317bf653SNate Case interrupts = <16 2>; 199317bf653SNate Case }; 200317bf653SNate Case 201317bf653SNate Case i2c@3000 { 202317bf653SNate Case #address-cells = <1>; 203317bf653SNate Case #size-cells = <0>; 204317bf653SNate Case cell-index = <0>; 205317bf653SNate Case compatible = "fsl-i2c"; 206317bf653SNate Case reg = <0x3000 0x100>; 207317bf653SNate Case interrupts = <43 2>; 208317bf653SNate Case interrupt-parent = <&mpic>; 209317bf653SNate Case dfsrr; 210317bf653SNate Case 211317bf653SNate Case temp-sensor@48 { 212317bf653SNate Case compatible = "dallas,ds1631", "dallas,ds1621"; 213317bf653SNate Case reg = <0x48>; 214317bf653SNate Case }; 215317bf653SNate Case 216317bf653SNate Case temp-sensor@4c { 217317bf653SNate Case compatible = "adi,adt7461"; 218317bf653SNate Case reg = <0x4c>; 219317bf653SNate Case }; 220317bf653SNate Case 221317bf653SNate Case cpu-supervisor@51 { 222317bf653SNate Case compatible = "dallas,ds4510"; 223317bf653SNate Case reg = <0x51>; 224317bf653SNate Case }; 225317bf653SNate Case 226317bf653SNate Case eeprom@54 { 227317bf653SNate Case compatible = "atmel,at24c128b"; 228317bf653SNate Case reg = <0x54>; 229317bf653SNate Case }; 230317bf653SNate Case 231317bf653SNate Case rtc@68 { 232317bf653SNate Case compatible = "stm,m41t00", 233317bf653SNate Case "dallas,ds1338"; 234317bf653SNate Case reg = <0x68>; 235317bf653SNate Case }; 236317bf653SNate Case 237317bf653SNate Case pcie-switch@70 { 238317bf653SNate Case compatible = "plx,pex8518"; 239317bf653SNate Case reg = <0x70>; 240317bf653SNate Case }; 241317bf653SNate Case 242317bf653SNate Case gpio1: gpio@18 { 243317bf653SNate Case compatible = "nxp,pca9557"; 244317bf653SNate Case reg = <0x18>; 245317bf653SNate Case #gpio-cells = <2>; 246317bf653SNate Case gpio-controller; 247317bf653SNate Case polarity = <0x00>; 248317bf653SNate Case }; 249317bf653SNate Case 250317bf653SNate Case gpio2: gpio@1c { 251317bf653SNate Case compatible = "nxp,pca9557"; 252317bf653SNate Case reg = <0x1c>; 253317bf653SNate Case #gpio-cells = <2>; 254317bf653SNate Case gpio-controller; 255317bf653SNate Case polarity = <0x00>; 256317bf653SNate Case }; 257317bf653SNate Case 258317bf653SNate Case gpio3: gpio@1e { 259317bf653SNate Case compatible = "nxp,pca9557"; 260317bf653SNate Case reg = <0x1e>; 261317bf653SNate Case #gpio-cells = <2>; 262317bf653SNate Case gpio-controller; 263317bf653SNate Case polarity = <0x00>; 264317bf653SNate Case }; 265317bf653SNate Case 266317bf653SNate Case gpio4: gpio@1f { 267317bf653SNate Case compatible = "nxp,pca9557"; 268317bf653SNate Case reg = <0x1f>; 269317bf653SNate Case #gpio-cells = <2>; 270317bf653SNate Case gpio-controller; 271317bf653SNate Case polarity = <0x00>; 272317bf653SNate Case }; 273317bf653SNate Case }; 274317bf653SNate Case 275317bf653SNate Case i2c@3100 { 276317bf653SNate Case #address-cells = <1>; 277317bf653SNate Case #size-cells = <0>; 278317bf653SNate Case cell-index = <1>; 279317bf653SNate Case compatible = "fsl-i2c"; 280317bf653SNate Case reg = <0x3100 0x100>; 281317bf653SNate Case interrupts = <43 2>; 282317bf653SNate Case interrupt-parent = <&mpic>; 283317bf653SNate Case dfsrr; 284317bf653SNate Case }; 285317bf653SNate Case 286317bf653SNate Case dma@c300 { 287317bf653SNate Case #address-cells = <1>; 288317bf653SNate Case #size-cells = <1>; 289317bf653SNate Case compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 290317bf653SNate Case reg = <0xc300 0x4>; 291317bf653SNate Case ranges = <0x0 0xc100 0x200>; 292317bf653SNate Case cell-index = <1>; 293317bf653SNate Case dma-channel@0 { 294317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 295317bf653SNate Case "fsl,eloplus-dma-channel"; 296317bf653SNate Case reg = <0x0 0x80>; 297317bf653SNate Case cell-index = <0>; 298317bf653SNate Case interrupt-parent = <&mpic>; 299317bf653SNate Case interrupts = <76 2>; 300317bf653SNate Case }; 301317bf653SNate Case dma-channel@80 { 302317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 303317bf653SNate Case "fsl,eloplus-dma-channel"; 304317bf653SNate Case reg = <0x80 0x80>; 305317bf653SNate Case cell-index = <1>; 306317bf653SNate Case interrupt-parent = <&mpic>; 307317bf653SNate Case interrupts = <77 2>; 308317bf653SNate Case }; 309317bf653SNate Case dma-channel@100 { 310317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 311317bf653SNate Case "fsl,eloplus-dma-channel"; 312317bf653SNate Case reg = <0x100 0x80>; 313317bf653SNate Case cell-index = <2>; 314317bf653SNate Case interrupt-parent = <&mpic>; 315317bf653SNate Case interrupts = <78 2>; 316317bf653SNate Case }; 317317bf653SNate Case dma-channel@180 { 318317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 319317bf653SNate Case "fsl,eloplus-dma-channel"; 320317bf653SNate Case reg = <0x180 0x80>; 321317bf653SNate Case cell-index = <3>; 322317bf653SNate Case interrupt-parent = <&mpic>; 323317bf653SNate Case interrupts = <79 2>; 324317bf653SNate Case }; 325317bf653SNate Case }; 326317bf653SNate Case 327317bf653SNate Case dma@21300 { 328317bf653SNate Case #address-cells = <1>; 329317bf653SNate Case #size-cells = <1>; 330317bf653SNate Case compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 331317bf653SNate Case reg = <0x21300 0x4>; 332317bf653SNate Case ranges = <0x0 0x21100 0x200>; 333317bf653SNate Case cell-index = <0>; 334317bf653SNate Case dma-channel@0 { 335317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 336317bf653SNate Case "fsl,eloplus-dma-channel"; 337317bf653SNate Case reg = <0x0 0x80>; 338317bf653SNate Case cell-index = <0>; 339317bf653SNate Case interrupt-parent = <&mpic>; 340317bf653SNate Case interrupts = <20 2>; 341317bf653SNate Case }; 342317bf653SNate Case dma-channel@80 { 343317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 344317bf653SNate Case "fsl,eloplus-dma-channel"; 345317bf653SNate Case reg = <0x80 0x80>; 346317bf653SNate Case cell-index = <1>; 347317bf653SNate Case interrupt-parent = <&mpic>; 348317bf653SNate Case interrupts = <21 2>; 349317bf653SNate Case }; 350317bf653SNate Case dma-channel@100 { 351317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 352317bf653SNate Case "fsl,eloplus-dma-channel"; 353317bf653SNate Case reg = <0x100 0x80>; 354317bf653SNate Case cell-index = <2>; 355317bf653SNate Case interrupt-parent = <&mpic>; 356317bf653SNate Case interrupts = <22 2>; 357317bf653SNate Case }; 358317bf653SNate Case dma-channel@180 { 359317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 360317bf653SNate Case "fsl,eloplus-dma-channel"; 361317bf653SNate Case reg = <0x180 0x80>; 362317bf653SNate Case cell-index = <3>; 363317bf653SNate Case interrupt-parent = <&mpic>; 364317bf653SNate Case interrupts = <23 2>; 365317bf653SNate Case }; 366317bf653SNate Case }; 367317bf653SNate Case 368317bf653SNate Case /* eTSEC 1 */ 369317bf653SNate Case enet0: ethernet@24000 { 370317bf653SNate Case #address-cells = <1>; 371317bf653SNate Case #size-cells = <1>; 372317bf653SNate Case cell-index = <0>; 373317bf653SNate Case device_type = "network"; 374317bf653SNate Case model = "eTSEC"; 375317bf653SNate Case compatible = "gianfar"; 376317bf653SNate Case reg = <0x24000 0x1000>; 377317bf653SNate Case ranges = <0x0 0x24000 0x1000>; 378317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 379317bf653SNate Case interrupts = <29 2 30 2 34 2>; 380317bf653SNate Case interrupt-parent = <&mpic>; 381317bf653SNate Case tbi-handle = <&tbi0>; 382317bf653SNate Case phy-handle = <&phy0>; 383317bf653SNate Case phy-connection-type = "sgmii"; 384317bf653SNate Case 385317bf653SNate Case mdio@520 { 386317bf653SNate Case #address-cells = <1>; 387317bf653SNate Case #size-cells = <0>; 388317bf653SNate Case compatible = "fsl,gianfar-mdio"; 389317bf653SNate Case reg = <0x520 0x20>; 390317bf653SNate Case 391317bf653SNate Case phy0: ethernet-phy@1 { 392317bf653SNate Case interrupt-parent = <&mpic>; 393317bf653SNate Case interrupts = <8 1>; 394317bf653SNate Case reg = <0x1>; 395317bf653SNate Case }; 396317bf653SNate Case phy1: ethernet-phy@2 { 397317bf653SNate Case interrupt-parent = <&mpic>; 398317bf653SNate Case interrupts = <8 1>; 399317bf653SNate Case reg = <0x2>; 400317bf653SNate Case }; 401317bf653SNate Case tbi0: tbi-phy@11 { 402317bf653SNate Case reg = <0x11>; 403317bf653SNate Case device_type = "tbi-phy"; 404317bf653SNate Case }; 405317bf653SNate Case }; 406317bf653SNate Case }; 407317bf653SNate Case 408317bf653SNate Case /* eTSEC 2 */ 409317bf653SNate Case enet1: ethernet@25000 { 410317bf653SNate Case #address-cells = <1>; 411317bf653SNate Case #size-cells = <1>; 412317bf653SNate Case cell-index = <1>; 413317bf653SNate Case device_type = "network"; 414317bf653SNate Case model = "eTSEC"; 415317bf653SNate Case compatible = "gianfar"; 416317bf653SNate Case reg = <0x25000 0x1000>; 417317bf653SNate Case ranges = <0x0 0x25000 0x1000>; 418317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 419317bf653SNate Case interrupts = <35 2 36 2 40 2>; 420317bf653SNate Case interrupt-parent = <&mpic>; 421317bf653SNate Case tbi-handle = <&tbi1>; 422317bf653SNate Case phy-handle = <&phy1>; 423317bf653SNate Case phy-connection-type = "sgmii"; 424317bf653SNate Case 425317bf653SNate Case mdio@520 { 426317bf653SNate Case #address-cells = <1>; 427317bf653SNate Case #size-cells = <0>; 428317bf653SNate Case compatible = "fsl,gianfar-tbi"; 429317bf653SNate Case reg = <0x520 0x20>; 430317bf653SNate Case 431317bf653SNate Case tbi1: tbi-phy@11 { 432317bf653SNate Case reg = <0x11>; 433317bf653SNate Case device_type = "tbi-phy"; 434317bf653SNate Case }; 435317bf653SNate Case }; 436317bf653SNate Case }; 437317bf653SNate Case 438317bf653SNate Case /* UART0 */ 439317bf653SNate Case serial0: serial@4500 { 440317bf653SNate Case cell-index = <0>; 441317bf653SNate Case device_type = "serial"; 442f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 443317bf653SNate Case reg = <0x4500 0x100>; 444317bf653SNate Case clock-frequency = <0>; 445317bf653SNate Case interrupts = <42 2>; 446317bf653SNate Case interrupt-parent = <&mpic>; 447317bf653SNate Case }; 448317bf653SNate Case 449317bf653SNate Case /* UART1 */ 450317bf653SNate Case serial1: serial@4600 { 451317bf653SNate Case cell-index = <1>; 452317bf653SNate Case device_type = "serial"; 453f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 454317bf653SNate Case reg = <0x4600 0x100>; 455317bf653SNate Case clock-frequency = <0>; 456317bf653SNate Case interrupts = <42 2>; 457317bf653SNate Case interrupt-parent = <&mpic>; 458317bf653SNate Case }; 459317bf653SNate Case 460317bf653SNate Case global-utilities@e0000 { //global utilities block 461317bf653SNate Case compatible = "fsl,mpc8572-guts"; 462317bf653SNate Case reg = <0xe0000 0x1000>; 463317bf653SNate Case fsl,has-rstcr; 464317bf653SNate Case }; 465317bf653SNate Case 466317bf653SNate Case msi@41600 { 467317bf653SNate Case compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 468317bf653SNate Case reg = <0x41600 0x80>; 469317bf653SNate Case msi-available-ranges = <0 0x100>; 470317bf653SNate Case interrupts = < 471317bf653SNate Case 0xe0 0 472317bf653SNate Case 0xe1 0 473317bf653SNate Case 0xe2 0 474317bf653SNate Case 0xe3 0 475317bf653SNate Case 0xe4 0 476317bf653SNate Case 0xe5 0 477317bf653SNate Case 0xe6 0 478317bf653SNate Case 0xe7 0>; 479317bf653SNate Case interrupt-parent = <&mpic>; 480317bf653SNate Case }; 481317bf653SNate Case 482317bf653SNate Case crypto@30000 { 483317bf653SNate Case compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 484317bf653SNate Case "fsl,sec2.1", "fsl,sec2.0"; 485317bf653SNate Case reg = <0x30000 0x10000>; 486317bf653SNate Case interrupts = <45 2 58 2>; 487317bf653SNate Case interrupt-parent = <&mpic>; 488317bf653SNate Case fsl,num-channels = <4>; 489317bf653SNate Case fsl,channel-fifo-len = <24>; 490317bf653SNate Case fsl,exec-units-mask = <0x9fe>; 491317bf653SNate Case fsl,descriptor-types-mask = <0x3ab0ebf>; 492317bf653SNate Case }; 493317bf653SNate Case 494317bf653SNate Case mpic: pic@40000 { 495317bf653SNate Case interrupt-controller; 496317bf653SNate Case #address-cells = <0>; 497317bf653SNate Case #interrupt-cells = <2>; 498317bf653SNate Case reg = <0x40000 0x40000>; 499317bf653SNate Case compatible = "chrp,open-pic"; 500317bf653SNate Case device_type = "open-pic"; 501317bf653SNate Case }; 502317bf653SNate Case 503317bf653SNate Case gpio0: gpio@f000 { 504317bf653SNate Case compatible = "fsl,mpc8572-gpio"; 505317bf653SNate Case reg = <0xf000 0x1000>; 506317bf653SNate Case interrupts = <47 2>; 507317bf653SNate Case interrupt-parent = <&mpic>; 508317bf653SNate Case #gpio-cells = <2>; 509317bf653SNate Case gpio-controller; 510317bf653SNate Case }; 511317bf653SNate Case 512317bf653SNate Case gpio-leds { 513317bf653SNate Case compatible = "gpio-leds"; 514317bf653SNate Case 515317bf653SNate Case heartbeat { 516317bf653SNate Case label = "Heartbeat"; 517317bf653SNate Case gpios = <&gpio0 4 1>; 518317bf653SNate Case linux,default-trigger = "heartbeat"; 519317bf653SNate Case }; 520317bf653SNate Case 521317bf653SNate Case yellow { 522317bf653SNate Case label = "Yellow"; 523317bf653SNate Case gpios = <&gpio0 5 1>; 524317bf653SNate Case }; 525317bf653SNate Case 526317bf653SNate Case red { 527317bf653SNate Case label = "Red"; 528317bf653SNate Case gpios = <&gpio0 6 1>; 529317bf653SNate Case }; 530317bf653SNate Case 531317bf653SNate Case green { 532317bf653SNate Case label = "Green"; 533317bf653SNate Case gpios = <&gpio0 7 1>; 534317bf653SNate Case }; 535317bf653SNate Case }; 536317bf653SNate Case 537317bf653SNate Case /* PME (pattern-matcher) */ 538317bf653SNate Case pme@10000 { 539317bf653SNate Case compatible = "fsl,mpc8572-pme", "pme8572"; 540317bf653SNate Case reg = <0x10000 0x5000>; 541317bf653SNate Case interrupts = <57 2 64 2 65 2 66 2 67 2>; 542317bf653SNate Case interrupt-parent = <&mpic>; 543317bf653SNate Case }; 544317bf653SNate Case 545317bf653SNate Case tlu@2f000 { 546317bf653SNate Case compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 547317bf653SNate Case reg = <0x2f000 0x1000>; 54853567cf3SAdam Borowski interrupts = <61 2>; 549317bf653SNate Case interrupt-parent = <&mpic>; 550317bf653SNate Case }; 551317bf653SNate Case 552317bf653SNate Case tlu@15000 { 553317bf653SNate Case compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 554317bf653SNate Case reg = <0x15000 0x1000>; 55553567cf3SAdam Borowski interrupts = <75 2>; 556317bf653SNate Case interrupt-parent = <&mpic>; 557317bf653SNate Case }; 558317bf653SNate Case }; 559317bf653SNate Case 560317bf653SNate Case /* 561317bf653SNate Case * PCI Express controller 3 @ ef008000 is not used. 562317bf653SNate Case * This would have been pci0 on other mpc85xx platforms. 563317bf653SNate Case */ 564317bf653SNate Case 565317bf653SNate Case /* PCI Express controller 2, wired to VPX P1,P2 backplane */ 566317bf653SNate Case pci1: pcie@ef009000 { 567317bf653SNate Case compatible = "fsl,mpc8548-pcie"; 568317bf653SNate Case device_type = "pci"; 569317bf653SNate Case #interrupt-cells = <1>; 570317bf653SNate Case #size-cells = <2>; 571317bf653SNate Case #address-cells = <3>; 572317bf653SNate Case reg = <0 0xef009000 0 0x1000>; 573317bf653SNate Case bus-range = <0 255>; 574317bf653SNate Case ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 575317bf653SNate Case 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; 576317bf653SNate Case clock-frequency = <33333333>; 577317bf653SNate Case interrupt-parent = <&mpic>; 578317bf653SNate Case interrupts = <25 2>; 579317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 580317bf653SNate Case interrupt-map = < 581317bf653SNate Case /* IDSEL 0x0 */ 582317bf653SNate Case 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 583317bf653SNate Case 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 584317bf653SNate Case 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 585317bf653SNate Case 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 586317bf653SNate Case >; 587317bf653SNate Case pcie@0 { 588317bf653SNate Case reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; 589317bf653SNate Case #size-cells = <2>; 590317bf653SNate Case #address-cells = <3>; 591317bf653SNate Case device_type = "pci"; 592317bf653SNate Case ranges = <0x2000000 0x0 0xc0000000 593317bf653SNate Case 0x2000000 0x0 0xc0000000 594317bf653SNate Case 0x0 0x10000000 595317bf653SNate Case 596317bf653SNate Case 0x1000000 0x0 0x0 597317bf653SNate Case 0x1000000 0x0 0x0 598317bf653SNate Case 0x0 0x100000>; 599317bf653SNate Case }; 600317bf653SNate Case }; 601317bf653SNate Case 602317bf653SNate Case /* PCI Express controller 1, wired to PEX8518 PCIe switch */ 603317bf653SNate Case pci2: pcie@ef00a000 { 604317bf653SNate Case compatible = "fsl,mpc8548-pcie"; 605317bf653SNate Case device_type = "pci"; 606317bf653SNate Case #interrupt-cells = <1>; 607317bf653SNate Case #size-cells = <2>; 608317bf653SNate Case #address-cells = <3>; 609317bf653SNate Case reg = <0 0xef00a000 0 0x1000>; 610317bf653SNate Case bus-range = <0 255>; 611317bf653SNate Case ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 612317bf653SNate Case 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; 613317bf653SNate Case clock-frequency = <33333333>; 614317bf653SNate Case interrupt-parent = <&mpic>; 615317bf653SNate Case interrupts = <26 2>; 616317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 617317bf653SNate Case interrupt-map = < 618317bf653SNate Case /* IDSEL 0x0 */ 619317bf653SNate Case 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 620317bf653SNate Case 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 621317bf653SNate Case 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 622317bf653SNate Case 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 623317bf653SNate Case >; 624317bf653SNate Case pcie@0 { 625317bf653SNate Case reg = <0x0 0x0 0x0 0x0 0x0>; 626317bf653SNate Case #size-cells = <2>; 627317bf653SNate Case #address-cells = <3>; 628317bf653SNate Case device_type = "pci"; 629317bf653SNate Case ranges = <0x2000000 0x0 0x80000000 630317bf653SNate Case 0x2000000 0x0 0x80000000 631317bf653SNate Case 0x0 0x40000000 632317bf653SNate Case 633317bf653SNate Case 0x1000000 0x0 0x0 634317bf653SNate Case 0x1000000 0x0 0x0 635317bf653SNate Case 0x0 0x100000>; 636317bf653SNate Case }; 637317bf653SNate Case }; 638317bf653SNate Case}; 639