1317bf653SNate Case/* 2317bf653SNate Case * Copyright (C) 2008 Extreme Engineering Solutions, Inc. 3317bf653SNate Case * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. 4317bf653SNate Case * 5317bf653SNate Case * XPedite5330 3U CompactPCI module based on MPC8572E 6317bf653SNate Case * 7317bf653SNate Case * This is free software; you can redistribute it and/or modify 8317bf653SNate Case * it under the terms of the GNU General Public License version 2 as 9317bf653SNate Case * published by the Free Software Foundation. 10317bf653SNate Case */ 11317bf653SNate Case 12317bf653SNate Case/dts-v1/; 13317bf653SNate Case/ { 14317bf653SNate Case model = "xes,xpedite5330"; 15317bf653SNate Case compatible = "xes,xpedite5330", "xes,MPC8572"; 16317bf653SNate Case #address-cells = <2>; 17317bf653SNate Case #size-cells = <2>; 18317bf653SNate Case form-factor = "3U CompactPCI"; 19317bf653SNate Case boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ 20317bf653SNate Case 21317bf653SNate Case aliases { 22317bf653SNate Case ethernet0 = &enet0; 23317bf653SNate Case ethernet1 = &enet1; 24317bf653SNate Case serial0 = &serial0; 25317bf653SNate Case serial1 = &serial1; 26317bf653SNate Case pci0 = &pci0; 27317bf653SNate Case pci1 = &pci1; 28317bf653SNate Case pci2 = &pci2; 29317bf653SNate Case }; 30317bf653SNate Case 31317bf653SNate Case pmcslots { 32317bf653SNate Case #address-cells = <1>; 33317bf653SNate Case #size-cells = <0>; 34317bf653SNate Case 35317bf653SNate Case pmcslot@0 { 36317bf653SNate Case cell-index = <0>; 37317bf653SNate Case /* 38317bf653SNate Case * boolean properties (true if defined): 39317bf653SNate Case * monarch; 40317bf653SNate Case * module-present; 41317bf653SNate Case */ 42317bf653SNate Case }; 43317bf653SNate Case }; 44317bf653SNate Case 45317bf653SNate Case xmcslots { 46317bf653SNate Case #address-cells = <1>; 47317bf653SNate Case #size-cells = <0>; 48317bf653SNate Case 49317bf653SNate Case xmcslot@0 { 50317bf653SNate Case cell-index = <0>; 51317bf653SNate Case /* 52317bf653SNate Case * boolean properties (true if defined): 53317bf653SNate Case * module-present; 54317bf653SNate Case */ 55317bf653SNate Case }; 56317bf653SNate Case }; 57317bf653SNate Case 58317bf653SNate Case cpci { 59317bf653SNate Case /* 60317bf653SNate Case * boolean properties (true if defined): 61317bf653SNate Case * system-controller; 62317bf653SNate Case */ 63317bf653SNate Case system-controller; 64317bf653SNate Case }; 65317bf653SNate Case 66317bf653SNate Case cpus { 67317bf653SNate Case #address-cells = <1>; 68317bf653SNate Case #size-cells = <0>; 69317bf653SNate Case 70317bf653SNate Case PowerPC,8572@0 { 71317bf653SNate Case device_type = "cpu"; 72317bf653SNate Case reg = <0x0>; 73317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 74317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 75317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 76317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 77317bf653SNate Case timebase-frequency = <0>; 78317bf653SNate Case bus-frequency = <0>; 79317bf653SNate Case clock-frequency = <0>; 80317bf653SNate Case next-level-cache = <&L2>; 81317bf653SNate Case }; 82317bf653SNate Case 83317bf653SNate Case PowerPC,8572@1 { 84317bf653SNate Case device_type = "cpu"; 85317bf653SNate Case reg = <0x1>; 86317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 87317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 88317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 89317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 90317bf653SNate Case timebase-frequency = <0>; 91317bf653SNate Case bus-frequency = <0>; 92317bf653SNate Case clock-frequency = <0>; 93317bf653SNate Case next-level-cache = <&L2>; 94317bf653SNate Case }; 95317bf653SNate Case }; 96317bf653SNate Case 97317bf653SNate Case memory { 98317bf653SNate Case device_type = "memory"; 99317bf653SNate Case reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot 100317bf653SNate Case }; 101317bf653SNate Case 102317bf653SNate Case localbus@ef005000 { 103317bf653SNate Case #address-cells = <2>; 104317bf653SNate Case #size-cells = <1>; 105317bf653SNate Case compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 106317bf653SNate Case reg = <0 0xef005000 0 0x1000>; 107317bf653SNate Case interrupts = <19 2>; 108317bf653SNate Case interrupt-parent = <&mpic>; 109317bf653SNate Case /* Local bus region mappings */ 110317bf653SNate Case ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ 111317bf653SNate Case 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ 112317bf653SNate Case 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ 113317bf653SNate Case 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ 114317bf653SNate Case 115317bf653SNate Case nor-boot@0,0 { 116317bf653SNate Case compatible = "amd,s29gl01gp", "cfi-flash"; 117317bf653SNate Case bank-width = <2>; 118317bf653SNate Case reg = <0 0 0x8000000>; /* 128MB */ 119317bf653SNate Case #address-cells = <1>; 120317bf653SNate Case #size-cells = <1>; 121317bf653SNate Case partition@0 { 122317bf653SNate Case label = "Primary user space"; 123317bf653SNate Case reg = <0x00000000 0x6f00000>; /* 111 MB */ 124317bf653SNate Case }; 125317bf653SNate Case partition@6f00000 { 126317bf653SNate Case label = "Primary kernel"; 127317bf653SNate Case reg = <0x6f00000 0x1000000>; /* 16 MB */ 128317bf653SNate Case }; 129317bf653SNate Case partition@7f00000 { 130317bf653SNate Case label = "Primary DTB"; 131317bf653SNate Case reg = <0x7f00000 0x40000>; /* 256 KB */ 132317bf653SNate Case }; 133317bf653SNate Case partition@7f40000 { 134317bf653SNate Case label = "Primary U-Boot environment"; 135317bf653SNate Case reg = <0x7f40000 0x40000>; /* 256 KB */ 136317bf653SNate Case }; 137317bf653SNate Case partition@7f80000 { 138317bf653SNate Case label = "Primary U-Boot"; 139317bf653SNate Case reg = <0x7f80000 0x80000>; /* 512 KB */ 140317bf653SNate Case read-only; 141317bf653SNate Case }; 142317bf653SNate Case }; 143317bf653SNate Case 144317bf653SNate Case nor-alternate@1,0 { 145317bf653SNate Case compatible = "amd,s29gl01gp", "cfi-flash"; 146317bf653SNate Case bank-width = <2>; 147317bf653SNate Case //reg = <0xf0000000 0x08000000>; /* 128MB */ 148317bf653SNate Case reg = <1 0 0x8000000>; /* 128MB */ 149317bf653SNate Case #address-cells = <1>; 150317bf653SNate Case #size-cells = <1>; 151317bf653SNate Case partition@0 { 152317bf653SNate Case label = "Secondary user space"; 153317bf653SNate Case reg = <0x00000000 0x6f00000>; /* 111 MB */ 154317bf653SNate Case }; 155317bf653SNate Case partition@6f00000 { 156317bf653SNate Case label = "Secondary kernel"; 157317bf653SNate Case reg = <0x6f00000 0x1000000>; /* 16 MB */ 158317bf653SNate Case }; 159317bf653SNate Case partition@7f00000 { 160317bf653SNate Case label = "Secondary DTB"; 161317bf653SNate Case reg = <0x7f00000 0x40000>; /* 256 KB */ 162317bf653SNate Case }; 163317bf653SNate Case partition@7f40000 { 164317bf653SNate Case label = "Secondary U-Boot environment"; 165317bf653SNate Case reg = <0x7f40000 0x40000>; /* 256 KB */ 166317bf653SNate Case }; 167317bf653SNate Case partition@7f80000 { 168317bf653SNate Case label = "Secondary U-Boot"; 169317bf653SNate Case reg = <0x7f80000 0x80000>; /* 512 KB */ 170317bf653SNate Case read-only; 171317bf653SNate Case }; 172317bf653SNate Case }; 173317bf653SNate Case 174317bf653SNate Case nand@2,0 { 175317bf653SNate Case #address-cells = <1>; 176317bf653SNate Case #size-cells = <1>; 177317bf653SNate Case /* 178317bf653SNate Case * Actual part could be ST Micro NAND08GW3B2A (1 GB), 179317bf653SNate Case * Micron MT29F8G08DAA (2x 512 MB), or Micron 180317bf653SNate Case * MT29F16G08FAA (2x 1 GB), depending on the build 181317bf653SNate Case * configuration 182317bf653SNate Case */ 183317bf653SNate Case compatible = "fsl,mpc8572-fcm-nand", 184317bf653SNate Case "fsl,elbc-fcm-nand"; 185317bf653SNate Case reg = <2 0 0x40000>; 186317bf653SNate Case /* U-Boot should fix this up if chip size > 1 GB */ 187317bf653SNate Case partition@0 { 188317bf653SNate Case label = "NAND Filesystem"; 189317bf653SNate Case reg = <0 0x40000000>; 190317bf653SNate Case }; 191317bf653SNate Case }; 192317bf653SNate Case 193317bf653SNate Case }; 194317bf653SNate Case 195317bf653SNate Case soc8572@ef000000 { 196317bf653SNate Case #address-cells = <1>; 197317bf653SNate Case #size-cells = <1>; 198317bf653SNate Case device_type = "soc"; 199317bf653SNate Case compatible = "fsl,mpc8572-immr", "simple-bus"; 200317bf653SNate Case ranges = <0x0 0 0xef000000 0x100000>; 201317bf653SNate Case bus-frequency = <0>; // Filled out by uboot. 202317bf653SNate Case 203317bf653SNate Case ecm-law@0 { 204317bf653SNate Case compatible = "fsl,ecm-law"; 205317bf653SNate Case reg = <0x0 0x1000>; 206317bf653SNate Case fsl,num-laws = <12>; 207317bf653SNate Case }; 208317bf653SNate Case 209317bf653SNate Case ecm@1000 { 210317bf653SNate Case compatible = "fsl,mpc8572-ecm", "fsl,ecm"; 211317bf653SNate Case reg = <0x1000 0x1000>; 212317bf653SNate Case interrupts = <17 2>; 213317bf653SNate Case interrupt-parent = <&mpic>; 214317bf653SNate Case }; 215317bf653SNate Case 216317bf653SNate Case memory-controller@2000 { 217317bf653SNate Case compatible = "fsl,mpc8572-memory-controller"; 218317bf653SNate Case reg = <0x2000 0x1000>; 219317bf653SNate Case interrupt-parent = <&mpic>; 220317bf653SNate Case interrupts = <18 2>; 221317bf653SNate Case }; 222317bf653SNate Case 223317bf653SNate Case memory-controller@6000 { 224317bf653SNate Case compatible = "fsl,mpc8572-memory-controller"; 225317bf653SNate Case reg = <0x6000 0x1000>; 226317bf653SNate Case interrupt-parent = <&mpic>; 227317bf653SNate Case interrupts = <18 2>; 228317bf653SNate Case }; 229317bf653SNate Case 230317bf653SNate Case L2: l2-cache-controller@20000 { 231317bf653SNate Case compatible = "fsl,mpc8572-l2-cache-controller"; 232317bf653SNate Case reg = <0x20000 0x1000>; 233317bf653SNate Case cache-line-size = <32>; // 32 bytes 234317bf653SNate Case cache-size = <0x100000>; // L2, 1M 235317bf653SNate Case interrupt-parent = <&mpic>; 236317bf653SNate Case interrupts = <16 2>; 237317bf653SNate Case }; 238317bf653SNate Case 239317bf653SNate Case i2c@3000 { 240317bf653SNate Case #address-cells = <1>; 241317bf653SNate Case #size-cells = <0>; 242317bf653SNate Case cell-index = <0>; 243317bf653SNate Case compatible = "fsl-i2c"; 244317bf653SNate Case reg = <0x3000 0x100>; 245317bf653SNate Case interrupts = <43 2>; 246317bf653SNate Case interrupt-parent = <&mpic>; 247317bf653SNate Case dfsrr; 248317bf653SNate Case 249317bf653SNate Case temp-sensor@48 { 250317bf653SNate Case compatible = "dallas,ds1631", "dallas,ds1621"; 251317bf653SNate Case reg = <0x48>; 252317bf653SNate Case }; 253317bf653SNate Case 254317bf653SNate Case temp-sensor@4c { 255317bf653SNate Case compatible = "adi,adt7461"; 256317bf653SNate Case reg = <0x4c>; 257317bf653SNate Case }; 258317bf653SNate Case 259317bf653SNate Case cpu-supervisor@51 { 260317bf653SNate Case compatible = "dallas,ds4510"; 261317bf653SNate Case reg = <0x51>; 262317bf653SNate Case }; 263317bf653SNate Case 264317bf653SNate Case eeprom@54 { 265317bf653SNate Case compatible = "atmel,at24c128b"; 266317bf653SNate Case reg = <0x54>; 267317bf653SNate Case }; 268317bf653SNate Case 269317bf653SNate Case rtc@68 { 270317bf653SNate Case compatible = "stm,m41t00", 271317bf653SNate Case "dallas,ds1338"; 272317bf653SNate Case reg = <0x68>; 273317bf653SNate Case }; 274317bf653SNate Case 275317bf653SNate Case pcie-switch@70 { 276317bf653SNate Case compatible = "plx,pex8518"; 277317bf653SNate Case reg = <0x70>; 278317bf653SNate Case }; 279317bf653SNate Case 280317bf653SNate Case gpio1: gpio@18 { 281317bf653SNate Case compatible = "nxp,pca9557"; 282317bf653SNate Case reg = <0x18>; 283317bf653SNate Case #gpio-cells = <2>; 284317bf653SNate Case gpio-controller; 285317bf653SNate Case polarity = <0x00>; 286317bf653SNate Case }; 287317bf653SNate Case 288317bf653SNate Case gpio2: gpio@1c { 289317bf653SNate Case compatible = "nxp,pca9557"; 290317bf653SNate Case reg = <0x1c>; 291317bf653SNate Case #gpio-cells = <2>; 292317bf653SNate Case gpio-controller; 293317bf653SNate Case polarity = <0x00>; 294317bf653SNate Case }; 295317bf653SNate Case 296317bf653SNate Case gpio3: gpio@1e { 297317bf653SNate Case compatible = "nxp,pca9557"; 298317bf653SNate Case reg = <0x1e>; 299317bf653SNate Case #gpio-cells = <2>; 300317bf653SNate Case gpio-controller; 301317bf653SNate Case polarity = <0x00>; 302317bf653SNate Case }; 303317bf653SNate Case 304317bf653SNate Case gpio4: gpio@1f { 305317bf653SNate Case compatible = "nxp,pca9557"; 306317bf653SNate Case reg = <0x1f>; 307317bf653SNate Case #gpio-cells = <2>; 308317bf653SNate Case gpio-controller; 309317bf653SNate Case polarity = <0x00>; 310317bf653SNate Case }; 311317bf653SNate Case }; 312317bf653SNate Case 313317bf653SNate Case i2c@3100 { 314317bf653SNate Case #address-cells = <1>; 315317bf653SNate Case #size-cells = <0>; 316317bf653SNate Case cell-index = <1>; 317317bf653SNate Case compatible = "fsl-i2c"; 318317bf653SNate Case reg = <0x3100 0x100>; 319317bf653SNate Case interrupts = <43 2>; 320317bf653SNate Case interrupt-parent = <&mpic>; 321317bf653SNate Case dfsrr; 322317bf653SNate Case }; 323317bf653SNate Case 324317bf653SNate Case dma@c300 { 325317bf653SNate Case #address-cells = <1>; 326317bf653SNate Case #size-cells = <1>; 327317bf653SNate Case compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 328317bf653SNate Case reg = <0xc300 0x4>; 329317bf653SNate Case ranges = <0x0 0xc100 0x200>; 330317bf653SNate Case cell-index = <1>; 331317bf653SNate Case dma-channel@0 { 332317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 333317bf653SNate Case "fsl,eloplus-dma-channel"; 334317bf653SNate Case reg = <0x0 0x80>; 335317bf653SNate Case cell-index = <0>; 336317bf653SNate Case interrupt-parent = <&mpic>; 337317bf653SNate Case interrupts = <76 2>; 338317bf653SNate Case }; 339317bf653SNate Case dma-channel@80 { 340317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 341317bf653SNate Case "fsl,eloplus-dma-channel"; 342317bf653SNate Case reg = <0x80 0x80>; 343317bf653SNate Case cell-index = <1>; 344317bf653SNate Case interrupt-parent = <&mpic>; 345317bf653SNate Case interrupts = <77 2>; 346317bf653SNate Case }; 347317bf653SNate Case dma-channel@100 { 348317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 349317bf653SNate Case "fsl,eloplus-dma-channel"; 350317bf653SNate Case reg = <0x100 0x80>; 351317bf653SNate Case cell-index = <2>; 352317bf653SNate Case interrupt-parent = <&mpic>; 353317bf653SNate Case interrupts = <78 2>; 354317bf653SNate Case }; 355317bf653SNate Case dma-channel@180 { 356317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 357317bf653SNate Case "fsl,eloplus-dma-channel"; 358317bf653SNate Case reg = <0x180 0x80>; 359317bf653SNate Case cell-index = <3>; 360317bf653SNate Case interrupt-parent = <&mpic>; 361317bf653SNate Case interrupts = <79 2>; 362317bf653SNate Case }; 363317bf653SNate Case }; 364317bf653SNate Case 365317bf653SNate Case dma@21300 { 366317bf653SNate Case #address-cells = <1>; 367317bf653SNate Case #size-cells = <1>; 368317bf653SNate Case compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 369317bf653SNate Case reg = <0x21300 0x4>; 370317bf653SNate Case ranges = <0x0 0x21100 0x200>; 371317bf653SNate Case cell-index = <0>; 372317bf653SNate Case dma-channel@0 { 373317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 374317bf653SNate Case "fsl,eloplus-dma-channel"; 375317bf653SNate Case reg = <0x0 0x80>; 376317bf653SNate Case cell-index = <0>; 377317bf653SNate Case interrupt-parent = <&mpic>; 378317bf653SNate Case interrupts = <20 2>; 379317bf653SNate Case }; 380317bf653SNate Case dma-channel@80 { 381317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 382317bf653SNate Case "fsl,eloplus-dma-channel"; 383317bf653SNate Case reg = <0x80 0x80>; 384317bf653SNate Case cell-index = <1>; 385317bf653SNate Case interrupt-parent = <&mpic>; 386317bf653SNate Case interrupts = <21 2>; 387317bf653SNate Case }; 388317bf653SNate Case dma-channel@100 { 389317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 390317bf653SNate Case "fsl,eloplus-dma-channel"; 391317bf653SNate Case reg = <0x100 0x80>; 392317bf653SNate Case cell-index = <2>; 393317bf653SNate Case interrupt-parent = <&mpic>; 394317bf653SNate Case interrupts = <22 2>; 395317bf653SNate Case }; 396317bf653SNate Case dma-channel@180 { 397317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 398317bf653SNate Case "fsl,eloplus-dma-channel"; 399317bf653SNate Case reg = <0x180 0x80>; 400317bf653SNate Case cell-index = <3>; 401317bf653SNate Case interrupt-parent = <&mpic>; 402317bf653SNate Case interrupts = <23 2>; 403317bf653SNate Case }; 404317bf653SNate Case }; 405317bf653SNate Case 406317bf653SNate Case /* eTSEC 1 */ 407317bf653SNate Case enet0: ethernet@24000 { 408317bf653SNate Case #address-cells = <1>; 409317bf653SNate Case #size-cells = <1>; 410317bf653SNate Case cell-index = <0>; 411317bf653SNate Case device_type = "network"; 412317bf653SNate Case model = "eTSEC"; 413317bf653SNate Case compatible = "gianfar"; 414317bf653SNate Case reg = <0x24000 0x1000>; 415317bf653SNate Case ranges = <0x0 0x24000 0x1000>; 416317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 417317bf653SNate Case interrupts = <29 2 30 2 34 2>; 418317bf653SNate Case interrupt-parent = <&mpic>; 419317bf653SNate Case tbi-handle = <&tbi0>; 420317bf653SNate Case phy-handle = <&phy0>; 421317bf653SNate Case phy-connection-type = "sgmii"; 422317bf653SNate Case 423317bf653SNate Case mdio@520 { 424317bf653SNate Case #address-cells = <1>; 425317bf653SNate Case #size-cells = <0>; 426317bf653SNate Case compatible = "fsl,gianfar-mdio"; 427317bf653SNate Case reg = <0x520 0x20>; 428317bf653SNate Case 429317bf653SNate Case phy0: ethernet-phy@1 { 430317bf653SNate Case interrupt-parent = <&mpic>; 431317bf653SNate Case interrupts = <8 1>; 432317bf653SNate Case reg = <0x1>; 433317bf653SNate Case }; 434317bf653SNate Case phy1: ethernet-phy@2 { 435317bf653SNate Case interrupt-parent = <&mpic>; 436317bf653SNate Case interrupts = <8 1>; 437317bf653SNate Case reg = <0x2>; 438317bf653SNate Case }; 439317bf653SNate Case tbi0: tbi-phy@11 { 440317bf653SNate Case reg = <0x11>; 441317bf653SNate Case device_type = "tbi-phy"; 442317bf653SNate Case }; 443317bf653SNate Case }; 444317bf653SNate Case }; 445317bf653SNate Case 446317bf653SNate Case /* eTSEC 2 */ 447317bf653SNate Case enet1: ethernet@25000 { 448317bf653SNate Case #address-cells = <1>; 449317bf653SNate Case #size-cells = <1>; 450317bf653SNate Case cell-index = <1>; 451317bf653SNate Case device_type = "network"; 452317bf653SNate Case model = "eTSEC"; 453317bf653SNate Case compatible = "gianfar"; 454317bf653SNate Case reg = <0x25000 0x1000>; 455317bf653SNate Case ranges = <0x0 0x25000 0x1000>; 456317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 457317bf653SNate Case interrupts = <35 2 36 2 40 2>; 458317bf653SNate Case interrupt-parent = <&mpic>; 459317bf653SNate Case tbi-handle = <&tbi1>; 460317bf653SNate Case phy-handle = <&phy1>; 461317bf653SNate Case phy-connection-type = "sgmii"; 462317bf653SNate Case 463317bf653SNate Case mdio@520 { 464317bf653SNate Case #address-cells = <1>; 465317bf653SNate Case #size-cells = <0>; 466317bf653SNate Case compatible = "fsl,gianfar-tbi"; 467317bf653SNate Case reg = <0x520 0x20>; 468317bf653SNate Case 469317bf653SNate Case tbi1: tbi-phy@11 { 470317bf653SNate Case reg = <0x11>; 471317bf653SNate Case device_type = "tbi-phy"; 472317bf653SNate Case }; 473317bf653SNate Case }; 474317bf653SNate Case }; 475317bf653SNate Case 476317bf653SNate Case /* UART0 */ 477317bf653SNate Case serial0: serial@4500 { 478317bf653SNate Case cell-index = <0>; 479317bf653SNate Case device_type = "serial"; 480f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 481317bf653SNate Case reg = <0x4500 0x100>; 482317bf653SNate Case clock-frequency = <0>; 483317bf653SNate Case interrupts = <42 2>; 484317bf653SNate Case interrupt-parent = <&mpic>; 485317bf653SNate Case }; 486317bf653SNate Case 487317bf653SNate Case /* UART1 */ 488317bf653SNate Case serial1: serial@4600 { 489317bf653SNate Case cell-index = <1>; 490317bf653SNate Case device_type = "serial"; 491f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 492317bf653SNate Case reg = <0x4600 0x100>; 493317bf653SNate Case clock-frequency = <0>; 494317bf653SNate Case interrupts = <42 2>; 495317bf653SNate Case interrupt-parent = <&mpic>; 496317bf653SNate Case }; 497317bf653SNate Case 498317bf653SNate Case global-utilities@e0000 { //global utilities block 499317bf653SNate Case compatible = "fsl,mpc8572-guts"; 500317bf653SNate Case reg = <0xe0000 0x1000>; 501317bf653SNate Case fsl,has-rstcr; 502317bf653SNate Case }; 503317bf653SNate Case 504317bf653SNate Case msi@41600 { 505317bf653SNate Case compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 506317bf653SNate Case reg = <0x41600 0x80>; 507317bf653SNate Case msi-available-ranges = <0 0x100>; 508317bf653SNate Case interrupts = < 509317bf653SNate Case 0xe0 0 510317bf653SNate Case 0xe1 0 511317bf653SNate Case 0xe2 0 512317bf653SNate Case 0xe3 0 513317bf653SNate Case 0xe4 0 514317bf653SNate Case 0xe5 0 515317bf653SNate Case 0xe6 0 516317bf653SNate Case 0xe7 0>; 517317bf653SNate Case interrupt-parent = <&mpic>; 518317bf653SNate Case }; 519317bf653SNate Case 520317bf653SNate Case crypto@30000 { 521317bf653SNate Case compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 522317bf653SNate Case "fsl,sec2.1", "fsl,sec2.0"; 523317bf653SNate Case reg = <0x30000 0x10000>; 524317bf653SNate Case interrupts = <45 2 58 2>; 525317bf653SNate Case interrupt-parent = <&mpic>; 526317bf653SNate Case fsl,num-channels = <4>; 527317bf653SNate Case fsl,channel-fifo-len = <24>; 528317bf653SNate Case fsl,exec-units-mask = <0x9fe>; 529317bf653SNate Case fsl,descriptor-types-mask = <0x3ab0ebf>; 530317bf653SNate Case }; 531317bf653SNate Case 532317bf653SNate Case mpic: pic@40000 { 533317bf653SNate Case interrupt-controller; 534317bf653SNate Case #address-cells = <0>; 535317bf653SNate Case #interrupt-cells = <2>; 536317bf653SNate Case reg = <0x40000 0x40000>; 537317bf653SNate Case compatible = "chrp,open-pic"; 538317bf653SNate Case device_type = "open-pic"; 539317bf653SNate Case }; 540317bf653SNate Case 541317bf653SNate Case gpio0: gpio@f000 { 542317bf653SNate Case compatible = "fsl,mpc8572-gpio"; 543317bf653SNate Case reg = <0xf000 0x1000>; 544317bf653SNate Case interrupts = <47 2>; 545317bf653SNate Case interrupt-parent = <&mpic>; 546317bf653SNate Case #gpio-cells = <2>; 547317bf653SNate Case gpio-controller; 548317bf653SNate Case }; 549317bf653SNate Case 550317bf653SNate Case gpio-leds { 551317bf653SNate Case compatible = "gpio-leds"; 552317bf653SNate Case 553317bf653SNate Case heartbeat { 554317bf653SNate Case label = "Heartbeat"; 555317bf653SNate Case gpios = <&gpio0 4 1>; 556317bf653SNate Case linux,default-trigger = "heartbeat"; 557317bf653SNate Case }; 558317bf653SNate Case 559317bf653SNate Case yellow { 560317bf653SNate Case label = "Yellow"; 561317bf653SNate Case gpios = <&gpio0 5 1>; 562317bf653SNate Case }; 563317bf653SNate Case 564317bf653SNate Case red { 565317bf653SNate Case label = "Red"; 566317bf653SNate Case gpios = <&gpio0 6 1>; 567317bf653SNate Case }; 568317bf653SNate Case 569317bf653SNate Case green { 570317bf653SNate Case label = "Green"; 571317bf653SNate Case gpios = <&gpio0 7 1>; 572317bf653SNate Case }; 573317bf653SNate Case }; 574317bf653SNate Case 575317bf653SNate Case /* PME (pattern-matcher) */ 576317bf653SNate Case pme@10000 { 577317bf653SNate Case compatible = "fsl,mpc8572-pme", "pme8572"; 578317bf653SNate Case reg = <0x10000 0x5000>; 579317bf653SNate Case interrupts = <57 2 64 2 65 2 66 2 67 2>; 580317bf653SNate Case interrupt-parent = <&mpic>; 581317bf653SNate Case }; 582317bf653SNate Case 583317bf653SNate Case tlu@2f000 { 584317bf653SNate Case compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 585317bf653SNate Case reg = <0x2f000 0x1000>; 586317bf653SNate Case interupts = <61 2 >; 587317bf653SNate Case interrupt-parent = <&mpic>; 588317bf653SNate Case }; 589317bf653SNate Case 590317bf653SNate Case tlu@15000 { 591317bf653SNate Case compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 592317bf653SNate Case reg = <0x15000 0x1000>; 593317bf653SNate Case interupts = <75 2>; 594317bf653SNate Case interrupt-parent = <&mpic>; 595317bf653SNate Case }; 596317bf653SNate Case }; 597317bf653SNate Case 598317bf653SNate Case /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */ 599317bf653SNate Case pci0: pcie@ef008000 { 600317bf653SNate Case compatible = "fsl,mpc8548-pcie"; 601317bf653SNate Case device_type = "pci"; 602317bf653SNate Case #interrupt-cells = <1>; 603317bf653SNate Case #size-cells = <2>; 604317bf653SNate Case #address-cells = <3>; 605317bf653SNate Case reg = <0 0xef008000 0 0x1000>; 606317bf653SNate Case bus-range = <0 255>; 607317bf653SNate Case ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000 608317bf653SNate Case 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>; 609317bf653SNate Case clock-frequency = <33333333>; 610317bf653SNate Case interrupt-parent = <&mpic>; 611317bf653SNate Case interrupts = <24 2>; 612317bf653SNate Case interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 613317bf653SNate Case interrupt-map = < 614317bf653SNate Case 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 615317bf653SNate Case 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 616317bf653SNate Case 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 617317bf653SNate Case 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 618317bf653SNate Case >; 619317bf653SNate Case pcie@0 { 620317bf653SNate Case reg = <0x0 0x0 0x0 0x0 0x0>; 621317bf653SNate Case #size-cells = <2>; 622317bf653SNate Case #address-cells = <3>; 623317bf653SNate Case device_type = "pci"; 624317bf653SNate Case ranges = <0x02000000 0x0 0xe0000000 625317bf653SNate Case 0x02000000 0x0 0xe0000000 626317bf653SNate Case 0x0 0x10000000 627317bf653SNate Case 628317bf653SNate Case 0x01000000 0x0 0x0 629317bf653SNate Case 0x01000000 0x0 0x0 630317bf653SNate Case 0x0 0x100000>; 631317bf653SNate Case }; 632317bf653SNate Case }; 633317bf653SNate Case 634317bf653SNate Case /* PCI Express controller 2, PMC module via PEX8112 bridge */ 635317bf653SNate Case pci1: pcie@ef009000 { 636317bf653SNate Case compatible = "fsl,mpc8548-pcie"; 637317bf653SNate Case device_type = "pci"; 638317bf653SNate Case #interrupt-cells = <1>; 639317bf653SNate Case #size-cells = <2>; 640317bf653SNate Case #address-cells = <3>; 641317bf653SNate Case reg = <0 0xef009000 0 0x1000>; 642317bf653SNate Case bus-range = <0 255>; 643317bf653SNate Case ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 644317bf653SNate Case 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>; 645317bf653SNate Case clock-frequency = <33333333>; 646317bf653SNate Case interrupt-parent = <&mpic>; 647317bf653SNate Case interrupts = <25 2>; 648317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 649317bf653SNate Case interrupt-map = < 650317bf653SNate Case /* IDSEL 0x0 */ 651317bf653SNate Case 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 652317bf653SNate Case 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 653317bf653SNate Case 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 654317bf653SNate Case 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 655317bf653SNate Case >; 656317bf653SNate Case pcie@0 { 657317bf653SNate Case reg = <0x0 0x0 0x0 0x0 0x0>; 658317bf653SNate Case #size-cells = <2>; 659317bf653SNate Case #address-cells = <3>; 660317bf653SNate Case device_type = "pci"; 661317bf653SNate Case ranges = <0x2000000 0x0 0xc0000000 662317bf653SNate Case 0x2000000 0x0 0xc0000000 663317bf653SNate Case 0x0 0x10000000 664317bf653SNate Case 665317bf653SNate Case 0x1000000 0x0 0x0 666317bf653SNate Case 0x1000000 0x0 0x0 667317bf653SNate Case 0x0 0x100000>; 668317bf653SNate Case }; 669317bf653SNate Case }; 670317bf653SNate Case 671317bf653SNate Case /* PCI Express controller 1, XMC P15 */ 672317bf653SNate Case pci2: pcie@ef00a000 { 673317bf653SNate Case compatible = "fsl,mpc8548-pcie"; 674317bf653SNate Case device_type = "pci"; 675317bf653SNate Case #interrupt-cells = <1>; 676317bf653SNate Case #size-cells = <2>; 677317bf653SNate Case #address-cells = <3>; 678317bf653SNate Case reg = <0 0xef00a000 0 0x1000>; 679317bf653SNate Case bus-range = <0 255>; 680317bf653SNate Case ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 681317bf653SNate Case 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; 682317bf653SNate Case clock-frequency = <33333333>; 683317bf653SNate Case interrupt-parent = <&mpic>; 684317bf653SNate Case interrupts = <26 2>; 685317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 686317bf653SNate Case interrupt-map = < 687317bf653SNate Case /* IDSEL 0x0 */ 688317bf653SNate Case 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 689317bf653SNate Case 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 690317bf653SNate Case 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 691317bf653SNate Case 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 692317bf653SNate Case >; 693317bf653SNate Case pcie@0 { 694317bf653SNate Case reg = <0x0 0x0 0x0 0x0 0x0>; 695317bf653SNate Case #size-cells = <2>; 696317bf653SNate Case #address-cells = <3>; 697317bf653SNate Case device_type = "pci"; 698317bf653SNate Case ranges = <0x2000000 0x0 0x80000000 699317bf653SNate Case 0x2000000 0x0 0x80000000 700317bf653SNate Case 0x0 0x40000000 701317bf653SNate Case 702317bf653SNate Case 0x1000000 0x0 0x0 703317bf653SNate Case 0x1000000 0x0 0x0 704317bf653SNate Case 0x0 0x100000>; 705317bf653SNate Case }; 706317bf653SNate Case }; 707317bf653SNate Case}; 708