1ad1d7d7cSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2317bf653SNate Case/* 3317bf653SNate Case * Copyright (C) 2009 Extreme Engineering Solutions, Inc. 4317bf653SNate Case * Based on TQM8548 device tree 5317bf653SNate Case * 6317bf653SNate Case * XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the 7317bf653SNate Case * xMon boot loader memory map which differs from U-Boot's. 8317bf653SNate Case */ 9317bf653SNate Case 10317bf653SNate Case/dts-v1/; 11317bf653SNate Case 12317bf653SNate Case/ { 13317bf653SNate Case model = "xes,xpedite5200"; 14317bf653SNate Case compatible = "xes,xpedite5200", "xes,MPC8548"; 15317bf653SNate Case #address-cells = <1>; 16317bf653SNate Case #size-cells = <1>; 17317bf653SNate Case form-factor = "PMC/XMC"; 18317bf653SNate Case boot-bank = <0x0>; 19317bf653SNate Case 20317bf653SNate Case aliases { 21317bf653SNate Case ethernet0 = &enet0; 22317bf653SNate Case ethernet1 = &enet1; 23317bf653SNate Case ethernet2 = &enet2; 24317bf653SNate Case ethernet3 = &enet3; 25317bf653SNate Case 26317bf653SNate Case serial0 = &serial0; 27317bf653SNate Case serial1 = &serial1; 28317bf653SNate Case pci0 = &pci0; 29317bf653SNate Case pci1 = &pci1; 30317bf653SNate Case }; 31317bf653SNate Case 32317bf653SNate Case cpus { 33317bf653SNate Case #address-cells = <1>; 34317bf653SNate Case #size-cells = <0>; 35317bf653SNate Case 36317bf653SNate Case PowerPC,8548@0 { 37317bf653SNate Case device_type = "cpu"; 38317bf653SNate Case reg = <0>; 39317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 40317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 41317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 42317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 43317bf653SNate Case next-level-cache = <&L2>; 44317bf653SNate Case }; 45317bf653SNate Case }; 46317bf653SNate Case 47317bf653SNate Case memory { 48317bf653SNate Case device_type = "memory"; 49317bf653SNate Case reg = <0x0 0x0>; // Filled in by boot loader 50317bf653SNate Case }; 51317bf653SNate Case 52317bf653SNate Case soc@ef000000 { 53317bf653SNate Case #address-cells = <1>; 54317bf653SNate Case #size-cells = <1>; 55317bf653SNate Case device_type = "soc"; 56317bf653SNate Case ranges = <0x0 0xef000000 0x100000>; 57317bf653SNate Case bus-frequency = <0>; 58317bf653SNate Case compatible = "fsl,mpc8548-immr", "simple-bus"; 59317bf653SNate Case 60317bf653SNate Case ecm-law@0 { 61317bf653SNate Case compatible = "fsl,ecm-law"; 62317bf653SNate Case reg = <0x0 0x1000>; 63317bf653SNate Case fsl,num-laws = <12>; 64317bf653SNate Case }; 65317bf653SNate Case 66317bf653SNate Case ecm@1000 { 67317bf653SNate Case compatible = "fsl,mpc8548-ecm", "fsl,ecm"; 68317bf653SNate Case reg = <0x1000 0x1000>; 69317bf653SNate Case interrupts = <17 2>; 70317bf653SNate Case interrupt-parent = <&mpic>; 71317bf653SNate Case }; 72317bf653SNate Case 73317bf653SNate Case memory-controller@2000 { 74317bf653SNate Case compatible = "fsl,mpc8548-memory-controller"; 75317bf653SNate Case reg = <0x2000 0x1000>; 76317bf653SNate Case interrupt-parent = <&mpic>; 77317bf653SNate Case interrupts = <18 2>; 78317bf653SNate Case }; 79317bf653SNate Case 80317bf653SNate Case L2: l2-cache-controller@20000 { 81317bf653SNate Case compatible = "fsl,mpc8548-l2-cache-controller"; 82317bf653SNate Case reg = <0x20000 0x1000>; 83317bf653SNate Case cache-line-size = <32>; // 32 bytes 84317bf653SNate Case cache-size = <0x80000>; // L2, 512K 85317bf653SNate Case interrupt-parent = <&mpic>; 86317bf653SNate Case interrupts = <16 2>; 87317bf653SNate Case }; 88317bf653SNate Case 89317bf653SNate Case /* On-card I2C */ 90317bf653SNate Case i2c@3000 { 91317bf653SNate Case #address-cells = <1>; 92317bf653SNate Case #size-cells = <0>; 93317bf653SNate Case cell-index = <0>; 94317bf653SNate Case compatible = "fsl-i2c"; 95317bf653SNate Case reg = <0x3000 0x100>; 96317bf653SNate Case interrupts = <43 2>; 97317bf653SNate Case interrupt-parent = <&mpic>; 98317bf653SNate Case dfsrr; 99317bf653SNate Case 100317bf653SNate Case /* 101317bf653SNate Case * Board GPIO: 102317bf653SNate Case * 0: BRD_CFG0 (1: P14 IO present) 103317bf653SNate Case * 1: BRD_CFG1 (1: FP ethernet present) 104317bf653SNate Case * 2: BRD_CFG2 (1: XMC IO present) 105317bf653SNate Case * 3: XMC root complex indicator 106317bf653SNate Case * 4: Flash boot device indicator 107317bf653SNate Case * 5: Flash write protect enable 108317bf653SNate Case * 6: PMC monarch indicator 109317bf653SNate Case * 7: PMC EREADY 110317bf653SNate Case */ 111317bf653SNate Case gpio1: gpio@18 { 112317bf653SNate Case compatible = "nxp,pca9556"; 113317bf653SNate Case reg = <0x18>; 114317bf653SNate Case #gpio-cells = <2>; 115317bf653SNate Case gpio-controller; 116317bf653SNate Case polarity = <0x00>; 117317bf653SNate Case }; 118317bf653SNate Case 119317bf653SNate Case /* P14 GPIO */ 120317bf653SNate Case gpio2: gpio@19 { 121317bf653SNate Case compatible = "nxp,pca9556"; 122317bf653SNate Case reg = <0x19>; 123317bf653SNate Case #gpio-cells = <2>; 124317bf653SNate Case gpio-controller; 125317bf653SNate Case polarity = <0x00>; 126317bf653SNate Case }; 127317bf653SNate Case 128317bf653SNate Case eeprom@50 { 129317bf653SNate Case compatible = "atmel,at24c16"; 130317bf653SNate Case reg = <0x50>; 131317bf653SNate Case }; 132317bf653SNate Case 133317bf653SNate Case rtc@68 { 1345edc2aaeSStefan Agner compatible = "st,m41t00", 135317bf653SNate Case "dallas,ds1338"; 136317bf653SNate Case reg = <0x68>; 137317bf653SNate Case }; 138317bf653SNate Case 139317bf653SNate Case dtt@48 { 140317bf653SNate Case compatible = "maxim,max1237"; 141317bf653SNate Case reg = <0x34>; 142317bf653SNate Case }; 143317bf653SNate Case }; 144317bf653SNate Case 145317bf653SNate Case /* Off-card I2C */ 146317bf653SNate Case i2c@3100 { 147317bf653SNate Case #address-cells = <1>; 148317bf653SNate Case #size-cells = <0>; 149317bf653SNate Case cell-index = <1>; 150317bf653SNate Case compatible = "fsl-i2c"; 151317bf653SNate Case reg = <0x3100 0x100>; 152317bf653SNate Case interrupts = <43 2>; 153317bf653SNate Case interrupt-parent = <&mpic>; 154317bf653SNate Case dfsrr; 155317bf653SNate Case }; 156317bf653SNate Case 157317bf653SNate Case dma@21300 { 158317bf653SNate Case #address-cells = <1>; 159317bf653SNate Case #size-cells = <1>; 160317bf653SNate Case compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 161317bf653SNate Case reg = <0x21300 0x4>; 162317bf653SNate Case ranges = <0x0 0x21100 0x200>; 163317bf653SNate Case cell-index = <0>; 164317bf653SNate Case dma-channel@0 { 165317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 166317bf653SNate Case "fsl,eloplus-dma-channel"; 167317bf653SNate Case reg = <0x0 0x80>; 168317bf653SNate Case cell-index = <0>; 169317bf653SNate Case interrupt-parent = <&mpic>; 170317bf653SNate Case interrupts = <20 2>; 171317bf653SNate Case }; 172317bf653SNate Case dma-channel@80 { 173317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 174317bf653SNate Case "fsl,eloplus-dma-channel"; 175317bf653SNate Case reg = <0x80 0x80>; 176317bf653SNate Case cell-index = <1>; 177317bf653SNate Case interrupt-parent = <&mpic>; 178317bf653SNate Case interrupts = <21 2>; 179317bf653SNate Case }; 180317bf653SNate Case dma-channel@100 { 181317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 182317bf653SNate Case "fsl,eloplus-dma-channel"; 183317bf653SNate Case reg = <0x100 0x80>; 184317bf653SNate Case cell-index = <2>; 185317bf653SNate Case interrupt-parent = <&mpic>; 186317bf653SNate Case interrupts = <22 2>; 187317bf653SNate Case }; 188317bf653SNate Case dma-channel@180 { 189317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 190317bf653SNate Case "fsl,eloplus-dma-channel"; 191317bf653SNate Case reg = <0x180 0x80>; 192317bf653SNate Case cell-index = <3>; 193317bf653SNate Case interrupt-parent = <&mpic>; 194317bf653SNate Case interrupts = <23 2>; 195317bf653SNate Case }; 196317bf653SNate Case }; 197317bf653SNate Case 198317bf653SNate Case /* eTSEC1: Front panel port 0 */ 199317bf653SNate Case enet0: ethernet@24000 { 200317bf653SNate Case #address-cells = <1>; 201317bf653SNate Case #size-cells = <1>; 202317bf653SNate Case cell-index = <0>; 203317bf653SNate Case device_type = "network"; 204317bf653SNate Case model = "eTSEC"; 205317bf653SNate Case compatible = "gianfar"; 206317bf653SNate Case reg = <0x24000 0x1000>; 207317bf653SNate Case ranges = <0x0 0x24000 0x1000>; 208317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 209317bf653SNate Case interrupts = <29 2 30 2 34 2>; 210317bf653SNate Case interrupt-parent = <&mpic>; 211317bf653SNate Case tbi-handle = <&tbi0>; 212317bf653SNate Case phy-handle = <&phy0>; 213317bf653SNate Case 214317bf653SNate Case mdio@520 { 215317bf653SNate Case #address-cells = <1>; 216317bf653SNate Case #size-cells = <0>; 217317bf653SNate Case compatible = "fsl,gianfar-mdio"; 218317bf653SNate Case reg = <0x520 0x20>; 219317bf653SNate Case 220317bf653SNate Case phy0: ethernet-phy@1 { 221317bf653SNate Case interrupt-parent = <&mpic>; 222317bf653SNate Case interrupts = <8 1>; 223317bf653SNate Case reg = <0x1>; 224317bf653SNate Case }; 225317bf653SNate Case phy1: ethernet-phy@2 { 226317bf653SNate Case interrupt-parent = <&mpic>; 227317bf653SNate Case interrupts = <8 1>; 228317bf653SNate Case reg = <0x2>; 229317bf653SNate Case }; 230317bf653SNate Case phy2: ethernet-phy@3 { 231317bf653SNate Case interrupt-parent = <&mpic>; 232317bf653SNate Case interrupts = <8 1>; 233317bf653SNate Case reg = <0x3>; 234317bf653SNate Case }; 235317bf653SNate Case phy3: ethernet-phy@4 { 236317bf653SNate Case interrupt-parent = <&mpic>; 237317bf653SNate Case interrupts = <8 1>; 238317bf653SNate Case reg = <0x4>; 239317bf653SNate Case }; 240317bf653SNate Case tbi0: tbi-phy@11 { 241317bf653SNate Case reg = <0x11>; 242317bf653SNate Case device_type = "tbi-phy"; 243317bf653SNate Case }; 244317bf653SNate Case }; 245317bf653SNate Case }; 246317bf653SNate Case 247317bf653SNate Case /* eTSEC2: Front panel port 1 */ 248317bf653SNate Case enet1: ethernet@25000 { 249317bf653SNate Case #address-cells = <1>; 250317bf653SNate Case #size-cells = <1>; 251317bf653SNate Case cell-index = <1>; 252317bf653SNate Case device_type = "network"; 253317bf653SNate Case model = "eTSEC"; 254317bf653SNate Case compatible = "gianfar"; 255317bf653SNate Case reg = <0x25000 0x1000>; 256317bf653SNate Case ranges = <0x0 0x25000 0x1000>; 257317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 258317bf653SNate Case interrupts = <35 2 36 2 40 2>; 259317bf653SNate Case interrupt-parent = <&mpic>; 260317bf653SNate Case tbi-handle = <&tbi1>; 261317bf653SNate Case phy-handle = <&phy1>; 262317bf653SNate Case 263317bf653SNate Case mdio@520 { 264317bf653SNate Case #address-cells = <1>; 265317bf653SNate Case #size-cells = <0>; 266317bf653SNate Case compatible = "fsl,gianfar-tbi"; 267317bf653SNate Case reg = <0x520 0x20>; 268317bf653SNate Case 269317bf653SNate Case tbi1: tbi-phy@11 { 270317bf653SNate Case reg = <0x11>; 271317bf653SNate Case device_type = "tbi-phy"; 272317bf653SNate Case }; 273317bf653SNate Case }; 274317bf653SNate Case }; 275317bf653SNate Case 276317bf653SNate Case /* eTSEC3: Rear panel port 2 */ 277317bf653SNate Case enet2: ethernet@26000 { 278317bf653SNate Case #address-cells = <1>; 279317bf653SNate Case #size-cells = <1>; 280317bf653SNate Case cell-index = <2>; 281317bf653SNate Case device_type = "network"; 282317bf653SNate Case model = "eTSEC"; 283317bf653SNate Case compatible = "gianfar"; 284317bf653SNate Case reg = <0x26000 0x1000>; 285317bf653SNate Case ranges = <0x0 0x26000 0x1000>; 286317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 287317bf653SNate Case interrupts = <31 2 32 2 33 2>; 288317bf653SNate Case interrupt-parent = <&mpic>; 289317bf653SNate Case tbi-handle = <&tbi2>; 290317bf653SNate Case phy-handle = <&phy2>; 291317bf653SNate Case 292317bf653SNate Case mdio@520 { 293317bf653SNate Case #address-cells = <1>; 294317bf653SNate Case #size-cells = <0>; 295317bf653SNate Case compatible = "fsl,gianfar-tbi"; 296317bf653SNate Case reg = <0x520 0x20>; 297317bf653SNate Case 298317bf653SNate Case tbi2: tbi-phy@11 { 299317bf653SNate Case reg = <0x11>; 300317bf653SNate Case device_type = "tbi-phy"; 301317bf653SNate Case }; 302317bf653SNate Case }; 303317bf653SNate Case }; 304317bf653SNate Case 305317bf653SNate Case /* eTSEC4: Rear panel port 3 */ 306317bf653SNate Case enet3: ethernet@27000 { 307317bf653SNate Case #address-cells = <1>; 308317bf653SNate Case #size-cells = <1>; 309317bf653SNate Case cell-index = <3>; 310317bf653SNate Case device_type = "network"; 311317bf653SNate Case model = "eTSEC"; 312317bf653SNate Case compatible = "gianfar"; 313317bf653SNate Case reg = <0x27000 0x1000>; 314317bf653SNate Case ranges = <0x0 0x27000 0x1000>; 315317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 316317bf653SNate Case interrupts = <37 2 38 2 39 2>; 317317bf653SNate Case interrupt-parent = <&mpic>; 318317bf653SNate Case tbi-handle = <&tbi3>; 319317bf653SNate Case phy-handle = <&phy3>; 320317bf653SNate Case 321317bf653SNate Case mdio@520 { 322317bf653SNate Case #address-cells = <1>; 323317bf653SNate Case #size-cells = <0>; 324317bf653SNate Case compatible = "fsl,gianfar-tbi"; 325317bf653SNate Case reg = <0x520 0x20>; 326317bf653SNate Case 327317bf653SNate Case tbi3: tbi-phy@11 { 328317bf653SNate Case reg = <0x11>; 329317bf653SNate Case device_type = "tbi-phy"; 330317bf653SNate Case }; 331317bf653SNate Case }; 332317bf653SNate Case }; 333317bf653SNate Case 334317bf653SNate Case serial0: serial@4500 { 335317bf653SNate Case cell-index = <0>; 336317bf653SNate Case device_type = "serial"; 337f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 338317bf653SNate Case reg = <0x4500 0x100>; 339317bf653SNate Case clock-frequency = <0>; 340317bf653SNate Case current-speed = <9600>; 341317bf653SNate Case interrupts = <42 2>; 342317bf653SNate Case interrupt-parent = <&mpic>; 343317bf653SNate Case }; 344317bf653SNate Case 345317bf653SNate Case serial1: serial@4600 { 346317bf653SNate Case cell-index = <1>; 347317bf653SNate Case device_type = "serial"; 348f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 349317bf653SNate Case reg = <0x4600 0x100>; 350317bf653SNate Case clock-frequency = <0>; 351317bf653SNate Case current-speed = <9600>; 352317bf653SNate Case interrupts = <42 2>; 353317bf653SNate Case interrupt-parent = <&mpic>; 354317bf653SNate Case }; 355317bf653SNate Case 356317bf653SNate Case global-utilities@e0000 { // global utilities reg 357317bf653SNate Case compatible = "fsl,mpc8548-guts"; 358317bf653SNate Case reg = <0xe0000 0x1000>; 359317bf653SNate Case fsl,has-rstcr; 360317bf653SNate Case }; 361317bf653SNate Case 362317bf653SNate Case mpic: pic@40000 { 363317bf653SNate Case interrupt-controller; 364317bf653SNate Case #address-cells = <0>; 365317bf653SNate Case #interrupt-cells = <2>; 366317bf653SNate Case reg = <0x40000 0x40000>; 367317bf653SNate Case compatible = "chrp,open-pic"; 368317bf653SNate Case device_type = "open-pic"; 369317bf653SNate Case }; 370317bf653SNate Case }; 371317bf653SNate Case 372317bf653SNate Case localbus@ef005000 { 373317bf653SNate Case compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 374317bf653SNate Case "simple-bus"; 375317bf653SNate Case #address-cells = <2>; 376317bf653SNate Case #size-cells = <1>; 377317bf653SNate Case reg = <0xef005000 0x100>; // BRx, ORx, etc. 378c0f58950SDmitry Eremin-Solenikov interrupt-parent = <&mpic>; 379c0f58950SDmitry Eremin-Solenikov interrupts = <19 2>; 380317bf653SNate Case 381317bf653SNate Case ranges = < 382317bf653SNate Case 0 0x0 0xf8000000 0x08000000 // NOR boot flash 383317bf653SNate Case 1 0x0 0xf0000000 0x08000000 // NOR expansion flash 384317bf653SNate Case 2 0x0 0xe8000000 0x00010000 // NAND CE1 385317bf653SNate Case 3 0x0 0xe8010000 0x00010000 // NAND CE2 386317bf653SNate Case >; 387317bf653SNate Case 388317bf653SNate Case nor-boot@0,0 { 389317bf653SNate Case #address-cells = <1>; 390317bf653SNate Case #size-cells = <1>; 391317bf653SNate Case compatible = "cfi-flash"; 392317bf653SNate Case reg = <0 0x0 0x4000000>; 393317bf653SNate Case bank-width = <2>; 394317bf653SNate Case 395317bf653SNate Case partition@0 { 396317bf653SNate Case label = "Primary OS"; 397317bf653SNate Case reg = <0x00000000 0x180000>; 398317bf653SNate Case }; 399317bf653SNate Case partition@180000 { 400317bf653SNate Case label = "Secondary OS"; 401317bf653SNate Case reg = <0x00180000 0x180000>; 402317bf653SNate Case }; 403317bf653SNate Case partition@300000 { 404317bf653SNate Case label = "User"; 405317bf653SNate Case reg = <0x00300000 0x3c80000>; 406317bf653SNate Case }; 407317bf653SNate Case partition@3f80000 { 408317bf653SNate Case label = "Boot firmware"; 409317bf653SNate Case reg = <0x03f80000 0x80000>; 410317bf653SNate Case }; 411317bf653SNate Case }; 412317bf653SNate Case 413317bf653SNate Case nor-alternate@1,0 { 414317bf653SNate Case #address-cells = <1>; 415317bf653SNate Case #size-cells = <1>; 416317bf653SNate Case compatible = "cfi-flash"; 417317bf653SNate Case reg = <1 0x0 0x4000000>; 418317bf653SNate Case bank-width = <2>; 419317bf653SNate Case 420317bf653SNate Case partition@0 { 421317bf653SNate Case label = "Filesystem"; 422317bf653SNate Case reg = <0x00000000 0x3f80000>; 423317bf653SNate Case }; 424317bf653SNate Case partition@3f80000 { 425317bf653SNate Case label = "Alternate boot firmware"; 426317bf653SNate Case reg = <0x03f80000 0x80000>; 427317bf653SNate Case }; 428317bf653SNate Case }; 429317bf653SNate Case 430317bf653SNate Case nand@2,0 { 431317bf653SNate Case #address-cells = <1>; 432317bf653SNate Case #size-cells = <1>; 433317bf653SNate Case compatible = "xes,address-ctl-nand"; 434317bf653SNate Case reg = <2 0x0 0x10000>; 435317bf653SNate Case cle-line = <0x8>; /* CLE tied to A3 */ 436317bf653SNate Case ale-line = <0x10>; /* ALE tied to A4 */ 437317bf653SNate Case 438317bf653SNate Case partition@0 { 439317bf653SNate Case label = "NAND Filesystem"; 440317bf653SNate Case reg = <0 0x40000000>; 441317bf653SNate Case }; 442317bf653SNate Case }; 443317bf653SNate Case }; 444317bf653SNate Case 445317bf653SNate Case /* PMC interface */ 446317bf653SNate Case pci0: pci@ef008000 { 447317bf653SNate Case #interrupt-cells = <1>; 448317bf653SNate Case #size-cells = <2>; 449317bf653SNate Case #address-cells = <3>; 450317bf653SNate Case compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 451317bf653SNate Case device_type = "pci"; 452317bf653SNate Case reg = <0xef008000 0x1000>; 453317bf653SNate Case clock-frequency = <33333333>; 454317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 455317bf653SNate Case interrupt-map = < 456317bf653SNate Case /* IDSEL */ 457317bf653SNate Case 0xe000 0 0 1 &mpic 2 1 458317bf653SNate Case 0xe000 0 0 2 &mpic 3 1>; 459317bf653SNate Case 460317bf653SNate Case interrupt-parent = <&mpic>; 461317bf653SNate Case interrupts = <24 2>; 462317bf653SNate Case bus-range = <0 0>; 463317bf653SNate Case ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 464317bf653SNate Case 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>; 465317bf653SNate Case }; 466317bf653SNate Case 467317bf653SNate Case /* XMC PCIe */ 468317bf653SNate Case pci1: pcie@ef00a000 { 469317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 470317bf653SNate Case interrupt-map = < 471317bf653SNate Case /* IDSEL 0x0 */ 472317bf653SNate Case 0x00000 0 0 1 &mpic 0 1 473317bf653SNate Case 0x00000 0 0 2 &mpic 1 1 474317bf653SNate Case 0x00000 0 0 3 &mpic 2 1 475317bf653SNate Case 0x00000 0 0 4 &mpic 3 1>; 476317bf653SNate Case 477317bf653SNate Case interrupt-parent = <&mpic>; 478317bf653SNate Case interrupts = <26 2>; 479317bf653SNate Case bus-range = <0 0xff>; 480317bf653SNate Case ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 481317bf653SNate Case 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>; 482317bf653SNate Case clock-frequency = <33333333>; 483317bf653SNate Case #interrupt-cells = <1>; 484317bf653SNate Case #size-cells = <2>; 485317bf653SNate Case #address-cells = <3>; 486317bf653SNate Case reg = <0xef00a000 0x1000>; 487317bf653SNate Case compatible = "fsl,mpc8548-pcie"; 488317bf653SNate Case device_type = "pci"; 489317bf653SNate Case pcie@0 { 490317bf653SNate Case reg = <0 0 0 0 0>; 491317bf653SNate Case #size-cells = <2>; 492317bf653SNate Case #address-cells = <3>; 493317bf653SNate Case device_type = "pci"; 494317bf653SNate Case ranges = <0x02000000 0 0xc0000000 0x02000000 0 495317bf653SNate Case 0xc0000000 0 0x20000000 496317bf653SNate Case 0x01000000 0 0x00000000 0x01000000 0 497317bf653SNate Case 0x00000000 0 0x08000000>; 498317bf653SNate Case }; 499317bf653SNate Case }; 500317bf653SNate Case 501317bf653SNate Case /* Needed for dtbImage boot wrapper compatibility */ 502317bf653SNate Case chosen { 50378e5dfeaSRob Herring stdout-path = &serial0; 504317bf653SNate Case }; 505317bf653SNate Case}; 506