1317bf653SNate Case/* 2317bf653SNate Case * Copyright (C) 2009 Extreme Engineering Solutions, Inc. 3317bf653SNate Case * Based on TQM8548 device tree 4317bf653SNate Case * 5317bf653SNate Case * XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the 6317bf653SNate Case * xMon boot loader memory map which differs from U-Boot's. 7317bf653SNate Case * 8317bf653SNate Case * This is free software; you can redistribute it and/or modify 9317bf653SNate Case * it under the terms of the GNU General Public License version 2 as 10317bf653SNate Case * published by the Free Software Foundation. 11317bf653SNate Case */ 12317bf653SNate Case 13317bf653SNate Case/dts-v1/; 14317bf653SNate Case 15317bf653SNate Case/ { 16317bf653SNate Case model = "xes,xpedite5200"; 17317bf653SNate Case compatible = "xes,xpedite5200", "xes,MPC8548"; 18317bf653SNate Case #address-cells = <1>; 19317bf653SNate Case #size-cells = <1>; 20317bf653SNate Case form-factor = "PMC/XMC"; 21317bf653SNate Case boot-bank = <0x0>; 22317bf653SNate Case 23317bf653SNate Case aliases { 24317bf653SNate Case ethernet0 = &enet0; 25317bf653SNate Case ethernet1 = &enet1; 26317bf653SNate Case ethernet2 = &enet2; 27317bf653SNate Case ethernet3 = &enet3; 28317bf653SNate Case 29317bf653SNate Case serial0 = &serial0; 30317bf653SNate Case serial1 = &serial1; 31317bf653SNate Case pci0 = &pci0; 32317bf653SNate Case pci1 = &pci1; 33317bf653SNate Case }; 34317bf653SNate Case 35317bf653SNate Case cpus { 36317bf653SNate Case #address-cells = <1>; 37317bf653SNate Case #size-cells = <0>; 38317bf653SNate Case 39317bf653SNate Case PowerPC,8548@0 { 40317bf653SNate Case device_type = "cpu"; 41317bf653SNate Case reg = <0>; 42317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 43317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 44317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 45317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 46317bf653SNate Case next-level-cache = <&L2>; 47317bf653SNate Case }; 48317bf653SNate Case }; 49317bf653SNate Case 50317bf653SNate Case memory { 51317bf653SNate Case device_type = "memory"; 52317bf653SNate Case reg = <0x0 0x0>; // Filled in by boot loader 53317bf653SNate Case }; 54317bf653SNate Case 55317bf653SNate Case soc@ef000000 { 56317bf653SNate Case #address-cells = <1>; 57317bf653SNate Case #size-cells = <1>; 58317bf653SNate Case device_type = "soc"; 59317bf653SNate Case ranges = <0x0 0xef000000 0x100000>; 60317bf653SNate Case bus-frequency = <0>; 61317bf653SNate Case compatible = "fsl,mpc8548-immr", "simple-bus"; 62317bf653SNate Case 63317bf653SNate Case ecm-law@0 { 64317bf653SNate Case compatible = "fsl,ecm-law"; 65317bf653SNate Case reg = <0x0 0x1000>; 66317bf653SNate Case fsl,num-laws = <12>; 67317bf653SNate Case }; 68317bf653SNate Case 69317bf653SNate Case ecm@1000 { 70317bf653SNate Case compatible = "fsl,mpc8548-ecm", "fsl,ecm"; 71317bf653SNate Case reg = <0x1000 0x1000>; 72317bf653SNate Case interrupts = <17 2>; 73317bf653SNate Case interrupt-parent = <&mpic>; 74317bf653SNate Case }; 75317bf653SNate Case 76317bf653SNate Case memory-controller@2000 { 77317bf653SNate Case compatible = "fsl,mpc8548-memory-controller"; 78317bf653SNate Case reg = <0x2000 0x1000>; 79317bf653SNate Case interrupt-parent = <&mpic>; 80317bf653SNate Case interrupts = <18 2>; 81317bf653SNate Case }; 82317bf653SNate Case 83317bf653SNate Case L2: l2-cache-controller@20000 { 84317bf653SNate Case compatible = "fsl,mpc8548-l2-cache-controller"; 85317bf653SNate Case reg = <0x20000 0x1000>; 86317bf653SNate Case cache-line-size = <32>; // 32 bytes 87317bf653SNate Case cache-size = <0x80000>; // L2, 512K 88317bf653SNate Case interrupt-parent = <&mpic>; 89317bf653SNate Case interrupts = <16 2>; 90317bf653SNate Case }; 91317bf653SNate Case 92317bf653SNate Case /* On-card I2C */ 93317bf653SNate Case i2c@3000 { 94317bf653SNate Case #address-cells = <1>; 95317bf653SNate Case #size-cells = <0>; 96317bf653SNate Case cell-index = <0>; 97317bf653SNate Case compatible = "fsl-i2c"; 98317bf653SNate Case reg = <0x3000 0x100>; 99317bf653SNate Case interrupts = <43 2>; 100317bf653SNate Case interrupt-parent = <&mpic>; 101317bf653SNate Case dfsrr; 102317bf653SNate Case 103317bf653SNate Case /* 104317bf653SNate Case * Board GPIO: 105317bf653SNate Case * 0: BRD_CFG0 (1: P14 IO present) 106317bf653SNate Case * 1: BRD_CFG1 (1: FP ethernet present) 107317bf653SNate Case * 2: BRD_CFG2 (1: XMC IO present) 108317bf653SNate Case * 3: XMC root complex indicator 109317bf653SNate Case * 4: Flash boot device indicator 110317bf653SNate Case * 5: Flash write protect enable 111317bf653SNate Case * 6: PMC monarch indicator 112317bf653SNate Case * 7: PMC EREADY 113317bf653SNate Case */ 114317bf653SNate Case gpio1: gpio@18 { 115317bf653SNate Case compatible = "nxp,pca9556"; 116317bf653SNate Case reg = <0x18>; 117317bf653SNate Case #gpio-cells = <2>; 118317bf653SNate Case gpio-controller; 119317bf653SNate Case polarity = <0x00>; 120317bf653SNate Case }; 121317bf653SNate Case 122317bf653SNate Case /* P14 GPIO */ 123317bf653SNate Case gpio2: gpio@19 { 124317bf653SNate Case compatible = "nxp,pca9556"; 125317bf653SNate Case reg = <0x19>; 126317bf653SNate Case #gpio-cells = <2>; 127317bf653SNate Case gpio-controller; 128317bf653SNate Case polarity = <0x00>; 129317bf653SNate Case }; 130317bf653SNate Case 131317bf653SNate Case eeprom@50 { 132317bf653SNate Case compatible = "atmel,at24c16"; 133317bf653SNate Case reg = <0x50>; 134317bf653SNate Case }; 135317bf653SNate Case 136317bf653SNate Case rtc@68 { 1375edc2aaeSStefan Agner compatible = "st,m41t00", 138317bf653SNate Case "dallas,ds1338"; 139317bf653SNate Case reg = <0x68>; 140317bf653SNate Case }; 141317bf653SNate Case 142317bf653SNate Case dtt@48 { 143317bf653SNate Case compatible = "maxim,max1237"; 144317bf653SNate Case reg = <0x34>; 145317bf653SNate Case }; 146317bf653SNate Case }; 147317bf653SNate Case 148317bf653SNate Case /* Off-card I2C */ 149317bf653SNate Case i2c@3100 { 150317bf653SNate Case #address-cells = <1>; 151317bf653SNate Case #size-cells = <0>; 152317bf653SNate Case cell-index = <1>; 153317bf653SNate Case compatible = "fsl-i2c"; 154317bf653SNate Case reg = <0x3100 0x100>; 155317bf653SNate Case interrupts = <43 2>; 156317bf653SNate Case interrupt-parent = <&mpic>; 157317bf653SNate Case dfsrr; 158317bf653SNate Case }; 159317bf653SNate Case 160317bf653SNate Case dma@21300 { 161317bf653SNate Case #address-cells = <1>; 162317bf653SNate Case #size-cells = <1>; 163317bf653SNate Case compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 164317bf653SNate Case reg = <0x21300 0x4>; 165317bf653SNate Case ranges = <0x0 0x21100 0x200>; 166317bf653SNate Case cell-index = <0>; 167317bf653SNate Case dma-channel@0 { 168317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 169317bf653SNate Case "fsl,eloplus-dma-channel"; 170317bf653SNate Case reg = <0x0 0x80>; 171317bf653SNate Case cell-index = <0>; 172317bf653SNate Case interrupt-parent = <&mpic>; 173317bf653SNate Case interrupts = <20 2>; 174317bf653SNate Case }; 175317bf653SNate Case dma-channel@80 { 176317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 177317bf653SNate Case "fsl,eloplus-dma-channel"; 178317bf653SNate Case reg = <0x80 0x80>; 179317bf653SNate Case cell-index = <1>; 180317bf653SNate Case interrupt-parent = <&mpic>; 181317bf653SNate Case interrupts = <21 2>; 182317bf653SNate Case }; 183317bf653SNate Case dma-channel@100 { 184317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 185317bf653SNate Case "fsl,eloplus-dma-channel"; 186317bf653SNate Case reg = <0x100 0x80>; 187317bf653SNate Case cell-index = <2>; 188317bf653SNate Case interrupt-parent = <&mpic>; 189317bf653SNate Case interrupts = <22 2>; 190317bf653SNate Case }; 191317bf653SNate Case dma-channel@180 { 192317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 193317bf653SNate Case "fsl,eloplus-dma-channel"; 194317bf653SNate Case reg = <0x180 0x80>; 195317bf653SNate Case cell-index = <3>; 196317bf653SNate Case interrupt-parent = <&mpic>; 197317bf653SNate Case interrupts = <23 2>; 198317bf653SNate Case }; 199317bf653SNate Case }; 200317bf653SNate Case 201317bf653SNate Case /* eTSEC1: Front panel port 0 */ 202317bf653SNate Case enet0: ethernet@24000 { 203317bf653SNate Case #address-cells = <1>; 204317bf653SNate Case #size-cells = <1>; 205317bf653SNate Case cell-index = <0>; 206317bf653SNate Case device_type = "network"; 207317bf653SNate Case model = "eTSEC"; 208317bf653SNate Case compatible = "gianfar"; 209317bf653SNate Case reg = <0x24000 0x1000>; 210317bf653SNate Case ranges = <0x0 0x24000 0x1000>; 211317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 212317bf653SNate Case interrupts = <29 2 30 2 34 2>; 213317bf653SNate Case interrupt-parent = <&mpic>; 214317bf653SNate Case tbi-handle = <&tbi0>; 215317bf653SNate Case phy-handle = <&phy0>; 216317bf653SNate Case 217317bf653SNate Case mdio@520 { 218317bf653SNate Case #address-cells = <1>; 219317bf653SNate Case #size-cells = <0>; 220317bf653SNate Case compatible = "fsl,gianfar-mdio"; 221317bf653SNate Case reg = <0x520 0x20>; 222317bf653SNate Case 223317bf653SNate Case phy0: ethernet-phy@1 { 224317bf653SNate Case interrupt-parent = <&mpic>; 225317bf653SNate Case interrupts = <8 1>; 226317bf653SNate Case reg = <0x1>; 227317bf653SNate Case }; 228317bf653SNate Case phy1: ethernet-phy@2 { 229317bf653SNate Case interrupt-parent = <&mpic>; 230317bf653SNate Case interrupts = <8 1>; 231317bf653SNate Case reg = <0x2>; 232317bf653SNate Case }; 233317bf653SNate Case phy2: ethernet-phy@3 { 234317bf653SNate Case interrupt-parent = <&mpic>; 235317bf653SNate Case interrupts = <8 1>; 236317bf653SNate Case reg = <0x3>; 237317bf653SNate Case }; 238317bf653SNate Case phy3: ethernet-phy@4 { 239317bf653SNate Case interrupt-parent = <&mpic>; 240317bf653SNate Case interrupts = <8 1>; 241317bf653SNate Case reg = <0x4>; 242317bf653SNate Case }; 243317bf653SNate Case tbi0: tbi-phy@11 { 244317bf653SNate Case reg = <0x11>; 245317bf653SNate Case device_type = "tbi-phy"; 246317bf653SNate Case }; 247317bf653SNate Case }; 248317bf653SNate Case }; 249317bf653SNate Case 250317bf653SNate Case /* eTSEC2: Front panel port 1 */ 251317bf653SNate Case enet1: ethernet@25000 { 252317bf653SNate Case #address-cells = <1>; 253317bf653SNate Case #size-cells = <1>; 254317bf653SNate Case cell-index = <1>; 255317bf653SNate Case device_type = "network"; 256317bf653SNate Case model = "eTSEC"; 257317bf653SNate Case compatible = "gianfar"; 258317bf653SNate Case reg = <0x25000 0x1000>; 259317bf653SNate Case ranges = <0x0 0x25000 0x1000>; 260317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 261317bf653SNate Case interrupts = <35 2 36 2 40 2>; 262317bf653SNate Case interrupt-parent = <&mpic>; 263317bf653SNate Case tbi-handle = <&tbi1>; 264317bf653SNate Case phy-handle = <&phy1>; 265317bf653SNate Case 266317bf653SNate Case mdio@520 { 267317bf653SNate Case #address-cells = <1>; 268317bf653SNate Case #size-cells = <0>; 269317bf653SNate Case compatible = "fsl,gianfar-tbi"; 270317bf653SNate Case reg = <0x520 0x20>; 271317bf653SNate Case 272317bf653SNate Case tbi1: tbi-phy@11 { 273317bf653SNate Case reg = <0x11>; 274317bf653SNate Case device_type = "tbi-phy"; 275317bf653SNate Case }; 276317bf653SNate Case }; 277317bf653SNate Case }; 278317bf653SNate Case 279317bf653SNate Case /* eTSEC3: Rear panel port 2 */ 280317bf653SNate Case enet2: ethernet@26000 { 281317bf653SNate Case #address-cells = <1>; 282317bf653SNate Case #size-cells = <1>; 283317bf653SNate Case cell-index = <2>; 284317bf653SNate Case device_type = "network"; 285317bf653SNate Case model = "eTSEC"; 286317bf653SNate Case compatible = "gianfar"; 287317bf653SNate Case reg = <0x26000 0x1000>; 288317bf653SNate Case ranges = <0x0 0x26000 0x1000>; 289317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 290317bf653SNate Case interrupts = <31 2 32 2 33 2>; 291317bf653SNate Case interrupt-parent = <&mpic>; 292317bf653SNate Case tbi-handle = <&tbi2>; 293317bf653SNate Case phy-handle = <&phy2>; 294317bf653SNate Case 295317bf653SNate Case mdio@520 { 296317bf653SNate Case #address-cells = <1>; 297317bf653SNate Case #size-cells = <0>; 298317bf653SNate Case compatible = "fsl,gianfar-tbi"; 299317bf653SNate Case reg = <0x520 0x20>; 300317bf653SNate Case 301317bf653SNate Case tbi2: tbi-phy@11 { 302317bf653SNate Case reg = <0x11>; 303317bf653SNate Case device_type = "tbi-phy"; 304317bf653SNate Case }; 305317bf653SNate Case }; 306317bf653SNate Case }; 307317bf653SNate Case 308317bf653SNate Case /* eTSEC4: Rear panel port 3 */ 309317bf653SNate Case enet3: ethernet@27000 { 310317bf653SNate Case #address-cells = <1>; 311317bf653SNate Case #size-cells = <1>; 312317bf653SNate Case cell-index = <3>; 313317bf653SNate Case device_type = "network"; 314317bf653SNate Case model = "eTSEC"; 315317bf653SNate Case compatible = "gianfar"; 316317bf653SNate Case reg = <0x27000 0x1000>; 317317bf653SNate Case ranges = <0x0 0x27000 0x1000>; 318317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 319317bf653SNate Case interrupts = <37 2 38 2 39 2>; 320317bf653SNate Case interrupt-parent = <&mpic>; 321317bf653SNate Case tbi-handle = <&tbi3>; 322317bf653SNate Case phy-handle = <&phy3>; 323317bf653SNate Case 324317bf653SNate Case mdio@520 { 325317bf653SNate Case #address-cells = <1>; 326317bf653SNate Case #size-cells = <0>; 327317bf653SNate Case compatible = "fsl,gianfar-tbi"; 328317bf653SNate Case reg = <0x520 0x20>; 329317bf653SNate Case 330317bf653SNate Case tbi3: tbi-phy@11 { 331317bf653SNate Case reg = <0x11>; 332317bf653SNate Case device_type = "tbi-phy"; 333317bf653SNate Case }; 334317bf653SNate Case }; 335317bf653SNate Case }; 336317bf653SNate Case 337317bf653SNate Case serial0: serial@4500 { 338317bf653SNate Case cell-index = <0>; 339317bf653SNate Case device_type = "serial"; 340f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 341317bf653SNate Case reg = <0x4500 0x100>; 342317bf653SNate Case clock-frequency = <0>; 343317bf653SNate Case current-speed = <9600>; 344317bf653SNate Case interrupts = <42 2>; 345317bf653SNate Case interrupt-parent = <&mpic>; 346317bf653SNate Case }; 347317bf653SNate Case 348317bf653SNate Case serial1: serial@4600 { 349317bf653SNate Case cell-index = <1>; 350317bf653SNate Case device_type = "serial"; 351f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 352317bf653SNate Case reg = <0x4600 0x100>; 353317bf653SNate Case clock-frequency = <0>; 354317bf653SNate Case current-speed = <9600>; 355317bf653SNate Case interrupts = <42 2>; 356317bf653SNate Case interrupt-parent = <&mpic>; 357317bf653SNate Case }; 358317bf653SNate Case 359317bf653SNate Case global-utilities@e0000 { // global utilities reg 360317bf653SNate Case compatible = "fsl,mpc8548-guts"; 361317bf653SNate Case reg = <0xe0000 0x1000>; 362317bf653SNate Case fsl,has-rstcr; 363317bf653SNate Case }; 364317bf653SNate Case 365317bf653SNate Case mpic: pic@40000 { 366317bf653SNate Case interrupt-controller; 367317bf653SNate Case #address-cells = <0>; 368317bf653SNate Case #interrupt-cells = <2>; 369317bf653SNate Case reg = <0x40000 0x40000>; 370317bf653SNate Case compatible = "chrp,open-pic"; 371317bf653SNate Case device_type = "open-pic"; 372317bf653SNate Case }; 373317bf653SNate Case }; 374317bf653SNate Case 375317bf653SNate Case localbus@ef005000 { 376317bf653SNate Case compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 377317bf653SNate Case "simple-bus"; 378317bf653SNate Case #address-cells = <2>; 379317bf653SNate Case #size-cells = <1>; 380317bf653SNate Case reg = <0xef005000 0x100>; // BRx, ORx, etc. 381c0f58950SDmitry Eremin-Solenikov interrupt-parent = <&mpic>; 382c0f58950SDmitry Eremin-Solenikov interrupts = <19 2>; 383317bf653SNate Case 384317bf653SNate Case ranges = < 385317bf653SNate Case 0 0x0 0xf8000000 0x08000000 // NOR boot flash 386317bf653SNate Case 1 0x0 0xf0000000 0x08000000 // NOR expansion flash 387317bf653SNate Case 2 0x0 0xe8000000 0x00010000 // NAND CE1 388317bf653SNate Case 3 0x0 0xe8010000 0x00010000 // NAND CE2 389317bf653SNate Case >; 390317bf653SNate Case 391317bf653SNate Case nor-boot@0,0 { 392317bf653SNate Case #address-cells = <1>; 393317bf653SNate Case #size-cells = <1>; 394317bf653SNate Case compatible = "cfi-flash"; 395317bf653SNate Case reg = <0 0x0 0x4000000>; 396317bf653SNate Case bank-width = <2>; 397317bf653SNate Case 398317bf653SNate Case partition@0 { 399317bf653SNate Case label = "Primary OS"; 400317bf653SNate Case reg = <0x00000000 0x180000>; 401317bf653SNate Case }; 402317bf653SNate Case partition@180000 { 403317bf653SNate Case label = "Secondary OS"; 404317bf653SNate Case reg = <0x00180000 0x180000>; 405317bf653SNate Case }; 406317bf653SNate Case partition@300000 { 407317bf653SNate Case label = "User"; 408317bf653SNate Case reg = <0x00300000 0x3c80000>; 409317bf653SNate Case }; 410317bf653SNate Case partition@3f80000 { 411317bf653SNate Case label = "Boot firmware"; 412317bf653SNate Case reg = <0x03f80000 0x80000>; 413317bf653SNate Case }; 414317bf653SNate Case }; 415317bf653SNate Case 416317bf653SNate Case nor-alternate@1,0 { 417317bf653SNate Case #address-cells = <1>; 418317bf653SNate Case #size-cells = <1>; 419317bf653SNate Case compatible = "cfi-flash"; 420317bf653SNate Case reg = <1 0x0 0x4000000>; 421317bf653SNate Case bank-width = <2>; 422317bf653SNate Case 423317bf653SNate Case partition@0 { 424317bf653SNate Case label = "Filesystem"; 425317bf653SNate Case reg = <0x00000000 0x3f80000>; 426317bf653SNate Case }; 427317bf653SNate Case partition@3f80000 { 428317bf653SNate Case label = "Alternate boot firmware"; 429317bf653SNate Case reg = <0x03f80000 0x80000>; 430317bf653SNate Case }; 431317bf653SNate Case }; 432317bf653SNate Case 433317bf653SNate Case nand@2,0 { 434317bf653SNate Case #address-cells = <1>; 435317bf653SNate Case #size-cells = <1>; 436317bf653SNate Case compatible = "xes,address-ctl-nand"; 437317bf653SNate Case reg = <2 0x0 0x10000>; 438317bf653SNate Case cle-line = <0x8>; /* CLE tied to A3 */ 439317bf653SNate Case ale-line = <0x10>; /* ALE tied to A4 */ 440317bf653SNate Case 441317bf653SNate Case partition@0 { 442317bf653SNate Case label = "NAND Filesystem"; 443317bf653SNate Case reg = <0 0x40000000>; 444317bf653SNate Case }; 445317bf653SNate Case }; 446317bf653SNate Case }; 447317bf653SNate Case 448317bf653SNate Case /* PMC interface */ 449317bf653SNate Case pci0: pci@ef008000 { 450317bf653SNate Case #interrupt-cells = <1>; 451317bf653SNate Case #size-cells = <2>; 452317bf653SNate Case #address-cells = <3>; 453317bf653SNate Case compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 454317bf653SNate Case device_type = "pci"; 455317bf653SNate Case reg = <0xef008000 0x1000>; 456317bf653SNate Case clock-frequency = <33333333>; 457317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 458317bf653SNate Case interrupt-map = < 459317bf653SNate Case /* IDSEL */ 460317bf653SNate Case 0xe000 0 0 1 &mpic 2 1 461317bf653SNate Case 0xe000 0 0 2 &mpic 3 1>; 462317bf653SNate Case 463317bf653SNate Case interrupt-parent = <&mpic>; 464317bf653SNate Case interrupts = <24 2>; 465317bf653SNate Case bus-range = <0 0>; 466317bf653SNate Case ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 467317bf653SNate Case 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>; 468317bf653SNate Case }; 469317bf653SNate Case 470317bf653SNate Case /* XMC PCIe */ 471317bf653SNate Case pci1: pcie@ef00a000 { 472317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 473317bf653SNate Case interrupt-map = < 474317bf653SNate Case /* IDSEL 0x0 */ 475317bf653SNate Case 0x00000 0 0 1 &mpic 0 1 476317bf653SNate Case 0x00000 0 0 2 &mpic 1 1 477317bf653SNate Case 0x00000 0 0 3 &mpic 2 1 478317bf653SNate Case 0x00000 0 0 4 &mpic 3 1>; 479317bf653SNate Case 480317bf653SNate Case interrupt-parent = <&mpic>; 481317bf653SNate Case interrupts = <26 2>; 482317bf653SNate Case bus-range = <0 0xff>; 483317bf653SNate Case ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 484317bf653SNate Case 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>; 485317bf653SNate Case clock-frequency = <33333333>; 486317bf653SNate Case #interrupt-cells = <1>; 487317bf653SNate Case #size-cells = <2>; 488317bf653SNate Case #address-cells = <3>; 489317bf653SNate Case reg = <0xef00a000 0x1000>; 490317bf653SNate Case compatible = "fsl,mpc8548-pcie"; 491317bf653SNate Case device_type = "pci"; 492317bf653SNate Case pcie@0 { 493317bf653SNate Case reg = <0 0 0 0 0>; 494317bf653SNate Case #size-cells = <2>; 495317bf653SNate Case #address-cells = <3>; 496317bf653SNate Case device_type = "pci"; 497317bf653SNate Case ranges = <0x02000000 0 0xc0000000 0x02000000 0 498317bf653SNate Case 0xc0000000 0 0x20000000 499317bf653SNate Case 0x01000000 0 0x00000000 0x01000000 0 500317bf653SNate Case 0x00000000 0 0x08000000>; 501317bf653SNate Case }; 502317bf653SNate Case }; 503317bf653SNate Case 504317bf653SNate Case /* Needed for dtbImage boot wrapper compatibility */ 505317bf653SNate Case chosen { 506317bf653SNate Case linux,stdout-path = &serial0; 507317bf653SNate Case }; 508317bf653SNate Case}; 509