1317bf653SNate Case/* 2317bf653SNate Case * Copyright (C) 2009 Extreme Engineering Solutions, Inc. 3317bf653SNate Case * Based on TQM8548 device tree 4317bf653SNate Case * 5317bf653SNate Case * XPedite5200 PrPMC/XMC module based on MPC8548E 6317bf653SNate Case * 7317bf653SNate Case * This is free software; you can redistribute it and/or modify 8317bf653SNate Case * it under the terms of the GNU General Public License version 2 as 9317bf653SNate Case * published by the Free Software Foundation. 10317bf653SNate Case */ 11317bf653SNate Case 12317bf653SNate Case/dts-v1/; 13317bf653SNate Case 14317bf653SNate Case/ { 15317bf653SNate Case model = "xes,xpedite5200"; 16317bf653SNate Case compatible = "xes,xpedite5200", "xes,MPC8548"; 17317bf653SNate Case #address-cells = <1>; 18317bf653SNate Case #size-cells = <1>; 19317bf653SNate Case 20317bf653SNate Case aliases { 21317bf653SNate Case ethernet0 = &enet0; 22317bf653SNate Case ethernet1 = &enet1; 23317bf653SNate Case ethernet2 = &enet2; 24317bf653SNate Case ethernet3 = &enet3; 25317bf653SNate Case 26317bf653SNate Case serial0 = &serial0; 27317bf653SNate Case serial1 = &serial1; 28317bf653SNate Case pci0 = &pci0; 29317bf653SNate Case }; 30317bf653SNate Case 31317bf653SNate Case cpus { 32317bf653SNate Case #address-cells = <1>; 33317bf653SNate Case #size-cells = <0>; 34317bf653SNate Case 35317bf653SNate Case PowerPC,8548@0 { 36317bf653SNate Case device_type = "cpu"; 37317bf653SNate Case reg = <0>; 38317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 39317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 40317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 41317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 42317bf653SNate Case next-level-cache = <&L2>; 43317bf653SNate Case }; 44317bf653SNate Case }; 45317bf653SNate Case 46317bf653SNate Case memory { 47317bf653SNate Case device_type = "memory"; 48317bf653SNate Case reg = <0x0 0x0>; // Filled in by U-Boot 49317bf653SNate Case }; 50317bf653SNate Case 51317bf653SNate Case soc@ef000000 { 52317bf653SNate Case #address-cells = <1>; 53317bf653SNate Case #size-cells = <1>; 54317bf653SNate Case device_type = "soc"; 55317bf653SNate Case ranges = <0x0 0xef000000 0x100000>; 56317bf653SNate Case bus-frequency = <0>; 57317bf653SNate Case compatible = "fsl,mpc8548-immr", "simple-bus"; 58317bf653SNate Case 59317bf653SNate Case ecm-law@0 { 60317bf653SNate Case compatible = "fsl,ecm-law"; 61317bf653SNate Case reg = <0x0 0x1000>; 62317bf653SNate Case fsl,num-laws = <12>; 63317bf653SNate Case }; 64317bf653SNate Case 65317bf653SNate Case ecm@1000 { 66317bf653SNate Case compatible = "fsl,mpc8548-ecm", "fsl,ecm"; 67317bf653SNate Case reg = <0x1000 0x1000>; 68317bf653SNate Case interrupts = <17 2>; 69317bf653SNate Case interrupt-parent = <&mpic>; 70317bf653SNate Case }; 71317bf653SNate Case 72317bf653SNate Case memory-controller@2000 { 73317bf653SNate Case compatible = "fsl,mpc8548-memory-controller"; 74317bf653SNate Case reg = <0x2000 0x1000>; 75317bf653SNate Case interrupt-parent = <&mpic>; 76317bf653SNate Case interrupts = <18 2>; 77317bf653SNate Case }; 78317bf653SNate Case 79317bf653SNate Case L2: l2-cache-controller@20000 { 80317bf653SNate Case compatible = "fsl,mpc8548-l2-cache-controller"; 81317bf653SNate Case reg = <0x20000 0x1000>; 82317bf653SNate Case cache-line-size = <32>; // 32 bytes 83317bf653SNate Case cache-size = <0x80000>; // L2, 512K 84317bf653SNate Case interrupt-parent = <&mpic>; 85317bf653SNate Case interrupts = <16 2>; 86317bf653SNate Case }; 87317bf653SNate Case 88317bf653SNate Case /* On-card I2C */ 89317bf653SNate Case i2c@3000 { 90317bf653SNate Case #address-cells = <1>; 91317bf653SNate Case #size-cells = <0>; 92317bf653SNate Case cell-index = <0>; 93317bf653SNate Case compatible = "fsl-i2c"; 94317bf653SNate Case reg = <0x3000 0x100>; 95317bf653SNate Case interrupts = <43 2>; 96317bf653SNate Case interrupt-parent = <&mpic>; 97317bf653SNate Case dfsrr; 98317bf653SNate Case 99317bf653SNate Case /* 100317bf653SNate Case * Board GPIO: 101317bf653SNate Case * 0: BRD_CFG0 (1: P14 IO present) 102317bf653SNate Case * 1: BRD_CFG1 (1: FP ethernet present) 103317bf653SNate Case * 2: BRD_CFG2 (1: XMC IO present) 104317bf653SNate Case * 3: XMC root complex indicator 105317bf653SNate Case * 4: Flash boot device indicator 106317bf653SNate Case * 5: Flash write protect enable 107317bf653SNate Case * 6: PMC monarch indicator 108317bf653SNate Case * 7: PMC EREADY 109317bf653SNate Case */ 110317bf653SNate Case gpio1: gpio@18 { 111317bf653SNate Case compatible = "nxp,pca9556"; 112317bf653SNate Case reg = <0x18>; 113317bf653SNate Case #gpio-cells = <2>; 114317bf653SNate Case gpio-controller; 115317bf653SNate Case polarity = <0x00>; 116317bf653SNate Case }; 117317bf653SNate Case 118317bf653SNate Case /* P14 GPIO */ 119317bf653SNate Case gpio2: gpio@19 { 120317bf653SNate Case compatible = "nxp,pca9556"; 121317bf653SNate Case reg = <0x19>; 122317bf653SNate Case #gpio-cells = <2>; 123317bf653SNate Case gpio-controller; 124317bf653SNate Case polarity = <0x00>; 125317bf653SNate Case }; 126317bf653SNate Case 127317bf653SNate Case eeprom@50 { 128317bf653SNate Case compatible = "atmel,at24c16"; 129317bf653SNate Case reg = <0x50>; 130317bf653SNate Case }; 131317bf653SNate Case 132317bf653SNate Case rtc@68 { 133317bf653SNate Case compatible = "stm,m41t00", 134317bf653SNate Case "dallas,ds1338"; 135317bf653SNate Case reg = <0x68>; 136317bf653SNate Case }; 137317bf653SNate Case 138317bf653SNate Case dtt@48 { 139317bf653SNate Case compatible = "maxim,max1237"; 140317bf653SNate Case reg = <0x34>; 141317bf653SNate Case }; 142317bf653SNate Case }; 143317bf653SNate Case 144317bf653SNate Case /* Off-card I2C */ 145317bf653SNate Case i2c@3100 { 146317bf653SNate Case #address-cells = <1>; 147317bf653SNate Case #size-cells = <0>; 148317bf653SNate Case cell-index = <1>; 149317bf653SNate Case compatible = "fsl-i2c"; 150317bf653SNate Case reg = <0x3100 0x100>; 151317bf653SNate Case interrupts = <43 2>; 152317bf653SNate Case interrupt-parent = <&mpic>; 153317bf653SNate Case dfsrr; 154317bf653SNate Case }; 155317bf653SNate Case 156317bf653SNate Case dma@21300 { 157317bf653SNate Case #address-cells = <1>; 158317bf653SNate Case #size-cells = <1>; 159317bf653SNate Case compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 160317bf653SNate Case reg = <0x21300 0x4>; 161317bf653SNate Case ranges = <0x0 0x21100 0x200>; 162317bf653SNate Case cell-index = <0>; 163317bf653SNate Case dma-channel@0 { 164317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 165317bf653SNate Case "fsl,eloplus-dma-channel"; 166317bf653SNate Case reg = <0x0 0x80>; 167317bf653SNate Case cell-index = <0>; 168317bf653SNate Case interrupt-parent = <&mpic>; 169317bf653SNate Case interrupts = <20 2>; 170317bf653SNate Case }; 171317bf653SNate Case dma-channel@80 { 172317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 173317bf653SNate Case "fsl,eloplus-dma-channel"; 174317bf653SNate Case reg = <0x80 0x80>; 175317bf653SNate Case cell-index = <1>; 176317bf653SNate Case interrupt-parent = <&mpic>; 177317bf653SNate Case interrupts = <21 2>; 178317bf653SNate Case }; 179317bf653SNate Case dma-channel@100 { 180317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 181317bf653SNate Case "fsl,eloplus-dma-channel"; 182317bf653SNate Case reg = <0x100 0x80>; 183317bf653SNate Case cell-index = <2>; 184317bf653SNate Case interrupt-parent = <&mpic>; 185317bf653SNate Case interrupts = <22 2>; 186317bf653SNate Case }; 187317bf653SNate Case dma-channel@180 { 188317bf653SNate Case compatible = "fsl,mpc8548-dma-channel", 189317bf653SNate Case "fsl,eloplus-dma-channel"; 190317bf653SNate Case reg = <0x180 0x80>; 191317bf653SNate Case cell-index = <3>; 192317bf653SNate Case interrupt-parent = <&mpic>; 193317bf653SNate Case interrupts = <23 2>; 194317bf653SNate Case }; 195317bf653SNate Case }; 196317bf653SNate Case 197317bf653SNate Case /* eTSEC1: Front panel port 0 */ 198317bf653SNate Case enet0: ethernet@24000 { 199317bf653SNate Case #address-cells = <1>; 200317bf653SNate Case #size-cells = <1>; 201317bf653SNate Case cell-index = <0>; 202317bf653SNate Case device_type = "network"; 203317bf653SNate Case model = "eTSEC"; 204317bf653SNate Case compatible = "gianfar"; 205317bf653SNate Case reg = <0x24000 0x1000>; 206317bf653SNate Case ranges = <0x0 0x24000 0x1000>; 207317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 208317bf653SNate Case interrupts = <29 2 30 2 34 2>; 209317bf653SNate Case interrupt-parent = <&mpic>; 210317bf653SNate Case tbi-handle = <&tbi0>; 211317bf653SNate Case phy-handle = <&phy0>; 212317bf653SNate Case 213317bf653SNate Case mdio@520 { 214317bf653SNate Case #address-cells = <1>; 215317bf653SNate Case #size-cells = <0>; 216317bf653SNate Case compatible = "fsl,gianfar-mdio"; 217317bf653SNate Case reg = <0x520 0x20>; 218317bf653SNate Case 219317bf653SNate Case phy0: ethernet-phy@1 { 220317bf653SNate Case interrupt-parent = <&mpic>; 221317bf653SNate Case interrupts = <8 1>; 222317bf653SNate Case reg = <0x1>; 223317bf653SNate Case }; 224317bf653SNate Case phy1: ethernet-phy@2 { 225317bf653SNate Case interrupt-parent = <&mpic>; 226317bf653SNate Case interrupts = <8 1>; 227317bf653SNate Case reg = <0x2>; 228317bf653SNate Case }; 229317bf653SNate Case phy2: ethernet-phy@3 { 230317bf653SNate Case interrupt-parent = <&mpic>; 231317bf653SNate Case interrupts = <8 1>; 232317bf653SNate Case reg = <0x3>; 233317bf653SNate Case }; 234317bf653SNate Case phy3: ethernet-phy@4 { 235317bf653SNate Case interrupt-parent = <&mpic>; 236317bf653SNate Case interrupts = <8 1>; 237317bf653SNate Case reg = <0x4>; 238317bf653SNate Case }; 239317bf653SNate Case tbi0: tbi-phy@11 { 240317bf653SNate Case reg = <0x11>; 241317bf653SNate Case device_type = "tbi-phy"; 242317bf653SNate Case }; 243317bf653SNate Case }; 244317bf653SNate Case }; 245317bf653SNate Case 246317bf653SNate Case /* eTSEC2: Front panel port 1 */ 247317bf653SNate Case enet1: ethernet@25000 { 248317bf653SNate Case #address-cells = <1>; 249317bf653SNate Case #size-cells = <1>; 250317bf653SNate Case cell-index = <1>; 251317bf653SNate Case device_type = "network"; 252317bf653SNate Case model = "eTSEC"; 253317bf653SNate Case compatible = "gianfar"; 254317bf653SNate Case reg = <0x25000 0x1000>; 255317bf653SNate Case ranges = <0x0 0x25000 0x1000>; 256317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 257317bf653SNate Case interrupts = <35 2 36 2 40 2>; 258317bf653SNate Case interrupt-parent = <&mpic>; 259317bf653SNate Case tbi-handle = <&tbi1>; 260317bf653SNate Case phy-handle = <&phy1>; 261317bf653SNate Case 262317bf653SNate Case mdio@520 { 263317bf653SNate Case #address-cells = <1>; 264317bf653SNate Case #size-cells = <0>; 265317bf653SNate Case compatible = "fsl,gianfar-tbi"; 266317bf653SNate Case reg = <0x520 0x20>; 267317bf653SNate Case 268317bf653SNate Case tbi1: tbi-phy@11 { 269317bf653SNate Case reg = <0x11>; 270317bf653SNate Case device_type = "tbi-phy"; 271317bf653SNate Case }; 272317bf653SNate Case }; 273317bf653SNate Case }; 274317bf653SNate Case 275317bf653SNate Case /* eTSEC3: Rear panel port 2 */ 276317bf653SNate Case enet2: ethernet@26000 { 277317bf653SNate Case #address-cells = <1>; 278317bf653SNate Case #size-cells = <1>; 279317bf653SNate Case cell-index = <2>; 280317bf653SNate Case device_type = "network"; 281317bf653SNate Case model = "eTSEC"; 282317bf653SNate Case compatible = "gianfar"; 283317bf653SNate Case reg = <0x26000 0x1000>; 284317bf653SNate Case ranges = <0x0 0x26000 0x1000>; 285317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 286317bf653SNate Case interrupts = <31 2 32 2 33 2>; 287317bf653SNate Case interrupt-parent = <&mpic>; 288317bf653SNate Case tbi-handle = <&tbi2>; 289317bf653SNate Case phy-handle = <&phy2>; 290317bf653SNate Case 291317bf653SNate Case mdio@520 { 292317bf653SNate Case #address-cells = <1>; 293317bf653SNate Case #size-cells = <0>; 294317bf653SNate Case compatible = "fsl,gianfar-tbi"; 295317bf653SNate Case reg = <0x520 0x20>; 296317bf653SNate Case 297317bf653SNate Case tbi2: tbi-phy@11 { 298317bf653SNate Case reg = <0x11>; 299317bf653SNate Case device_type = "tbi-phy"; 300317bf653SNate Case }; 301317bf653SNate Case }; 302317bf653SNate Case }; 303317bf653SNate Case 304317bf653SNate Case /* eTSEC4: Rear panel port 3 */ 305317bf653SNate Case enet3: ethernet@27000 { 306317bf653SNate Case #address-cells = <1>; 307317bf653SNate Case #size-cells = <1>; 308317bf653SNate Case cell-index = <3>; 309317bf653SNate Case device_type = "network"; 310317bf653SNate Case model = "eTSEC"; 311317bf653SNate Case compatible = "gianfar"; 312317bf653SNate Case reg = <0x27000 0x1000>; 313317bf653SNate Case ranges = <0x0 0x27000 0x1000>; 314317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 315317bf653SNate Case interrupts = <37 2 38 2 39 2>; 316317bf653SNate Case interrupt-parent = <&mpic>; 317317bf653SNate Case tbi-handle = <&tbi3>; 318317bf653SNate Case phy-handle = <&phy3>; 319317bf653SNate Case 320317bf653SNate Case mdio@520 { 321317bf653SNate Case #address-cells = <1>; 322317bf653SNate Case #size-cells = <0>; 323317bf653SNate Case compatible = "fsl,gianfar-tbi"; 324317bf653SNate Case reg = <0x520 0x20>; 325317bf653SNate Case 326317bf653SNate Case tbi3: tbi-phy@11 { 327317bf653SNate Case reg = <0x11>; 328317bf653SNate Case device_type = "tbi-phy"; 329317bf653SNate Case }; 330317bf653SNate Case }; 331317bf653SNate Case }; 332317bf653SNate Case 333317bf653SNate Case serial0: serial@4500 { 334317bf653SNate Case cell-index = <0>; 335317bf653SNate Case device_type = "serial"; 336317bf653SNate Case compatible = "ns16550"; 337317bf653SNate Case reg = <0x4500 0x100>; 338317bf653SNate Case clock-frequency = <0>; 339317bf653SNate Case current-speed = <115200>; 340317bf653SNate Case interrupts = <42 2>; 341317bf653SNate Case interrupt-parent = <&mpic>; 342317bf653SNate Case }; 343317bf653SNate Case 344317bf653SNate Case serial1: serial@4600 { 345317bf653SNate Case cell-index = <1>; 346317bf653SNate Case device_type = "serial"; 347317bf653SNate Case compatible = "ns16550"; 348317bf653SNate Case reg = <0x4600 0x100>; 349317bf653SNate Case clock-frequency = <0>; 350317bf653SNate Case current-speed = <115200>; 351317bf653SNate Case interrupts = <42 2>; 352317bf653SNate Case interrupt-parent = <&mpic>; 353317bf653SNate Case }; 354317bf653SNate Case 355317bf653SNate Case global-utilities@e0000 { // global utilities reg 356317bf653SNate Case compatible = "fsl,mpc8548-guts"; 357317bf653SNate Case reg = <0xe0000 0x1000>; 358317bf653SNate Case fsl,has-rstcr; 359317bf653SNate Case }; 360317bf653SNate Case 361317bf653SNate Case mpic: pic@40000 { 362317bf653SNate Case interrupt-controller; 363317bf653SNate Case #address-cells = <0>; 364317bf653SNate Case #interrupt-cells = <2>; 365317bf653SNate Case reg = <0x40000 0x40000>; 366317bf653SNate Case compatible = "chrp,open-pic"; 367317bf653SNate Case device_type = "open-pic"; 368317bf653SNate Case }; 369317bf653SNate Case }; 370317bf653SNate Case 371317bf653SNate Case localbus@ef005000 { 372317bf653SNate Case compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 373317bf653SNate Case "simple-bus"; 374317bf653SNate Case #address-cells = <2>; 375317bf653SNate Case #size-cells = <1>; 376317bf653SNate Case reg = <0xef005000 0x100>; // BRx, ORx, etc. 377317bf653SNate Case 378317bf653SNate Case ranges = < 379317bf653SNate Case 0 0x0 0xfc000000 0x04000000 // NOR boot flash 380317bf653SNate Case 1 0x0 0xf8000000 0x04000000 // NOR expansion flash 381317bf653SNate Case 2 0x0 0xef800000 0x00010000 // NAND CE1 382317bf653SNate Case 3 0x0 0xef840000 0x00010000 // NAND CE2 383317bf653SNate Case >; 384317bf653SNate Case 385317bf653SNate Case nor-boot@0,0 { 386317bf653SNate Case #address-cells = <1>; 387317bf653SNate Case #size-cells = <1>; 388317bf653SNate Case compatible = "cfi-flash"; 389317bf653SNate Case reg = <0 0x0 0x4000000>; 390317bf653SNate Case bank-width = <2>; 391317bf653SNate Case 392317bf653SNate Case partition@0 { 393317bf653SNate Case label = "Primary OS"; 394317bf653SNate Case reg = <0x00000000 0x180000>; 395317bf653SNate Case }; 396317bf653SNate Case partition@180000 { 397317bf653SNate Case label = "Secondary OS"; 398317bf653SNate Case reg = <0x00180000 0x180000>; 399317bf653SNate Case }; 400317bf653SNate Case partition@300000 { 401317bf653SNate Case label = "User"; 402317bf653SNate Case reg = <0x00300000 0x3c80000>; 403317bf653SNate Case }; 404317bf653SNate Case partition@3f80000 { 405317bf653SNate Case label = "Boot firmware"; 406317bf653SNate Case reg = <0x03f80000 0x80000>; 407317bf653SNate Case }; 408317bf653SNate Case }; 409317bf653SNate Case 410317bf653SNate Case nor-alternate@1,0 { 411317bf653SNate Case #address-cells = <1>; 412317bf653SNate Case #size-cells = <1>; 413317bf653SNate Case compatible = "cfi-flash"; 414317bf653SNate Case reg = <1 0x0 0x4000000>; 415317bf653SNate Case bank-width = <2>; 416317bf653SNate Case 417317bf653SNate Case partition@0 { 418317bf653SNate Case label = "Filesystem"; 419317bf653SNate Case reg = <0x00000000 0x3f80000>; 420317bf653SNate Case }; 421317bf653SNate Case partition@3f80000 { 422317bf653SNate Case label = "Alternate boot firmware"; 423317bf653SNate Case reg = <0x03f80000 0x80000>; 424317bf653SNate Case }; 425317bf653SNate Case }; 426317bf653SNate Case 427317bf653SNate Case nand@2,0 { 428317bf653SNate Case #address-cells = <1>; 429317bf653SNate Case #size-cells = <1>; 430317bf653SNate Case compatible = "xes,address-ctl-nand"; 431317bf653SNate Case reg = <2 0x0 0x10000>; 432317bf653SNate Case cle-line = <0x8>; /* CLE tied to A3 */ 433317bf653SNate Case ale-line = <0x10>; /* ALE tied to A4 */ 434317bf653SNate Case 435317bf653SNate Case /* U-Boot should fix this up */ 436317bf653SNate Case partition@0 { 437317bf653SNate Case label = "NAND Filesystem"; 438317bf653SNate Case reg = <0 0x40000000>; 439317bf653SNate Case }; 440317bf653SNate Case }; 441317bf653SNate Case }; 442317bf653SNate Case 443317bf653SNate Case /* PMC interface */ 444317bf653SNate Case pci0: pci@ef008000 { 445317bf653SNate Case #interrupt-cells = <1>; 446317bf653SNate Case #size-cells = <2>; 447317bf653SNate Case #address-cells = <3>; 448317bf653SNate Case compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 449317bf653SNate Case device_type = "pci"; 450317bf653SNate Case reg = <0xef008000 0x1000>; 451317bf653SNate Case clock-frequency = <33333333>; 452317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 453317bf653SNate Case interrupt-map = < 454317bf653SNate Case /* IDSEL */ 455317bf653SNate Case 0xe000 0 0 1 &mpic 2 1 456317bf653SNate Case 0xe000 0 0 2 &mpic 3 1>; 457317bf653SNate Case 458317bf653SNate Case interrupt-parent = <&mpic>; 459317bf653SNate Case interrupts = <24 2>; 460317bf653SNate Case bus-range = <0 0>; 461317bf653SNate Case ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000 462317bf653SNate Case 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>; 463317bf653SNate Case }; 464317bf653SNate Case 465317bf653SNate Case /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */ 466317bf653SNate Case}; 467