1317bf653SNate Case/* 2317bf653SNate Case * Copyright (C) 2008 Extreme Engineering Solutions, Inc. 3317bf653SNate Case * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. 4317bf653SNate Case * 5317bf653SNate Case * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E 6317bf653SNate Case * 7317bf653SNate Case * This is free software; you can redistribute it and/or modify 8317bf653SNate Case * it under the terms of the GNU General Public License version 2 as 9317bf653SNate Case * published by the Free Software Foundation. 10317bf653SNate Case */ 11317bf653SNate Case 12317bf653SNate Case/dts-v1/; 13317bf653SNate Case/ { 14317bf653SNate Case model = "xes,xcalibur1501"; 15317bf653SNate Case compatible = "xes,xcalibur1501", "xes,MPC8572"; 16317bf653SNate Case #address-cells = <2>; 17317bf653SNate Case #size-cells = <2>; 18317bf653SNate Case 19317bf653SNate Case aliases { 20317bf653SNate Case ethernet0 = &enet0; 21317bf653SNate Case ethernet1 = &enet1; 22317bf653SNate Case ethernet2 = &enet2; 23317bf653SNate Case ethernet3 = &enet3; 24317bf653SNate Case serial0 = &serial0; 25317bf653SNate Case serial1 = &serial1; 26317bf653SNate Case pci2 = &pci2; 27317bf653SNate Case }; 28317bf653SNate Case 29317bf653SNate Case cpus { 30317bf653SNate Case #address-cells = <1>; 31317bf653SNate Case #size-cells = <0>; 32317bf653SNate Case 33317bf653SNate Case PowerPC,8572@0 { 34317bf653SNate Case device_type = "cpu"; 35317bf653SNate Case reg = <0x0>; 36317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 37317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 38317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 39317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 40317bf653SNate Case timebase-frequency = <0>; 41317bf653SNate Case bus-frequency = <0>; 42317bf653SNate Case clock-frequency = <0>; 43317bf653SNate Case next-level-cache = <&L2>; 44317bf653SNate Case }; 45317bf653SNate Case 46317bf653SNate Case PowerPC,8572@1 { 47317bf653SNate Case device_type = "cpu"; 48317bf653SNate Case reg = <0x1>; 49317bf653SNate Case d-cache-line-size = <32>; // 32 bytes 50317bf653SNate Case i-cache-line-size = <32>; // 32 bytes 51317bf653SNate Case d-cache-size = <0x8000>; // L1, 32K 52317bf653SNate Case i-cache-size = <0x8000>; // L1, 32K 53317bf653SNate Case timebase-frequency = <0>; 54317bf653SNate Case bus-frequency = <0>; 55317bf653SNate Case clock-frequency = <0>; 56317bf653SNate Case next-level-cache = <&L2>; 57317bf653SNate Case }; 58317bf653SNate Case }; 59317bf653SNate Case 60317bf653SNate Case memory { 61317bf653SNate Case device_type = "memory"; 62317bf653SNate Case reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot 63317bf653SNate Case }; 64317bf653SNate Case 65317bf653SNate Case localbus@ef005000 { 66317bf653SNate Case #address-cells = <2>; 67317bf653SNate Case #size-cells = <1>; 68317bf653SNate Case compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 69317bf653SNate Case reg = <0 0xef005000 0 0x1000>; 70317bf653SNate Case interrupts = <19 2>; 71317bf653SNate Case interrupt-parent = <&mpic>; 72317bf653SNate Case /* Local bus region mappings */ 73317bf653SNate Case ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */ 74317bf653SNate Case 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */ 75317bf653SNate Case 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ 76317bf653SNate Case 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */ 77317bf653SNate Case 4 0 0 0xe9000000 0x100000>; /* CS4: USB */ 78317bf653SNate Case 79317bf653SNate Case nor-boot@0,0 { 80317bf653SNate Case compatible = "amd,s29gl01gp", "cfi-flash"; 81317bf653SNate Case bank-width = <2>; 82317bf653SNate Case reg = <0 0 0x8000000>; /* 128MB */ 83317bf653SNate Case #address-cells = <1>; 84317bf653SNate Case #size-cells = <1>; 85317bf653SNate Case partition@0 { 86317bf653SNate Case label = "Primary user space"; 87317bf653SNate Case reg = <0x00000000 0x6f00000>; /* 111 MB */ 88317bf653SNate Case }; 89317bf653SNate Case partition@6f00000 { 90317bf653SNate Case label = "Primary kernel"; 91317bf653SNate Case reg = <0x6f00000 0x1000000>; /* 16 MB */ 92317bf653SNate Case }; 93317bf653SNate Case partition@7f00000 { 94317bf653SNate Case label = "Primary DTB"; 95317bf653SNate Case reg = <0x7f00000 0x40000>; /* 256 KB */ 96317bf653SNate Case }; 97317bf653SNate Case partition@7f40000 { 98317bf653SNate Case label = "Primary U-Boot environment"; 99317bf653SNate Case reg = <0x7f40000 0x40000>; /* 256 KB */ 100317bf653SNate Case }; 101317bf653SNate Case partition@7f80000 { 102317bf653SNate Case label = "Primary U-Boot"; 103317bf653SNate Case reg = <0x7f80000 0x80000>; /* 512 KB */ 104317bf653SNate Case read-only; 105317bf653SNate Case }; 106317bf653SNate Case }; 107317bf653SNate Case 108317bf653SNate Case nor-alternate@1,0 { 109317bf653SNate Case compatible = "amd,s29gl01gp", "cfi-flash"; 110317bf653SNate Case bank-width = <2>; 111317bf653SNate Case //reg = <0xf0000000 0x08000000>; /* 128MB */ 112317bf653SNate Case reg = <1 0 0x8000000>; /* 128MB */ 113317bf653SNate Case #address-cells = <1>; 114317bf653SNate Case #size-cells = <1>; 115317bf653SNate Case partition@0 { 116317bf653SNate Case label = "Secondary user space"; 117317bf653SNate Case reg = <0x00000000 0x6f00000>; /* 111 MB */ 118317bf653SNate Case }; 119317bf653SNate Case partition@6f00000 { 120317bf653SNate Case label = "Secondary kernel"; 121317bf653SNate Case reg = <0x6f00000 0x1000000>; /* 16 MB */ 122317bf653SNate Case }; 123317bf653SNate Case partition@7f00000 { 124317bf653SNate Case label = "Secondary DTB"; 125317bf653SNate Case reg = <0x7f00000 0x40000>; /* 256 KB */ 126317bf653SNate Case }; 127317bf653SNate Case partition@7f40000 { 128317bf653SNate Case label = "Secondary U-Boot environment"; 129317bf653SNate Case reg = <0x7f40000 0x40000>; /* 256 KB */ 130317bf653SNate Case }; 131317bf653SNate Case partition@7f80000 { 132317bf653SNate Case label = "Secondary U-Boot"; 133317bf653SNate Case reg = <0x7f80000 0x80000>; /* 512 KB */ 134317bf653SNate Case read-only; 135317bf653SNate Case }; 136317bf653SNate Case }; 137317bf653SNate Case 138317bf653SNate Case nand@2,0 { 139317bf653SNate Case #address-cells = <1>; 140317bf653SNate Case #size-cells = <1>; 141317bf653SNate Case /* 142317bf653SNate Case * Actual part could be ST Micro NAND08GW3B2A (1 GB), 143317bf653SNate Case * Micron MT29F8G08DAA (2x 512 MB), or Micron 144317bf653SNate Case * MT29F16G08FAA (2x 1 GB), depending on the build 145317bf653SNate Case * configuration 146317bf653SNate Case */ 147317bf653SNate Case compatible = "fsl,mpc8572-fcm-nand", 148317bf653SNate Case "fsl,elbc-fcm-nand"; 149317bf653SNate Case reg = <2 0 0x40000>; 150317bf653SNate Case /* U-Boot should fix this up if chip size > 1 GB */ 151317bf653SNate Case partition@0 { 152317bf653SNate Case label = "NAND Filesystem"; 153317bf653SNate Case reg = <0 0x40000000>; 154317bf653SNate Case }; 155317bf653SNate Case }; 156317bf653SNate Case 157317bf653SNate Case usb@4,0 { 158317bf653SNate Case compatible = "nxp,usb-isp1761"; 159317bf653SNate Case reg = <4 0 0x100000>; 160317bf653SNate Case bus-width = <32>; 161317bf653SNate Case interrupt-parent = <&mpic>; 162317bf653SNate Case interrupts = <10 1>; 163317bf653SNate Case }; 164317bf653SNate Case }; 165317bf653SNate Case 166317bf653SNate Case soc8572@ef000000 { 167317bf653SNate Case #address-cells = <1>; 168317bf653SNate Case #size-cells = <1>; 169317bf653SNate Case device_type = "soc"; 170317bf653SNate Case compatible = "fsl,mpc8572-immr", "simple-bus"; 171317bf653SNate Case ranges = <0x0 0 0xef000000 0x100000>; 172317bf653SNate Case bus-frequency = <0>; // Filled out by uboot. 173317bf653SNate Case 174317bf653SNate Case ecm-law@0 { 175317bf653SNate Case compatible = "fsl,ecm-law"; 176317bf653SNate Case reg = <0x0 0x1000>; 177317bf653SNate Case fsl,num-laws = <12>; 178317bf653SNate Case }; 179317bf653SNate Case 180317bf653SNate Case ecm@1000 { 181317bf653SNate Case compatible = "fsl,mpc8572-ecm", "fsl,ecm"; 182317bf653SNate Case reg = <0x1000 0x1000>; 183317bf653SNate Case interrupts = <17 2>; 184317bf653SNate Case interrupt-parent = <&mpic>; 185317bf653SNate Case }; 186317bf653SNate Case 187317bf653SNate Case memory-controller@2000 { 188317bf653SNate Case compatible = "fsl,mpc8572-memory-controller"; 189317bf653SNate Case reg = <0x2000 0x1000>; 190317bf653SNate Case interrupt-parent = <&mpic>; 191317bf653SNate Case interrupts = <18 2>; 192317bf653SNate Case }; 193317bf653SNate Case 194317bf653SNate Case memory-controller@6000 { 195317bf653SNate Case compatible = "fsl,mpc8572-memory-controller"; 196317bf653SNate Case reg = <0x6000 0x1000>; 197317bf653SNate Case interrupt-parent = <&mpic>; 198317bf653SNate Case interrupts = <18 2>; 199317bf653SNate Case }; 200317bf653SNate Case 201317bf653SNate Case L2: l2-cache-controller@20000 { 202317bf653SNate Case compatible = "fsl,mpc8572-l2-cache-controller"; 203317bf653SNate Case reg = <0x20000 0x1000>; 204317bf653SNate Case cache-line-size = <32>; // 32 bytes 205317bf653SNate Case cache-size = <0x100000>; // L2, 1M 206317bf653SNate Case interrupt-parent = <&mpic>; 207317bf653SNate Case interrupts = <16 2>; 208317bf653SNate Case }; 209317bf653SNate Case 210317bf653SNate Case i2c@3000 { 211317bf653SNate Case #address-cells = <1>; 212317bf653SNate Case #size-cells = <0>; 213317bf653SNate Case cell-index = <0>; 214317bf653SNate Case compatible = "fsl-i2c"; 215317bf653SNate Case reg = <0x3000 0x100>; 216317bf653SNate Case interrupts = <43 2>; 217317bf653SNate Case interrupt-parent = <&mpic>; 218317bf653SNate Case dfsrr; 219317bf653SNate Case 220317bf653SNate Case temp-sensor@48 { 221317bf653SNate Case compatible = "dallas,ds1631", "dallas,ds1621"; 222317bf653SNate Case reg = <0x48>; 223317bf653SNate Case }; 224317bf653SNate Case 225317bf653SNate Case temp-sensor@4c { 226317bf653SNate Case compatible = "adi,adt7461"; 227317bf653SNate Case reg = <0x4c>; 228317bf653SNate Case }; 229317bf653SNate Case 230317bf653SNate Case cpu-supervisor@51 { 231317bf653SNate Case compatible = "dallas,ds4510"; 232317bf653SNate Case reg = <0x51>; 233317bf653SNate Case }; 234317bf653SNate Case 235317bf653SNate Case eeprom@54 { 236317bf653SNate Case compatible = "atmel,at24c128b"; 237317bf653SNate Case reg = <0x54>; 238317bf653SNate Case }; 239317bf653SNate Case 240317bf653SNate Case rtc@68 { 241317bf653SNate Case compatible = "stm,m41t00", 242317bf653SNate Case "dallas,ds1338"; 243317bf653SNate Case reg = <0x68>; 244317bf653SNate Case }; 245317bf653SNate Case 246317bf653SNate Case pcie-switch@6a { 247317bf653SNate Case compatible = "plx,pex8648"; 248317bf653SNate Case reg = <0x6a>; 249317bf653SNate Case }; 250317bf653SNate Case 251317bf653SNate Case /* On-board signals for VID, flash, serial */ 252317bf653SNate Case gpio1: gpio@18 { 253317bf653SNate Case compatible = "nxp,pca9557"; 254317bf653SNate Case reg = <0x18>; 255317bf653SNate Case #gpio-cells = <2>; 256317bf653SNate Case gpio-controller; 257317bf653SNate Case polarity = <0x00>; 258317bf653SNate Case }; 259317bf653SNate Case 260317bf653SNate Case /* PMC0/XMC0 signals */ 261317bf653SNate Case gpio2: gpio@1c { 262317bf653SNate Case compatible = "nxp,pca9557"; 263317bf653SNate Case reg = <0x1c>; 264317bf653SNate Case #gpio-cells = <2>; 265317bf653SNate Case gpio-controller; 266317bf653SNate Case polarity = <0x00>; 267317bf653SNate Case }; 268317bf653SNate Case 269317bf653SNate Case /* PMC1/XMC1 signals */ 270317bf653SNate Case gpio3: gpio@1d { 271317bf653SNate Case compatible = "nxp,pca9557"; 272317bf653SNate Case reg = <0x1d>; 273317bf653SNate Case #gpio-cells = <2>; 274317bf653SNate Case gpio-controller; 275317bf653SNate Case polarity = <0x00>; 276317bf653SNate Case }; 277317bf653SNate Case 278317bf653SNate Case /* CompactPCI signals (sysen, GA[4:0]) */ 279317bf653SNate Case gpio4: gpio@1e { 280317bf653SNate Case compatible = "nxp,pca9557"; 281317bf653SNate Case reg = <0x1e>; 282317bf653SNate Case #gpio-cells = <2>; 283317bf653SNate Case gpio-controller; 284317bf653SNate Case polarity = <0x00>; 285317bf653SNate Case }; 286317bf653SNate Case 287317bf653SNate Case /* CompactPCI J5 GPIO and FAL/DEG/PRST */ 288317bf653SNate Case gpio5: gpio@1f { 289317bf653SNate Case compatible = "nxp,pca9557"; 290317bf653SNate Case reg = <0x1f>; 291317bf653SNate Case #gpio-cells = <2>; 292317bf653SNate Case gpio-controller; 293317bf653SNate Case polarity = <0x00>; 294317bf653SNate Case }; 295317bf653SNate Case }; 296317bf653SNate Case 297317bf653SNate Case i2c@3100 { 298317bf653SNate Case #address-cells = <1>; 299317bf653SNate Case #size-cells = <0>; 300317bf653SNate Case cell-index = <1>; 301317bf653SNate Case compatible = "fsl-i2c"; 302317bf653SNate Case reg = <0x3100 0x100>; 303317bf653SNate Case interrupts = <43 2>; 304317bf653SNate Case interrupt-parent = <&mpic>; 305317bf653SNate Case dfsrr; 306317bf653SNate Case }; 307317bf653SNate Case 308317bf653SNate Case dma@c300 { 309317bf653SNate Case #address-cells = <1>; 310317bf653SNate Case #size-cells = <1>; 311317bf653SNate Case compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 312317bf653SNate Case reg = <0xc300 0x4>; 313317bf653SNate Case ranges = <0x0 0xc100 0x200>; 314317bf653SNate Case cell-index = <1>; 315317bf653SNate Case dma-channel@0 { 316317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 317317bf653SNate Case "fsl,eloplus-dma-channel"; 318317bf653SNate Case reg = <0x0 0x80>; 319317bf653SNate Case cell-index = <0>; 320317bf653SNate Case interrupt-parent = <&mpic>; 321317bf653SNate Case interrupts = <76 2>; 322317bf653SNate Case }; 323317bf653SNate Case dma-channel@80 { 324317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 325317bf653SNate Case "fsl,eloplus-dma-channel"; 326317bf653SNate Case reg = <0x80 0x80>; 327317bf653SNate Case cell-index = <1>; 328317bf653SNate Case interrupt-parent = <&mpic>; 329317bf653SNate Case interrupts = <77 2>; 330317bf653SNate Case }; 331317bf653SNate Case dma-channel@100 { 332317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 333317bf653SNate Case "fsl,eloplus-dma-channel"; 334317bf653SNate Case reg = <0x100 0x80>; 335317bf653SNate Case cell-index = <2>; 336317bf653SNate Case interrupt-parent = <&mpic>; 337317bf653SNate Case interrupts = <78 2>; 338317bf653SNate Case }; 339317bf653SNate Case dma-channel@180 { 340317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 341317bf653SNate Case "fsl,eloplus-dma-channel"; 342317bf653SNate Case reg = <0x180 0x80>; 343317bf653SNate Case cell-index = <3>; 344317bf653SNate Case interrupt-parent = <&mpic>; 345317bf653SNate Case interrupts = <79 2>; 346317bf653SNate Case }; 347317bf653SNate Case }; 348317bf653SNate Case 349317bf653SNate Case dma@21300 { 350317bf653SNate Case #address-cells = <1>; 351317bf653SNate Case #size-cells = <1>; 352317bf653SNate Case compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 353317bf653SNate Case reg = <0x21300 0x4>; 354317bf653SNate Case ranges = <0x0 0x21100 0x200>; 355317bf653SNate Case cell-index = <0>; 356317bf653SNate Case dma-channel@0 { 357317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 358317bf653SNate Case "fsl,eloplus-dma-channel"; 359317bf653SNate Case reg = <0x0 0x80>; 360317bf653SNate Case cell-index = <0>; 361317bf653SNate Case interrupt-parent = <&mpic>; 362317bf653SNate Case interrupts = <20 2>; 363317bf653SNate Case }; 364317bf653SNate Case dma-channel@80 { 365317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 366317bf653SNate Case "fsl,eloplus-dma-channel"; 367317bf653SNate Case reg = <0x80 0x80>; 368317bf653SNate Case cell-index = <1>; 369317bf653SNate Case interrupt-parent = <&mpic>; 370317bf653SNate Case interrupts = <21 2>; 371317bf653SNate Case }; 372317bf653SNate Case dma-channel@100 { 373317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 374317bf653SNate Case "fsl,eloplus-dma-channel"; 375317bf653SNate Case reg = <0x100 0x80>; 376317bf653SNate Case cell-index = <2>; 377317bf653SNate Case interrupt-parent = <&mpic>; 378317bf653SNate Case interrupts = <22 2>; 379317bf653SNate Case }; 380317bf653SNate Case dma-channel@180 { 381317bf653SNate Case compatible = "fsl,mpc8572-dma-channel", 382317bf653SNate Case "fsl,eloplus-dma-channel"; 383317bf653SNate Case reg = <0x180 0x80>; 384317bf653SNate Case cell-index = <3>; 385317bf653SNate Case interrupt-parent = <&mpic>; 386317bf653SNate Case interrupts = <23 2>; 387317bf653SNate Case }; 388317bf653SNate Case }; 389317bf653SNate Case 390317bf653SNate Case /* eTSEC 1 front panel 0 */ 391317bf653SNate Case enet0: ethernet@24000 { 392317bf653SNate Case #address-cells = <1>; 393317bf653SNate Case #size-cells = <1>; 394317bf653SNate Case cell-index = <0>; 395317bf653SNate Case device_type = "network"; 396317bf653SNate Case model = "eTSEC"; 397317bf653SNate Case compatible = "gianfar"; 398317bf653SNate Case reg = <0x24000 0x1000>; 399317bf653SNate Case ranges = <0x0 0x24000 0x1000>; 400317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 401317bf653SNate Case interrupts = <29 2 30 2 34 2>; 402317bf653SNate Case interrupt-parent = <&mpic>; 403317bf653SNate Case tbi-handle = <&tbi0>; 404317bf653SNate Case phy-handle = <&phy0>; 405317bf653SNate Case phy-connection-type = "sgmii"; 406317bf653SNate Case 407317bf653SNate Case mdio@520 { 408317bf653SNate Case #address-cells = <1>; 409317bf653SNate Case #size-cells = <0>; 410317bf653SNate Case compatible = "fsl,gianfar-mdio"; 411317bf653SNate Case reg = <0x520 0x20>; 412317bf653SNate Case 413317bf653SNate Case phy0: ethernet-phy@1 { 414317bf653SNate Case interrupt-parent = <&mpic>; 415317bf653SNate Case interrupts = <4 1>; 416317bf653SNate Case reg = <0x1>; 417317bf653SNate Case }; 418317bf653SNate Case phy1: ethernet-phy@2 { 419317bf653SNate Case interrupt-parent = <&mpic>; 420317bf653SNate Case interrupts = <4 1>; 421317bf653SNate Case reg = <0x2>; 422317bf653SNate Case }; 423317bf653SNate Case phy2: ethernet-phy@3 { 424317bf653SNate Case interrupt-parent = <&mpic>; 425317bf653SNate Case interrupts = <5 1>; 426317bf653SNate Case reg = <0x3>; 427317bf653SNate Case }; 428317bf653SNate Case phy3: ethernet-phy@4 { 429317bf653SNate Case interrupt-parent = <&mpic>; 430317bf653SNate Case interrupts = <5 1>; 431317bf653SNate Case reg = <0x4>; 432317bf653SNate Case }; 433317bf653SNate Case tbi0: tbi-phy@11 { 434317bf653SNate Case reg = <0x11>; 435317bf653SNate Case device_type = "tbi-phy"; 436317bf653SNate Case }; 437317bf653SNate Case }; 438317bf653SNate Case }; 439317bf653SNate Case 440317bf653SNate Case /* eTSEC 2 front panel 1 */ 441317bf653SNate Case enet1: ethernet@25000 { 442317bf653SNate Case #address-cells = <1>; 443317bf653SNate Case #size-cells = <1>; 444317bf653SNate Case cell-index = <1>; 445317bf653SNate Case device_type = "network"; 446317bf653SNate Case model = "eTSEC"; 447317bf653SNate Case compatible = "gianfar"; 448317bf653SNate Case reg = <0x25000 0x1000>; 449317bf653SNate Case ranges = <0x0 0x25000 0x1000>; 450317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 451317bf653SNate Case interrupts = <35 2 36 2 40 2>; 452317bf653SNate Case interrupt-parent = <&mpic>; 453317bf653SNate Case tbi-handle = <&tbi1>; 454317bf653SNate Case phy-handle = <&phy1>; 455317bf653SNate Case phy-connection-type = "sgmii"; 456317bf653SNate Case 457317bf653SNate Case mdio@520 { 458317bf653SNate Case #address-cells = <1>; 459317bf653SNate Case #size-cells = <0>; 460317bf653SNate Case compatible = "fsl,gianfar-tbi"; 461317bf653SNate Case reg = <0x520 0x20>; 462317bf653SNate Case 463317bf653SNate Case tbi1: tbi-phy@11 { 464317bf653SNate Case reg = <0x11>; 465317bf653SNate Case device_type = "tbi-phy"; 466317bf653SNate Case }; 467317bf653SNate Case }; 468317bf653SNate Case }; 469317bf653SNate Case 470317bf653SNate Case /* eTSEC 3 PICMG2.16 backplane port 0 */ 471317bf653SNate Case enet2: ethernet@26000 { 472317bf653SNate Case #address-cells = <1>; 473317bf653SNate Case #size-cells = <1>; 474317bf653SNate Case cell-index = <2>; 475317bf653SNate Case device_type = "network"; 476317bf653SNate Case model = "eTSEC"; 477317bf653SNate Case compatible = "gianfar"; 478317bf653SNate Case reg = <0x26000 0x1000>; 479317bf653SNate Case ranges = <0x0 0x26000 0x1000>; 480317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 481317bf653SNate Case interrupts = <31 2 32 2 33 2>; 482317bf653SNate Case interrupt-parent = <&mpic>; 483317bf653SNate Case tbi-handle = <&tbi2>; 484317bf653SNate Case phy-handle = <&phy2>; 485317bf653SNate Case phy-connection-type = "sgmii"; 486317bf653SNate Case 487317bf653SNate Case mdio@520 { 488317bf653SNate Case #address-cells = <1>; 489317bf653SNate Case #size-cells = <0>; 490317bf653SNate Case compatible = "fsl,gianfar-tbi"; 491317bf653SNate Case reg = <0x520 0x20>; 492317bf653SNate Case 493317bf653SNate Case tbi2: tbi-phy@11 { 494317bf653SNate Case reg = <0x11>; 495317bf653SNate Case device_type = "tbi-phy"; 496317bf653SNate Case }; 497317bf653SNate Case }; 498317bf653SNate Case }; 499317bf653SNate Case 500317bf653SNate Case /* eTSEC 4 PICMG2.16 backplane port 1 */ 501317bf653SNate Case enet3: ethernet@27000 { 502317bf653SNate Case #address-cells = <1>; 503317bf653SNate Case #size-cells = <1>; 504317bf653SNate Case cell-index = <3>; 505317bf653SNate Case device_type = "network"; 506317bf653SNate Case model = "eTSEC"; 507317bf653SNate Case compatible = "gianfar"; 508317bf653SNate Case reg = <0x27000 0x1000>; 509317bf653SNate Case ranges = <0x0 0x27000 0x1000>; 510317bf653SNate Case local-mac-address = [ 00 00 00 00 00 00 ]; 511317bf653SNate Case interrupts = <37 2 38 2 39 2>; 512317bf653SNate Case interrupt-parent = <&mpic>; 513317bf653SNate Case tbi-handle = <&tbi3>; 514317bf653SNate Case phy-handle = <&phy3>; 515317bf653SNate Case phy-connection-type = "sgmii"; 516317bf653SNate Case 517317bf653SNate Case mdio@520 { 518317bf653SNate Case #address-cells = <1>; 519317bf653SNate Case #size-cells = <0>; 520317bf653SNate Case compatible = "fsl,gianfar-tbi"; 521317bf653SNate Case reg = <0x520 0x20>; 522317bf653SNate Case 523317bf653SNate Case tbi3: tbi-phy@11 { 524317bf653SNate Case reg = <0x11>; 525317bf653SNate Case device_type = "tbi-phy"; 526317bf653SNate Case }; 527317bf653SNate Case }; 528317bf653SNate Case }; 529317bf653SNate Case 530317bf653SNate Case /* UART0 */ 531317bf653SNate Case serial0: serial@4500 { 532317bf653SNate Case cell-index = <0>; 533317bf653SNate Case device_type = "serial"; 534317bf653SNate Case compatible = "ns16550"; 535317bf653SNate Case reg = <0x4500 0x100>; 536317bf653SNate Case clock-frequency = <0>; 537317bf653SNate Case interrupts = <42 2>; 538317bf653SNate Case interrupt-parent = <&mpic>; 539317bf653SNate Case }; 540317bf653SNate Case 541317bf653SNate Case /* UART1 */ 542317bf653SNate Case serial1: serial@4600 { 543317bf653SNate Case cell-index = <1>; 544317bf653SNate Case device_type = "serial"; 545317bf653SNate Case compatible = "ns16550"; 546317bf653SNate Case reg = <0x4600 0x100>; 547317bf653SNate Case clock-frequency = <0>; 548317bf653SNate Case interrupts = <42 2>; 549317bf653SNate Case interrupt-parent = <&mpic>; 550317bf653SNate Case }; 551317bf653SNate Case 552317bf653SNate Case global-utilities@e0000 { //global utilities block 553317bf653SNate Case compatible = "fsl,mpc8572-guts"; 554317bf653SNate Case reg = <0xe0000 0x1000>; 555317bf653SNate Case fsl,has-rstcr; 556317bf653SNate Case }; 557317bf653SNate Case 558317bf653SNate Case msi@41600 { 559317bf653SNate Case compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 560317bf653SNate Case reg = <0x41600 0x80>; 561317bf653SNate Case msi-available-ranges = <0 0x100>; 562317bf653SNate Case interrupts = < 563317bf653SNate Case 0xe0 0 564317bf653SNate Case 0xe1 0 565317bf653SNate Case 0xe2 0 566317bf653SNate Case 0xe3 0 567317bf653SNate Case 0xe4 0 568317bf653SNate Case 0xe5 0 569317bf653SNate Case 0xe6 0 570317bf653SNate Case 0xe7 0>; 571317bf653SNate Case interrupt-parent = <&mpic>; 572317bf653SNate Case }; 573317bf653SNate Case 574317bf653SNate Case crypto@30000 { 575317bf653SNate Case compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 576317bf653SNate Case "fsl,sec2.1", "fsl,sec2.0"; 577317bf653SNate Case reg = <0x30000 0x10000>; 578317bf653SNate Case interrupts = <45 2 58 2>; 579317bf653SNate Case interrupt-parent = <&mpic>; 580317bf653SNate Case fsl,num-channels = <4>; 581317bf653SNate Case fsl,channel-fifo-len = <24>; 582317bf653SNate Case fsl,exec-units-mask = <0x9fe>; 583317bf653SNate Case fsl,descriptor-types-mask = <0x3ab0ebf>; 584317bf653SNate Case }; 585317bf653SNate Case 586317bf653SNate Case mpic: pic@40000 { 587317bf653SNate Case interrupt-controller; 588317bf653SNate Case #address-cells = <0>; 589317bf653SNate Case #interrupt-cells = <2>; 590317bf653SNate Case reg = <0x40000 0x40000>; 591317bf653SNate Case compatible = "chrp,open-pic"; 592317bf653SNate Case device_type = "open-pic"; 593317bf653SNate Case }; 594317bf653SNate Case 595317bf653SNate Case gpio0: gpio@f000 { 596317bf653SNate Case compatible = "fsl,mpc8572-gpio"; 597317bf653SNate Case reg = <0xf000 0x1000>; 598317bf653SNate Case interrupts = <47 2>; 599317bf653SNate Case interrupt-parent = <&mpic>; 600317bf653SNate Case #gpio-cells = <2>; 601317bf653SNate Case gpio-controller; 602317bf653SNate Case }; 603317bf653SNate Case 604317bf653SNate Case gpio-leds { 605317bf653SNate Case compatible = "gpio-leds"; 606317bf653SNate Case 607317bf653SNate Case heartbeat { 608317bf653SNate Case label = "Heartbeat"; 609317bf653SNate Case gpios = <&gpio0 4 1>; 610317bf653SNate Case linux,default-trigger = "heartbeat"; 611317bf653SNate Case }; 612317bf653SNate Case 613317bf653SNate Case yellow { 614317bf653SNate Case label = "Yellow"; 615317bf653SNate Case gpios = <&gpio0 5 1>; 616317bf653SNate Case }; 617317bf653SNate Case 618317bf653SNate Case red { 619317bf653SNate Case label = "Red"; 620317bf653SNate Case gpios = <&gpio0 6 1>; 621317bf653SNate Case }; 622317bf653SNate Case 623317bf653SNate Case green { 624317bf653SNate Case label = "Green"; 625317bf653SNate Case gpios = <&gpio0 7 1>; 626317bf653SNate Case }; 627317bf653SNate Case }; 628317bf653SNate Case 629317bf653SNate Case /* PME (pattern-matcher) */ 630317bf653SNate Case pme@10000 { 631317bf653SNate Case compatible = "fsl,mpc8572-pme", "pme8572"; 632317bf653SNate Case reg = <0x10000 0x5000>; 633317bf653SNate Case interrupts = <57 2 64 2 65 2 66 2 67 2>; 634317bf653SNate Case interrupt-parent = <&mpic>; 635317bf653SNate Case }; 636317bf653SNate Case 637317bf653SNate Case tlu@2f000 { 638317bf653SNate Case compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 639317bf653SNate Case reg = <0x2f000 0x1000>; 640317bf653SNate Case interupts = <61 2 >; 641317bf653SNate Case interrupt-parent = <&mpic>; 642317bf653SNate Case }; 643317bf653SNate Case 644317bf653SNate Case tlu@15000 { 645317bf653SNate Case compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 646317bf653SNate Case reg = <0x15000 0x1000>; 647317bf653SNate Case interupts = <75 2>; 648317bf653SNate Case interrupt-parent = <&mpic>; 649317bf653SNate Case }; 650317bf653SNate Case }; 651317bf653SNate Case 652317bf653SNate Case /* 653317bf653SNate Case * PCI Express controller 3 @ ef008000 is not used. 654317bf653SNate Case * This would have been pci0 on other mpc85xx platforms. 655317bf653SNate Case * 656317bf653SNate Case * PCI Express controller 2 @ ef009000 is not used. 657317bf653SNate Case * This would have been pci1 on other mpc85xx platforms. 658317bf653SNate Case */ 659317bf653SNate Case 660317bf653SNate Case /* PCI Express controller 1, wired to PEX8648 PCIe switch */ 661317bf653SNate Case pci2: pcie@ef00a000 { 662317bf653SNate Case compatible = "fsl,mpc8548-pcie"; 663317bf653SNate Case device_type = "pci"; 664317bf653SNate Case #interrupt-cells = <1>; 665317bf653SNate Case #size-cells = <2>; 666317bf653SNate Case #address-cells = <3>; 667317bf653SNate Case reg = <0 0xef00a000 0 0x1000>; 668317bf653SNate Case bus-range = <0 255>; 669317bf653SNate Case ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 670317bf653SNate Case 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; 671317bf653SNate Case clock-frequency = <33333333>; 672317bf653SNate Case interrupt-parent = <&mpic>; 673317bf653SNate Case interrupts = <26 2>; 674317bf653SNate Case interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 675317bf653SNate Case interrupt-map = < 676317bf653SNate Case /* IDSEL 0x0 */ 677317bf653SNate Case 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 678317bf653SNate Case 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 679317bf653SNate Case 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 680317bf653SNate Case 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 681317bf653SNate Case >; 682317bf653SNate Case pcie@0 { 683317bf653SNate Case reg = <0x0 0x0 0x0 0x0 0x0>; 684317bf653SNate Case #size-cells = <2>; 685317bf653SNate Case #address-cells = <3>; 686317bf653SNate Case device_type = "pci"; 687317bf653SNate Case ranges = <0x2000000 0x0 0x80000000 688317bf653SNate Case 0x2000000 0x0 0x80000000 689317bf653SNate Case 0x0 0x40000000 690317bf653SNate Case 691317bf653SNate Case 0x1000000 0x0 0x0 692317bf653SNate Case 0x1000000 0x0 0x0 693317bf653SNate Case 0x0 0x100000>; 694317bf653SNate Case }; 695317bf653SNate Case }; 696317bf653SNate Case}; 697