1/*
2 * TQM 8560 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16	model = "tqc,tqm8560";
17	compatible = "tqc,tqm8560";
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	aliases {
22		ethernet0 = &enet0;
23		ethernet1 = &enet1;
24		ethernet2 = &enet2;
25		serial0 = &serial0;
26		serial1 = &serial1;
27		pci0 = &pci0;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		PowerPC,8560@0 {
35			device_type = "cpu";
36			reg = <0>;
37			d-cache-line-size = <32>;
38			i-cache-line-size = <32>;
39			d-cache-size = <32768>;
40			i-cache-size = <32768>;
41			timebase-frequency = <0>;
42			bus-frequency = <0>;
43			clock-frequency = <0>;
44			next-level-cache = <&L2>;
45		};
46	};
47
48	memory {
49		device_type = "memory";
50		reg = <0x00000000 0x10000000>;
51	};
52
53	soc@e0000000 {
54		#address-cells = <1>;
55		#size-cells = <1>;
56		device_type = "soc";
57		ranges = <0x0 0xe0000000 0x100000>;
58		bus-frequency = <0>;
59		compatible = "fsl,mpc8560-immr", "simple-bus";
60
61		ecm-law@0 {
62			compatible = "fsl,ecm-law";
63			reg = <0x0 0x1000>;
64			fsl,num-laws = <8>;
65		};
66
67		ecm@1000 {
68			compatible = "fsl,mpc8560-ecm", "fsl,ecm";
69			reg = <0x1000 0x1000>;
70			interrupts = <17 2>;
71			interrupt-parent = <&mpic>;
72		};
73
74		memory-controller@2000 {
75			compatible = "fsl,mpc8540-memory-controller";
76			reg = <0x2000 0x1000>;
77			interrupt-parent = <&mpic>;
78			interrupts = <18 2>;
79		};
80
81		L2: l2-cache-controller@20000 {
82			compatible = "fsl,mpc8540-l2-cache-controller";
83			reg = <0x20000 0x1000>;
84			cache-line-size = <32>;
85			cache-size = <0x40000>;	// L2, 256K
86			interrupt-parent = <&mpic>;
87			interrupts = <16 2>;
88		};
89
90		i2c@3000 {
91			#address-cells = <1>;
92			#size-cells = <0>;
93			cell-index = <0>;
94			compatible = "fsl-i2c";
95			reg = <0x3000 0x100>;
96			interrupts = <43 2>;
97			interrupt-parent = <&mpic>;
98			dfsrr;
99
100			dtt@48 {
101				compatible = "national,lm75";
102				reg = <0x48>;
103			};
104
105			rtc@68 {
106				compatible = "dallas,ds1337";
107				reg = <0x68>;
108			};
109		};
110
111		dma@21300 {
112			#address-cells = <1>;
113			#size-cells = <1>;
114			compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
115			reg = <0x21300 0x4>;
116			ranges = <0x0 0x21100 0x200>;
117			cell-index = <0>;
118			dma-channel@0 {
119				compatible = "fsl,mpc8560-dma-channel",
120						"fsl,eloplus-dma-channel";
121				reg = <0x0 0x80>;
122				cell-index = <0>;
123				interrupt-parent = <&mpic>;
124				interrupts = <20 2>;
125			};
126			dma-channel@80 {
127				compatible = "fsl,mpc8560-dma-channel",
128						"fsl,eloplus-dma-channel";
129				reg = <0x80 0x80>;
130				cell-index = <1>;
131				interrupt-parent = <&mpic>;
132				interrupts = <21 2>;
133			};
134			dma-channel@100 {
135				compatible = "fsl,mpc8560-dma-channel",
136						"fsl,eloplus-dma-channel";
137				reg = <0x100 0x80>;
138				cell-index = <2>;
139				interrupt-parent = <&mpic>;
140				interrupts = <22 2>;
141			};
142			dma-channel@180 {
143				compatible = "fsl,mpc8560-dma-channel",
144						"fsl,eloplus-dma-channel";
145				reg = <0x180 0x80>;
146				cell-index = <3>;
147				interrupt-parent = <&mpic>;
148				interrupts = <23 2>;
149			};
150		};
151
152		enet0: ethernet@24000 {
153			#address-cells = <1>;
154			#size-cells = <1>;
155			cell-index = <0>;
156			device_type = "network";
157			model = "TSEC";
158			compatible = "gianfar";
159			reg = <0x24000 0x1000>;
160			ranges = <0x0 0x24000 0x1000>;
161			local-mac-address = [ 00 00 00 00 00 00 ];
162			interrupts = <29 2 30 2 34 2>;
163			interrupt-parent = <&mpic>;
164			tbi-handle = <&tbi0>;
165			phy-handle = <&phy2>;
166
167			mdio@520 {
168				#address-cells = <1>;
169				#size-cells = <0>;
170				compatible = "fsl,gianfar-mdio";
171				reg = <0x520 0x20>;
172
173				phy1: ethernet-phy@1 {
174					interrupt-parent = <&mpic>;
175					interrupts = <8 1>;
176					reg = <1>;
177					device_type = "ethernet-phy";
178				};
179				phy2: ethernet-phy@2 {
180					interrupt-parent = <&mpic>;
181					interrupts = <8 1>;
182					reg = <2>;
183					device_type = "ethernet-phy";
184				};
185				phy3: ethernet-phy@3 {
186					interrupt-parent = <&mpic>;
187					interrupts = <8 1>;
188					reg = <3>;
189					device_type = "ethernet-phy";
190				};
191				tbi0: tbi-phy@11 {
192					reg = <0x11>;
193					device_type = "tbi-phy";
194				};
195			};
196		};
197
198		enet1: ethernet@25000 {
199			#address-cells = <1>;
200			#size-cells = <1>;
201			cell-index = <1>;
202			device_type = "network";
203			model = "TSEC";
204			compatible = "gianfar";
205			reg = <0x25000 0x1000>;
206			ranges = <0x0 0x25000 0x1000>;
207			local-mac-address = [ 00 00 00 00 00 00 ];
208			interrupts = <35 2 36 2 40 2>;
209			interrupt-parent = <&mpic>;
210			tbi-handle = <&tbi1>;
211			phy-handle = <&phy1>;
212
213			mdio@520 {
214				#address-cells = <1>;
215				#size-cells = <0>;
216				compatible = "fsl,gianfar-tbi";
217				reg = <0x520 0x20>;
218
219				tbi1: tbi-phy@11 {
220					reg = <0x11>;
221					device_type = "tbi-phy";
222				};
223			};
224		};
225
226		mpic: pic@40000 {
227			interrupt-controller;
228			#address-cells = <0>;
229			#interrupt-cells = <2>;
230			reg = <0x40000 0x40000>;
231			device_type = "open-pic";
232			compatible = "chrp,open-pic";
233		};
234
235		cpm@919c0 {
236			#address-cells = <1>;
237			#size-cells = <1>;
238			compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
239			reg = <0x919c0 0x30>;
240			ranges;
241
242			muram@80000 {
243				#address-cells = <1>;
244				#size-cells = <1>;
245				ranges = <0 0x80000 0x10000>;
246
247				data@0 {
248					compatible = "fsl,cpm-muram-data";
249					reg = <0 0x4000 0x9000 0x2000>;
250				};
251			};
252
253			brg@919f0 {
254				compatible = "fsl,mpc8560-brg",
255				             "fsl,cpm2-brg",
256				             "fsl,cpm-brg";
257				reg = <0x919f0 0x10 0x915f0 0x10>;
258				clock-frequency = <0>;
259			};
260
261			cpmpic: pic@90c00 {
262				interrupt-controller;
263				#address-cells = <0>;
264				#interrupt-cells = <2>;
265				interrupts = <46 2>;
266				interrupt-parent = <&mpic>;
267				reg = <0x90c00 0x80>;
268				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
269			};
270
271			serial0: serial@91a00 {
272				device_type = "serial";
273				compatible = "fsl,mpc8560-scc-uart",
274				             "fsl,cpm2-scc-uart";
275				reg = <0x91a00 0x20 0x88000 0x100>;
276				fsl,cpm-brg = <1>;
277				fsl,cpm-command = <0x800000>;
278				current-speed = <115200>;
279				interrupts = <40 8>;
280				interrupt-parent = <&cpmpic>;
281			};
282
283			serial1: serial@91a20 {
284				device_type = "serial";
285				compatible = "fsl,mpc8560-scc-uart",
286				             "fsl,cpm2-scc-uart";
287				reg = <0x91a20 0x20 0x88100 0x100>;
288				fsl,cpm-brg = <2>;
289				fsl,cpm-command = <0x4a00000>;
290				current-speed = <115200>;
291				interrupts = <41 8>;
292				interrupt-parent = <&cpmpic>;
293			};
294
295			enet2: ethernet@91340 {
296				device_type = "network";
297				compatible = "fsl,mpc8560-fcc-enet",
298				             "fsl,cpm2-fcc-enet";
299				reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
300				local-mac-address = [ 00 00 00 00 00 00 ];
301				fsl,cpm-command = <0x1a400300>;
302				interrupts = <34 8>;
303				interrupt-parent = <&cpmpic>;
304				phy-handle = <&phy3>;
305			};
306		};
307	};
308
309	localbus@e0005000 {
310		compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
311			     "simple-bus";
312		#address-cells = <2>;
313		#size-cells = <1>;
314		reg = <0xe0005000 0x100>;	// BRx, ORx, etc.
315		interrupt-parent = <&mpic>;
316		interrupts = <19 2>;
317
318		ranges = <
319			0 0x0 0xfc000000 0x04000000	// NOR FLASH bank 1
320			1 0x0 0xf8000000 0x08000000	// NOR FLASH bank 0
321			2 0x0 0xe3000000 0x00008000	// CAN (2 x i82527)
322		>;
323
324		flash@1,0 {
325			#address-cells = <1>;
326			#size-cells = <1>;
327			compatible = "cfi-flash";
328			reg = <1 0x0 0x8000000>;
329			bank-width = <4>;
330			device-width = <1>;
331
332			partition@0 {
333				label = "kernel";
334				reg = <0x00000000 0x00200000>;
335			};
336			partition@200000 {
337				label = "root";
338				reg = <0x00200000 0x00300000>;
339			};
340			partition@500000 {
341				label = "user";
342				reg = <0x00500000 0x07a00000>;
343			};
344			partition@7f00000 {
345				label = "env1";
346				reg = <0x07f00000 0x00040000>;
347			};
348			partition@7f40000 {
349				label = "env2";
350				reg = <0x07f40000 0x00040000>;
351			};
352			partition@7f80000 {
353				label = "u-boot";
354				reg = <0x07f80000 0x00080000>;
355				read-only;
356			};
357		};
358
359		/* Note: CAN support needs be enabled in U-Boot */
360		can0@2,0 {
361			compatible = "intel,82527"; // Bosch CC770
362			reg = <2 0x0 0x100>;
363			interrupts = <4 1>;
364			interrupt-parent = <&mpic>;
365		};
366
367		can1@2,100 {
368			compatible = "intel,82527"; // Bosch CC770
369			reg = <2 0x100 0x100>;
370			interrupts = <4 1>;
371			interrupt-parent = <&mpic>;
372		};
373	};
374
375	pci0: pci@e0008000 {
376		#interrupt-cells = <1>;
377		#size-cells = <2>;
378		#address-cells = <3>;
379		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
380		device_type = "pci";
381		reg = <0xe0008000 0x1000>;
382		clock-frequency = <66666666>;
383		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
384		interrupt-map = <
385				/* IDSEL 28 */
386				 0xe000 0 0 1 &mpic 2 1
387				 0xe000 0 0 2 &mpic 3 1
388				 0xe000 0 0 3 &mpic 6 1
389				 0xe000 0 0 4 &mpic 5 1
390
391				/* IDSEL 11 */
392				 0x5800 0 0 1 &mpic 6 1
393				 0x5800 0 0 2 &mpic 5 1
394				 >;
395
396		interrupt-parent = <&mpic>;
397		interrupts = <24 2>;
398		bus-range = <0 0>;
399		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
400			  0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
401	};
402};
403