1/*
2 * TQM 8560 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16	model = "tqc,tqm8560";
17	compatible = "tqc,tqm8560";
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	aliases {
22		ethernet0 = &enet0;
23		ethernet1 = &enet1;
24		ethernet2 = &enet2;
25		serial0 = &serial0;
26		serial1 = &serial1;
27		pci0 = &pci0;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		PowerPC,8560@0 {
35			device_type = "cpu";
36			reg = <0>;
37			d-cache-line-size = <32>;
38			i-cache-line-size = <32>;
39			d-cache-size = <32768>;
40			i-cache-size = <32768>;
41			timebase-frequency = <0>;
42			bus-frequency = <0>;
43			clock-frequency = <0>;
44			next-level-cache = <&L2>;
45		};
46	};
47
48	memory {
49		device_type = "memory";
50		reg = <0x00000000 0x10000000>;
51	};
52
53	soc@e0000000 {
54		#address-cells = <1>;
55		#size-cells = <1>;
56		device_type = "soc";
57		ranges = <0x0 0xe0000000 0x100000>;
58		reg = <0xe0000000 0x200>;
59		bus-frequency = <0>;
60		compatible = "fsl,mpc8560-immr", "simple-bus";
61
62		memory-controller@2000 {
63			compatible = "fsl,mpc8540-memory-controller";
64			reg = <0x2000 0x1000>;
65			interrupt-parent = <&mpic>;
66			interrupts = <18 2>;
67		};
68
69		L2: l2-cache-controller@20000 {
70			compatible = "fsl,mpc8540-l2-cache-controller";
71			reg = <0x20000 0x1000>;
72			cache-line-size = <32>;
73			cache-size = <0x40000>;	// L2, 256K
74			interrupt-parent = <&mpic>;
75			interrupts = <16 2>;
76		};
77
78		i2c@3000 {
79			#address-cells = <1>;
80			#size-cells = <0>;
81			cell-index = <0>;
82			compatible = "fsl-i2c";
83			reg = <0x3000 0x100>;
84			interrupts = <43 2>;
85			interrupt-parent = <&mpic>;
86			dfsrr;
87
88			dtt@48 {
89				compatible = "national,lm75";
90				reg = <0x48>;
91			};
92
93			rtc@68 {
94				compatible = "dallas,ds1337";
95				reg = <0x68>;
96			};
97		};
98
99		dma@21300 {
100			#address-cells = <1>;
101			#size-cells = <1>;
102			compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
103			reg = <0x21300 0x4>;
104			ranges = <0x0 0x21100 0x200>;
105			cell-index = <0>;
106			dma-channel@0 {
107				compatible = "fsl,mpc8560-dma-channel",
108						"fsl,eloplus-dma-channel";
109				reg = <0x0 0x80>;
110				cell-index = <0>;
111				interrupt-parent = <&mpic>;
112				interrupts = <20 2>;
113			};
114			dma-channel@80 {
115				compatible = "fsl,mpc8560-dma-channel",
116						"fsl,eloplus-dma-channel";
117				reg = <0x80 0x80>;
118				cell-index = <1>;
119				interrupt-parent = <&mpic>;
120				interrupts = <21 2>;
121			};
122			dma-channel@100 {
123				compatible = "fsl,mpc8560-dma-channel",
124						"fsl,eloplus-dma-channel";
125				reg = <0x100 0x80>;
126				cell-index = <2>;
127				interrupt-parent = <&mpic>;
128				interrupts = <22 2>;
129			};
130			dma-channel@180 {
131				compatible = "fsl,mpc8560-dma-channel",
132						"fsl,eloplus-dma-channel";
133				reg = <0x180 0x80>;
134				cell-index = <3>;
135				interrupt-parent = <&mpic>;
136				interrupts = <23 2>;
137			};
138		};
139
140		enet0: ethernet@24000 {
141			#address-cells = <1>;
142			#size-cells = <1>;
143			cell-index = <0>;
144			device_type = "network";
145			model = "TSEC";
146			compatible = "gianfar";
147			reg = <0x24000 0x1000>;
148			ranges = <0x0 0x24000 0x1000>;
149			local-mac-address = [ 00 00 00 00 00 00 ];
150			interrupts = <29 2 30 2 34 2>;
151			interrupt-parent = <&mpic>;
152			tbi-handle = <&tbi0>;
153			phy-handle = <&phy2>;
154
155			mdio@520 {
156				#address-cells = <1>;
157				#size-cells = <0>;
158				compatible = "fsl,gianfar-mdio";
159				reg = <0x520 0x20>;
160
161				phy1: ethernet-phy@1 {
162					interrupt-parent = <&mpic>;
163					interrupts = <8 1>;
164					reg = <1>;
165					device_type = "ethernet-phy";
166				};
167				phy2: ethernet-phy@2 {
168					interrupt-parent = <&mpic>;
169					interrupts = <8 1>;
170					reg = <2>;
171					device_type = "ethernet-phy";
172				};
173				phy3: ethernet-phy@3 {
174					interrupt-parent = <&mpic>;
175					interrupts = <8 1>;
176					reg = <3>;
177					device_type = "ethernet-phy";
178				};
179				tbi0: tbi-phy@11 {
180					reg = <0x11>;
181					device_type = "tbi-phy";
182				};
183			};
184		};
185
186		enet1: ethernet@25000 {
187			#address-cells = <1>;
188			#size-cells = <1>;
189			cell-index = <1>;
190			device_type = "network";
191			model = "TSEC";
192			compatible = "gianfar";
193			reg = <0x25000 0x1000>;
194			ranges = <0x0 0x25000 0x1000>;
195			local-mac-address = [ 00 00 00 00 00 00 ];
196			interrupts = <35 2 36 2 40 2>;
197			interrupt-parent = <&mpic>;
198			tbi-handle = <&tbi1>;
199			phy-handle = <&phy1>;
200
201			mdio@520 {
202				#address-cells = <1>;
203				#size-cells = <0>;
204				compatible = "fsl,gianfar-tbi";
205				reg = <0x520 0x20>;
206
207				tbi1: tbi-phy@11 {
208					reg = <0x11>;
209					device_type = "tbi-phy";
210				};
211			};
212		};
213
214		mpic: pic@40000 {
215			interrupt-controller;
216			#address-cells = <0>;
217			#interrupt-cells = <2>;
218			reg = <0x40000 0x40000>;
219			device_type = "open-pic";
220			compatible = "chrp,open-pic";
221		};
222
223		cpm@919c0 {
224			#address-cells = <1>;
225			#size-cells = <1>;
226			compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
227			reg = <0x919c0 0x30>;
228			ranges;
229
230			muram@80000 {
231				#address-cells = <1>;
232				#size-cells = <1>;
233				ranges = <0 0x80000 0x10000>;
234
235				data@0 {
236					compatible = "fsl,cpm-muram-data";
237					reg = <0 0x4000 0x9000 0x2000>;
238				};
239			};
240
241			brg@919f0 {
242				compatible = "fsl,mpc8560-brg",
243				             "fsl,cpm2-brg",
244				             "fsl,cpm-brg";
245				reg = <0x919f0 0x10 0x915f0 0x10>;
246				clock-frequency = <0>;
247			};
248
249			cpmpic: pic@90c00 {
250				interrupt-controller;
251				#address-cells = <0>;
252				#interrupt-cells = <2>;
253				interrupts = <46 2>;
254				interrupt-parent = <&mpic>;
255				reg = <0x90c00 0x80>;
256				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
257			};
258
259			serial0: serial@91a00 {
260				device_type = "serial";
261				compatible = "fsl,mpc8560-scc-uart",
262				             "fsl,cpm2-scc-uart";
263				reg = <0x91a00 0x20 0x88000 0x100>;
264				fsl,cpm-brg = <1>;
265				fsl,cpm-command = <0x800000>;
266				current-speed = <115200>;
267				interrupts = <40 8>;
268				interrupt-parent = <&cpmpic>;
269			};
270
271			serial1: serial@91a20 {
272				device_type = "serial";
273				compatible = "fsl,mpc8560-scc-uart",
274				             "fsl,cpm2-scc-uart";
275				reg = <0x91a20 0x20 0x88100 0x100>;
276				fsl,cpm-brg = <2>;
277				fsl,cpm-command = <0x4a00000>;
278				current-speed = <115200>;
279				interrupts = <41 8>;
280				interrupt-parent = <&cpmpic>;
281			};
282
283			enet2: ethernet@91340 {
284				device_type = "network";
285				compatible = "fsl,mpc8560-fcc-enet",
286				             "fsl,cpm2-fcc-enet";
287				reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
288				local-mac-address = [ 00 00 00 00 00 00 ];
289				fsl,cpm-command = <0x1a400300>;
290				interrupts = <34 8>;
291				interrupt-parent = <&cpmpic>;
292				phy-handle = <&phy3>;
293			};
294		};
295	};
296
297	localbus@e0005000 {
298		compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
299			     "simple-bus";
300		#address-cells = <2>;
301		#size-cells = <1>;
302		reg = <0xe0005000 0x100>;	// BRx, ORx, etc.
303
304		ranges = <
305			0 0x0 0xfc000000 0x04000000	// NOR FLASH bank 1
306			1 0x0 0xf8000000 0x08000000	// NOR FLASH bank 0
307			2 0x0 0xe3000000 0x00008000	// CAN (2 x i82527)
308		>;
309
310		flash@1,0 {
311			#address-cells = <1>;
312			#size-cells = <1>;
313			compatible = "cfi-flash";
314			reg = <1 0x0 0x8000000>;
315			bank-width = <4>;
316			device-width = <1>;
317
318			partition@0 {
319				label = "kernel";
320				reg = <0x00000000 0x00200000>;
321			};
322			partition@200000 {
323				label = "root";
324				reg = <0x00200000 0x00300000>;
325			};
326			partition@500000 {
327				label = "user";
328				reg = <0x00500000 0x07a00000>;
329			};
330			partition@7f00000 {
331				label = "env1";
332				reg = <0x07f00000 0x00040000>;
333			};
334			partition@7f40000 {
335				label = "env2";
336				reg = <0x07f40000 0x00040000>;
337			};
338			partition@7f80000 {
339				label = "u-boot";
340				reg = <0x07f80000 0x00080000>;
341				read-only;
342			};
343		};
344
345		/* Note: CAN support needs be enabled in U-Boot */
346		can0@2,0 {
347			compatible = "intel,82527"; // Bosch CC770
348			reg = <2 0x0 0x100>;
349			interrupts = <4 1>;
350			interrupt-parent = <&mpic>;
351		};
352
353		can1@2,100 {
354			compatible = "intel,82527"; // Bosch CC770
355			reg = <2 0x100 0x100>;
356			interrupts = <4 1>;
357			interrupt-parent = <&mpic>;
358		};
359	};
360
361	pci0: pci@e0008000 {
362		#interrupt-cells = <1>;
363		#size-cells = <2>;
364		#address-cells = <3>;
365		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
366		device_type = "pci";
367		reg = <0xe0008000 0x1000>;
368		clock-frequency = <66666666>;
369		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
370		interrupt-map = <
371				/* IDSEL 28 */
372				 0xe000 0 0 1 &mpic 2 1
373				 0xe000 0 0 2 &mpic 3 1>;
374
375		interrupt-parent = <&mpic>;
376		interrupts = <24 2>;
377		bus-range = <0 0>;
378		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
379			  0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
380	};
381};
382