1/* 2 * TQM 8555 Device Tree Source 3 * 4 * Copyright 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "tqc,tqm8555"; 16 compatible = "tqc,tqm8555"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8555@0 { 33 device_type = "cpu"; 34 reg = <0>; 35 d-cache-line-size = <32>; 36 i-cache-line-size = <32>; 37 d-cache-size = <32768>; 38 i-cache-size = <32768>; 39 timebase-frequency = <0>; 40 bus-frequency = <0>; 41 clock-frequency = <0>; 42 next-level-cache = <&L2>; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0x00000000 0x10000000>; 49 }; 50 51 soc@e0000000 { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 device_type = "soc"; 55 ranges = <0x0 0xe0000000 0x100000>; 56 reg = <0xe0000000 0x200>; 57 bus-frequency = <0>; 58 compatible = "fsl,mpc8555-immr", "simple-bus"; 59 60 memory-controller@2000 { 61 compatible = "fsl,8540-memory-controller"; 62 reg = <0x2000 0x1000>; 63 interrupt-parent = <&mpic>; 64 interrupts = <18 2>; 65 }; 66 67 L2: l2-cache-controller@20000 { 68 compatible = "fsl,8540-l2-cache-controller"; 69 reg = <0x20000 0x1000>; 70 cache-line-size = <32>; 71 cache-size = <0x40000>; // L2, 256K 72 interrupt-parent = <&mpic>; 73 interrupts = <16 2>; 74 }; 75 76 i2c@3000 { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 cell-index = <0>; 80 compatible = "fsl-i2c"; 81 reg = <0x3000 0x100>; 82 interrupts = <43 2>; 83 interrupt-parent = <&mpic>; 84 dfsrr; 85 86 dtt@50 { 87 compatible = "national,lm75"; 88 reg = <0x50>; 89 }; 90 91 rtc@68 { 92 compatible = "dallas,ds1337"; 93 reg = <0x68>; 94 }; 95 }; 96 97 dma@21300 { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; 101 reg = <0x21300 0x4>; 102 ranges = <0x0 0x21100 0x200>; 103 cell-index = <0>; 104 dma-channel@0 { 105 compatible = "fsl,mpc8555-dma-channel", 106 "fsl,eloplus-dma-channel"; 107 reg = <0x0 0x80>; 108 cell-index = <0>; 109 interrupt-parent = <&mpic>; 110 interrupts = <20 2>; 111 }; 112 dma-channel@80 { 113 compatible = "fsl,mpc8555-dma-channel", 114 "fsl,eloplus-dma-channel"; 115 reg = <0x80 0x80>; 116 cell-index = <1>; 117 interrupt-parent = <&mpic>; 118 interrupts = <21 2>; 119 }; 120 dma-channel@100 { 121 compatible = "fsl,mpc8555-dma-channel", 122 "fsl,eloplus-dma-channel"; 123 reg = <0x100 0x80>; 124 cell-index = <2>; 125 interrupt-parent = <&mpic>; 126 interrupts = <22 2>; 127 }; 128 dma-channel@180 { 129 compatible = "fsl,mpc8555-dma-channel", 130 "fsl,eloplus-dma-channel"; 131 reg = <0x180 0x80>; 132 cell-index = <3>; 133 interrupt-parent = <&mpic>; 134 interrupts = <23 2>; 135 }; 136 }; 137 138 mdio@24520 { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 compatible = "fsl,gianfar-mdio"; 142 reg = <0x24520 0x20>; 143 144 phy1: ethernet-phy@1 { 145 interrupt-parent = <&mpic>; 146 interrupts = <8 1>; 147 reg = <1>; 148 device_type = "ethernet-phy"; 149 }; 150 phy2: ethernet-phy@2 { 151 interrupt-parent = <&mpic>; 152 interrupts = <8 1>; 153 reg = <2>; 154 device_type = "ethernet-phy"; 155 }; 156 phy3: ethernet-phy@3 { 157 interrupt-parent = <&mpic>; 158 interrupts = <8 1>; 159 reg = <3>; 160 device_type = "ethernet-phy"; 161 }; 162 tbi0: tbi-phy@11 { 163 reg = <0x11>; 164 device_type = "tbi-phy"; 165 }; 166 }; 167 168 mdio@25520 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "fsl,gianfar-tbi"; 172 reg = <0x25520 0x20>; 173 174 tbi1: tbi-phy@11 { 175 reg = <0x11>; 176 device_type = "tbi-phy"; 177 }; 178 }; 179 180 enet0: ethernet@24000 { 181 cell-index = <0>; 182 device_type = "network"; 183 model = "TSEC"; 184 compatible = "gianfar"; 185 reg = <0x24000 0x1000>; 186 local-mac-address = [ 00 00 00 00 00 00 ]; 187 interrupts = <29 2 30 2 34 2>; 188 interrupt-parent = <&mpic>; 189 tbi-handle = <&tbi0>; 190 phy-handle = <&phy2>; 191 }; 192 193 enet1: ethernet@25000 { 194 cell-index = <1>; 195 device_type = "network"; 196 model = "TSEC"; 197 compatible = "gianfar"; 198 reg = <0x25000 0x1000>; 199 local-mac-address = [ 00 00 00 00 00 00 ]; 200 interrupts = <35 2 36 2 40 2>; 201 interrupt-parent = <&mpic>; 202 tbi-handle = <&tbi1>; 203 phy-handle = <&phy1>; 204 }; 205 206 serial0: serial@4500 { 207 cell-index = <0>; 208 device_type = "serial"; 209 compatible = "ns16550"; 210 reg = <0x4500 0x100>; // reg base, size 211 clock-frequency = <0>; // should we fill in in uboot? 212 interrupts = <42 2>; 213 interrupt-parent = <&mpic>; 214 }; 215 216 serial1: serial@4600 { 217 cell-index = <1>; 218 device_type = "serial"; 219 compatible = "ns16550"; 220 reg = <0x4600 0x100>; // reg base, size 221 clock-frequency = <0>; // should we fill in in uboot? 222 interrupts = <42 2>; 223 interrupt-parent = <&mpic>; 224 }; 225 226 crypto@30000 { 227 compatible = "fsl,sec2.0"; 228 reg = <0x30000 0x10000>; 229 interrupts = <45 2>; 230 interrupt-parent = <&mpic>; 231 fsl,num-channels = <4>; 232 fsl,channel-fifo-len = <24>; 233 fsl,exec-units-mask = <0x7e>; 234 fsl,descriptor-types-mask = <0x01010ebf>; 235 }; 236 237 mpic: pic@40000 { 238 interrupt-controller; 239 #address-cells = <0>; 240 #interrupt-cells = <2>; 241 reg = <0x40000 0x40000>; 242 device_type = "open-pic"; 243 compatible = "chrp,open-pic"; 244 }; 245 246 cpm@919c0 { 247 #address-cells = <1>; 248 #size-cells = <1>; 249 compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus"; 250 reg = <0x919c0 0x30>; 251 ranges; 252 253 muram@80000 { 254 #address-cells = <1>; 255 #size-cells = <1>; 256 ranges = <0 0x80000 0x10000>; 257 258 data@0 { 259 compatible = "fsl,cpm-muram-data"; 260 reg = <0 0x2000 0x9000 0x1000>; 261 }; 262 }; 263 264 brg@919f0 { 265 compatible = "fsl,mpc8555-brg", 266 "fsl,cpm2-brg", 267 "fsl,cpm-brg"; 268 reg = <0x919f0 0x10 0x915f0 0x10>; 269 clock-frequency = <0>; 270 }; 271 272 cpmpic: pic@90c00 { 273 interrupt-controller; 274 #address-cells = <0>; 275 #interrupt-cells = <2>; 276 interrupts = <46 2>; 277 interrupt-parent = <&mpic>; 278 reg = <0x90c00 0x80>; 279 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; 280 }; 281 }; 282 }; 283 284 pci0: pci@e0008000 { 285 cell-index = <0>; 286 #interrupt-cells = <1>; 287 #size-cells = <2>; 288 #address-cells = <3>; 289 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 290 device_type = "pci"; 291 reg = <0xe0008000 0x1000>; 292 clock-frequency = <66666666>; 293 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 294 interrupt-map = < 295 /* IDSEL 28 */ 296 0xe000 0 0 1 &mpic 2 1 297 0xe000 0 0 2 &mpic 3 1>; 298 299 interrupt-parent = <&mpic>; 300 interrupts = <24 2>; 301 bus-range = <0 0>; 302 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 303 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 304 }; 305}; 306