10052bc5dSKumar Gala/* 20052bc5dSKumar Gala * TQM 8555 Device Tree Source 30052bc5dSKumar Gala * 40052bc5dSKumar Gala * Copyright 2008 Freescale Semiconductor Inc. 50052bc5dSKumar Gala * 60052bc5dSKumar Gala * This program is free software; you can redistribute it and/or modify it 70052bc5dSKumar Gala * under the terms of the GNU General Public License as published by the 80052bc5dSKumar Gala * Free Software Foundation; either version 2 of the License, or (at your 90052bc5dSKumar Gala * option) any later version. 100052bc5dSKumar Gala */ 110052bc5dSKumar Gala 120052bc5dSKumar Gala/dts-v1/; 130052bc5dSKumar Gala 140052bc5dSKumar Gala/ { 154fb035f6SWolfgang Grandegger model = "tqc,tqm8555"; 164fb035f6SWolfgang Grandegger compatible = "tqc,tqm8555"; 170052bc5dSKumar Gala #address-cells = <1>; 180052bc5dSKumar Gala #size-cells = <1>; 190052bc5dSKumar Gala 200052bc5dSKumar Gala aliases { 210052bc5dSKumar Gala ethernet0 = &enet0; 220052bc5dSKumar Gala ethernet1 = &enet1; 230052bc5dSKumar Gala serial0 = &serial0; 240052bc5dSKumar Gala serial1 = &serial1; 250052bc5dSKumar Gala pci0 = &pci0; 260052bc5dSKumar Gala }; 270052bc5dSKumar Gala 280052bc5dSKumar Gala cpus { 290052bc5dSKumar Gala #address-cells = <1>; 300052bc5dSKumar Gala #size-cells = <0>; 310052bc5dSKumar Gala 320052bc5dSKumar Gala PowerPC,8555@0 { 330052bc5dSKumar Gala device_type = "cpu"; 340052bc5dSKumar Gala reg = <0>; 350052bc5dSKumar Gala d-cache-line-size = <32>; 360052bc5dSKumar Gala i-cache-line-size = <32>; 370052bc5dSKumar Gala d-cache-size = <32768>; 380052bc5dSKumar Gala i-cache-size = <32768>; 390052bc5dSKumar Gala timebase-frequency = <0>; 400052bc5dSKumar Gala bus-frequency = <0>; 410052bc5dSKumar Gala clock-frequency = <0>; 42c054065bSKumar Gala next-level-cache = <&L2>; 430052bc5dSKumar Gala }; 440052bc5dSKumar Gala }; 450052bc5dSKumar Gala 460052bc5dSKumar Gala memory { 470052bc5dSKumar Gala device_type = "memory"; 480052bc5dSKumar Gala reg = <0x00000000 0x10000000>; 490052bc5dSKumar Gala }; 500052bc5dSKumar Gala 51f67be814SKumar Gala soc@e0000000 { 520052bc5dSKumar Gala #address-cells = <1>; 530052bc5dSKumar Gala #size-cells = <1>; 540052bc5dSKumar Gala device_type = "soc"; 550052bc5dSKumar Gala ranges = <0x0 0xe0000000 0x100000>; 560052bc5dSKumar Gala reg = <0xe0000000 0x200>; 570052bc5dSKumar Gala bus-frequency = <0>; 580052bc5dSKumar Gala compatible = "fsl,mpc8555-immr", "simple-bus"; 590052bc5dSKumar Gala 600052bc5dSKumar Gala memory-controller@2000 { 610052bc5dSKumar Gala compatible = "fsl,8540-memory-controller"; 620052bc5dSKumar Gala reg = <0x2000 0x1000>; 630052bc5dSKumar Gala interrupt-parent = <&mpic>; 640052bc5dSKumar Gala interrupts = <18 2>; 650052bc5dSKumar Gala }; 660052bc5dSKumar Gala 67c054065bSKumar Gala L2: l2-cache-controller@20000 { 680052bc5dSKumar Gala compatible = "fsl,8540-l2-cache-controller"; 690052bc5dSKumar Gala reg = <0x20000 0x1000>; 700052bc5dSKumar Gala cache-line-size = <32>; 710052bc5dSKumar Gala cache-size = <0x40000>; // L2, 256K 720052bc5dSKumar Gala interrupt-parent = <&mpic>; 730052bc5dSKumar Gala interrupts = <16 2>; 740052bc5dSKumar Gala }; 750052bc5dSKumar Gala 760052bc5dSKumar Gala i2c@3000 { 770052bc5dSKumar Gala #address-cells = <1>; 780052bc5dSKumar Gala #size-cells = <0>; 790052bc5dSKumar Gala cell-index = <0>; 800052bc5dSKumar Gala compatible = "fsl-i2c"; 810052bc5dSKumar Gala reg = <0x3000 0x100>; 820052bc5dSKumar Gala interrupts = <43 2>; 830052bc5dSKumar Gala interrupt-parent = <&mpic>; 840052bc5dSKumar Gala dfsrr; 850052bc5dSKumar Gala 860052bc5dSKumar Gala rtc@68 { 870052bc5dSKumar Gala compatible = "dallas,ds1337"; 880052bc5dSKumar Gala reg = <0x68>; 890052bc5dSKumar Gala }; 900052bc5dSKumar Gala }; 910052bc5dSKumar Gala 92dee80553SKumar Gala dma@21300 { 93dee80553SKumar Gala #address-cells = <1>; 94dee80553SKumar Gala #size-cells = <1>; 95dee80553SKumar Gala compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; 96dee80553SKumar Gala reg = <0x21300 0x4>; 97dee80553SKumar Gala ranges = <0x0 0x21100 0x200>; 98dee80553SKumar Gala cell-index = <0>; 99dee80553SKumar Gala dma-channel@0 { 100dee80553SKumar Gala compatible = "fsl,mpc8555-dma-channel", 101dee80553SKumar Gala "fsl,eloplus-dma-channel"; 102dee80553SKumar Gala reg = <0x0 0x80>; 103dee80553SKumar Gala cell-index = <0>; 104dee80553SKumar Gala interrupt-parent = <&mpic>; 105dee80553SKumar Gala interrupts = <20 2>; 106dee80553SKumar Gala }; 107dee80553SKumar Gala dma-channel@80 { 108dee80553SKumar Gala compatible = "fsl,mpc8555-dma-channel", 109dee80553SKumar Gala "fsl,eloplus-dma-channel"; 110dee80553SKumar Gala reg = <0x80 0x80>; 111dee80553SKumar Gala cell-index = <1>; 112dee80553SKumar Gala interrupt-parent = <&mpic>; 113dee80553SKumar Gala interrupts = <21 2>; 114dee80553SKumar Gala }; 115dee80553SKumar Gala dma-channel@100 { 116dee80553SKumar Gala compatible = "fsl,mpc8555-dma-channel", 117dee80553SKumar Gala "fsl,eloplus-dma-channel"; 118dee80553SKumar Gala reg = <0x100 0x80>; 119dee80553SKumar Gala cell-index = <2>; 120dee80553SKumar Gala interrupt-parent = <&mpic>; 121dee80553SKumar Gala interrupts = <22 2>; 122dee80553SKumar Gala }; 123dee80553SKumar Gala dma-channel@180 { 124dee80553SKumar Gala compatible = "fsl,mpc8555-dma-channel", 125dee80553SKumar Gala "fsl,eloplus-dma-channel"; 126dee80553SKumar Gala reg = <0x180 0x80>; 127dee80553SKumar Gala cell-index = <3>; 128dee80553SKumar Gala interrupt-parent = <&mpic>; 129dee80553SKumar Gala interrupts = <23 2>; 130dee80553SKumar Gala }; 131dee80553SKumar Gala }; 132dee80553SKumar Gala 1330052bc5dSKumar Gala mdio@24520 { 1340052bc5dSKumar Gala #address-cells = <1>; 1350052bc5dSKumar Gala #size-cells = <0>; 1360052bc5dSKumar Gala compatible = "fsl,gianfar-mdio"; 1370052bc5dSKumar Gala reg = <0x24520 0x20>; 1380052bc5dSKumar Gala 1390052bc5dSKumar Gala phy1: ethernet-phy@1 { 1400052bc5dSKumar Gala interrupt-parent = <&mpic>; 1410052bc5dSKumar Gala interrupts = <8 1>; 1420052bc5dSKumar Gala reg = <1>; 1430052bc5dSKumar Gala device_type = "ethernet-phy"; 1440052bc5dSKumar Gala }; 1450052bc5dSKumar Gala phy2: ethernet-phy@2 { 1460052bc5dSKumar Gala interrupt-parent = <&mpic>; 1470052bc5dSKumar Gala interrupts = <8 1>; 1480052bc5dSKumar Gala reg = <2>; 1490052bc5dSKumar Gala device_type = "ethernet-phy"; 1500052bc5dSKumar Gala }; 1510052bc5dSKumar Gala phy3: ethernet-phy@3 { 1520052bc5dSKumar Gala interrupt-parent = <&mpic>; 1530052bc5dSKumar Gala interrupts = <8 1>; 1540052bc5dSKumar Gala reg = <3>; 1550052bc5dSKumar Gala device_type = "ethernet-phy"; 1560052bc5dSKumar Gala }; 157b31a1d8bSAndy Fleming tbi0: tbi-phy@11 { 158b31a1d8bSAndy Fleming reg = <0x11>; 159b31a1d8bSAndy Fleming device_type = "tbi-phy"; 160b31a1d8bSAndy Fleming }; 161b31a1d8bSAndy Fleming }; 162b31a1d8bSAndy Fleming 163b31a1d8bSAndy Fleming mdio@25520 { 164b31a1d8bSAndy Fleming #address-cells = <1>; 165b31a1d8bSAndy Fleming #size-cells = <0>; 166b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 167b31a1d8bSAndy Fleming reg = <0x25520 0x20>; 168b31a1d8bSAndy Fleming 169b31a1d8bSAndy Fleming tbi1: tbi-phy@11 { 170b31a1d8bSAndy Fleming reg = <0x11>; 171b31a1d8bSAndy Fleming device_type = "tbi-phy"; 172b31a1d8bSAndy Fleming }; 1730052bc5dSKumar Gala }; 1740052bc5dSKumar Gala 1750052bc5dSKumar Gala enet0: ethernet@24000 { 1760052bc5dSKumar Gala cell-index = <0>; 1770052bc5dSKumar Gala device_type = "network"; 1780052bc5dSKumar Gala model = "TSEC"; 1790052bc5dSKumar Gala compatible = "gianfar"; 1800052bc5dSKumar Gala reg = <0x24000 0x1000>; 1810052bc5dSKumar Gala local-mac-address = [ 00 00 00 00 00 00 ]; 1820052bc5dSKumar Gala interrupts = <29 2 30 2 34 2>; 1830052bc5dSKumar Gala interrupt-parent = <&mpic>; 184b31a1d8bSAndy Fleming tbi-handle = <&tbi0>; 1850052bc5dSKumar Gala phy-handle = <&phy2>; 1860052bc5dSKumar Gala }; 1870052bc5dSKumar Gala 1880052bc5dSKumar Gala enet1: ethernet@25000 { 1890052bc5dSKumar Gala cell-index = <1>; 1900052bc5dSKumar Gala device_type = "network"; 1910052bc5dSKumar Gala model = "TSEC"; 1920052bc5dSKumar Gala compatible = "gianfar"; 1930052bc5dSKumar Gala reg = <0x25000 0x1000>; 1940052bc5dSKumar Gala local-mac-address = [ 00 00 00 00 00 00 ]; 1950052bc5dSKumar Gala interrupts = <35 2 36 2 40 2>; 1960052bc5dSKumar Gala interrupt-parent = <&mpic>; 197b31a1d8bSAndy Fleming tbi-handle = <&tbi1>; 1980052bc5dSKumar Gala phy-handle = <&phy1>; 1990052bc5dSKumar Gala }; 2000052bc5dSKumar Gala 2010052bc5dSKumar Gala serial0: serial@4500 { 2020052bc5dSKumar Gala cell-index = <0>; 2030052bc5dSKumar Gala device_type = "serial"; 2040052bc5dSKumar Gala compatible = "ns16550"; 2050052bc5dSKumar Gala reg = <0x4500 0x100>; // reg base, size 2060052bc5dSKumar Gala clock-frequency = <0>; // should we fill in in uboot? 2070052bc5dSKumar Gala interrupts = <42 2>; 2080052bc5dSKumar Gala interrupt-parent = <&mpic>; 2090052bc5dSKumar Gala }; 2100052bc5dSKumar Gala 2110052bc5dSKumar Gala serial1: serial@4600 { 2120052bc5dSKumar Gala cell-index = <1>; 2130052bc5dSKumar Gala device_type = "serial"; 2140052bc5dSKumar Gala compatible = "ns16550"; 2150052bc5dSKumar Gala reg = <0x4600 0x100>; // reg base, size 2160052bc5dSKumar Gala clock-frequency = <0>; // should we fill in in uboot? 2170052bc5dSKumar Gala interrupts = <42 2>; 2180052bc5dSKumar Gala interrupt-parent = <&mpic>; 2190052bc5dSKumar Gala }; 2200052bc5dSKumar Gala 2213fd44736SKim Phillips crypto@30000 { 2223fd44736SKim Phillips compatible = "fsl,sec2.0"; 2233fd44736SKim Phillips reg = <0x30000 0x10000>; 2243fd44736SKim Phillips interrupts = <45 2>; 2253fd44736SKim Phillips interrupt-parent = <&mpic>; 2263fd44736SKim Phillips fsl,num-channels = <4>; 2273fd44736SKim Phillips fsl,channel-fifo-len = <24>; 2283fd44736SKim Phillips fsl,exec-units-mask = <0x7e>; 2293fd44736SKim Phillips fsl,descriptor-types-mask = <0x01010ebf>; 2303fd44736SKim Phillips }; 2313fd44736SKim Phillips 2320052bc5dSKumar Gala mpic: pic@40000 { 2330052bc5dSKumar Gala interrupt-controller; 2340052bc5dSKumar Gala #address-cells = <0>; 2350052bc5dSKumar Gala #interrupt-cells = <2>; 2360052bc5dSKumar Gala reg = <0x40000 0x40000>; 2370052bc5dSKumar Gala device_type = "open-pic"; 238acd4b715SKumar Gala compatible = "chrp,open-pic"; 2390052bc5dSKumar Gala }; 2400052bc5dSKumar Gala 2410052bc5dSKumar Gala cpm@919c0 { 2420052bc5dSKumar Gala #address-cells = <1>; 2430052bc5dSKumar Gala #size-cells = <1>; 2440052bc5dSKumar Gala compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus"; 2450052bc5dSKumar Gala reg = <0x919c0 0x30>; 2460052bc5dSKumar Gala ranges; 2470052bc5dSKumar Gala 2480052bc5dSKumar Gala muram@80000 { 2490052bc5dSKumar Gala #address-cells = <1>; 2500052bc5dSKumar Gala #size-cells = <1>; 2510052bc5dSKumar Gala ranges = <0 0x80000 0x10000>; 2520052bc5dSKumar Gala 2530052bc5dSKumar Gala data@0 { 2540052bc5dSKumar Gala compatible = "fsl,cpm-muram-data"; 2550052bc5dSKumar Gala reg = <0 0x2000 0x9000 0x1000>; 2560052bc5dSKumar Gala }; 2570052bc5dSKumar Gala }; 2580052bc5dSKumar Gala 2590052bc5dSKumar Gala brg@919f0 { 2600052bc5dSKumar Gala compatible = "fsl,mpc8555-brg", 2610052bc5dSKumar Gala "fsl,cpm2-brg", 2620052bc5dSKumar Gala "fsl,cpm-brg"; 2630052bc5dSKumar Gala reg = <0x919f0 0x10 0x915f0 0x10>; 2640052bc5dSKumar Gala clock-frequency = <0>; 2650052bc5dSKumar Gala }; 2660052bc5dSKumar Gala 2670052bc5dSKumar Gala cpmpic: pic@90c00 { 2680052bc5dSKumar Gala interrupt-controller; 2690052bc5dSKumar Gala #address-cells = <0>; 2700052bc5dSKumar Gala #interrupt-cells = <2>; 2710052bc5dSKumar Gala interrupts = <46 2>; 2720052bc5dSKumar Gala interrupt-parent = <&mpic>; 2730052bc5dSKumar Gala reg = <0x90c00 0x80>; 2740052bc5dSKumar Gala compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; 2750052bc5dSKumar Gala }; 2760052bc5dSKumar Gala }; 2770052bc5dSKumar Gala }; 2780052bc5dSKumar Gala 2790052bc5dSKumar Gala pci0: pci@e0008000 { 2800052bc5dSKumar Gala cell-index = <0>; 2810052bc5dSKumar Gala #interrupt-cells = <1>; 2820052bc5dSKumar Gala #size-cells = <2>; 2830052bc5dSKumar Gala #address-cells = <3>; 2840052bc5dSKumar Gala compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 2850052bc5dSKumar Gala device_type = "pci"; 2860052bc5dSKumar Gala reg = <0xe0008000 0x1000>; 2870052bc5dSKumar Gala clock-frequency = <66666666>; 2880052bc5dSKumar Gala interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 2890052bc5dSKumar Gala interrupt-map = < 2900052bc5dSKumar Gala /* IDSEL 28 */ 2910052bc5dSKumar Gala 0xe000 0 0 1 &mpic 2 1 2920052bc5dSKumar Gala 0xe000 0 0 2 &mpic 3 1>; 2930052bc5dSKumar Gala 2940052bc5dSKumar Gala interrupt-parent = <&mpic>; 2950052bc5dSKumar Gala interrupts = <24 2>; 2960052bc5dSKumar Gala bus-range = <0 0>; 2970052bc5dSKumar Gala ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 2980052bc5dSKumar Gala 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 2990052bc5dSKumar Gala }; 3000052bc5dSKumar Gala}; 301