12874c5fdSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-or-later 20052bc5dSKumar Gala/* 30052bc5dSKumar Gala * TQM 8555 Device Tree Source 40052bc5dSKumar Gala * 50052bc5dSKumar Gala * Copyright 2008 Freescale Semiconductor Inc. 60052bc5dSKumar Gala */ 70052bc5dSKumar Gala 80052bc5dSKumar Gala/dts-v1/; 90052bc5dSKumar Gala 10*c1024320SPali Rohár/include/ "fsl/e500v1_power_isa.dtsi" 11*c1024320SPali Rohár 120052bc5dSKumar Gala/ { 134fb035f6SWolfgang Grandegger model = "tqc,tqm8555"; 144fb035f6SWolfgang Grandegger compatible = "tqc,tqm8555"; 150052bc5dSKumar Gala #address-cells = <1>; 160052bc5dSKumar Gala #size-cells = <1>; 170052bc5dSKumar Gala 180052bc5dSKumar Gala aliases { 190052bc5dSKumar Gala ethernet0 = &enet0; 200052bc5dSKumar Gala ethernet1 = &enet1; 210052bc5dSKumar Gala serial0 = &serial0; 220052bc5dSKumar Gala serial1 = &serial1; 230052bc5dSKumar Gala pci0 = &pci0; 240052bc5dSKumar Gala }; 250052bc5dSKumar Gala 260052bc5dSKumar Gala cpus { 270052bc5dSKumar Gala #address-cells = <1>; 280052bc5dSKumar Gala #size-cells = <0>; 290052bc5dSKumar Gala 300052bc5dSKumar Gala PowerPC,8555@0 { 310052bc5dSKumar Gala device_type = "cpu"; 320052bc5dSKumar Gala reg = <0>; 330052bc5dSKumar Gala d-cache-line-size = <32>; 340052bc5dSKumar Gala i-cache-line-size = <32>; 350052bc5dSKumar Gala d-cache-size = <32768>; 360052bc5dSKumar Gala i-cache-size = <32768>; 370052bc5dSKumar Gala timebase-frequency = <0>; 380052bc5dSKumar Gala bus-frequency = <0>; 390052bc5dSKumar Gala clock-frequency = <0>; 40c054065bSKumar Gala next-level-cache = <&L2>; 410052bc5dSKumar Gala }; 420052bc5dSKumar Gala }; 430052bc5dSKumar Gala 440052bc5dSKumar Gala memory { 450052bc5dSKumar Gala device_type = "memory"; 460052bc5dSKumar Gala reg = <0x00000000 0x10000000>; 470052bc5dSKumar Gala }; 480052bc5dSKumar Gala 49f67be814SKumar Gala soc@e0000000 { 500052bc5dSKumar Gala #address-cells = <1>; 510052bc5dSKumar Gala #size-cells = <1>; 520052bc5dSKumar Gala device_type = "soc"; 530052bc5dSKumar Gala ranges = <0x0 0xe0000000 0x100000>; 540052bc5dSKumar Gala bus-frequency = <0>; 550052bc5dSKumar Gala compatible = "fsl,mpc8555-immr", "simple-bus"; 560052bc5dSKumar Gala 57e1a22897SKumar Gala ecm-law@0 { 58e1a22897SKumar Gala compatible = "fsl,ecm-law"; 59e1a22897SKumar Gala reg = <0x0 0x1000>; 60e1a22897SKumar Gala fsl,num-laws = <8>; 61e1a22897SKumar Gala }; 62e1a22897SKumar Gala 63e1a22897SKumar Gala ecm@1000 { 64e1a22897SKumar Gala compatible = "fsl,mpc8555-ecm", "fsl,ecm"; 65e1a22897SKumar Gala reg = <0x1000 0x1000>; 66e1a22897SKumar Gala interrupts = <17 2>; 67e1a22897SKumar Gala interrupt-parent = <&mpic>; 68e1a22897SKumar Gala }; 69e1a22897SKumar Gala 700052bc5dSKumar Gala memory-controller@2000 { 71fe671772SKumar Gala compatible = "fsl,mpc8540-memory-controller"; 720052bc5dSKumar Gala reg = <0x2000 0x1000>; 730052bc5dSKumar Gala interrupt-parent = <&mpic>; 740052bc5dSKumar Gala interrupts = <18 2>; 750052bc5dSKumar Gala }; 760052bc5dSKumar Gala 77c054065bSKumar Gala L2: l2-cache-controller@20000 { 78fe671772SKumar Gala compatible = "fsl,mpc8540-l2-cache-controller"; 790052bc5dSKumar Gala reg = <0x20000 0x1000>; 800052bc5dSKumar Gala cache-line-size = <32>; 810052bc5dSKumar Gala cache-size = <0x40000>; // L2, 256K 820052bc5dSKumar Gala interrupt-parent = <&mpic>; 830052bc5dSKumar Gala interrupts = <16 2>; 840052bc5dSKumar Gala }; 850052bc5dSKumar Gala 860052bc5dSKumar Gala i2c@3000 { 870052bc5dSKumar Gala #address-cells = <1>; 880052bc5dSKumar Gala #size-cells = <0>; 890052bc5dSKumar Gala cell-index = <0>; 900052bc5dSKumar Gala compatible = "fsl-i2c"; 910052bc5dSKumar Gala reg = <0x3000 0x100>; 920052bc5dSKumar Gala interrupts = <43 2>; 930052bc5dSKumar Gala interrupt-parent = <&mpic>; 940052bc5dSKumar Gala dfsrr; 950052bc5dSKumar Gala 966467cae3SWolfgang Grandegger dtt@48 { 970f73a449SWolfgang Grandegger compatible = "national,lm75"; 986467cae3SWolfgang Grandegger reg = <0x48>; 990f73a449SWolfgang Grandegger }; 1000f73a449SWolfgang Grandegger 1010052bc5dSKumar Gala rtc@68 { 1020052bc5dSKumar Gala compatible = "dallas,ds1337"; 1030052bc5dSKumar Gala reg = <0x68>; 1040052bc5dSKumar Gala }; 1050052bc5dSKumar Gala }; 1060052bc5dSKumar Gala 107dee80553SKumar Gala dma@21300 { 108dee80553SKumar Gala #address-cells = <1>; 109dee80553SKumar Gala #size-cells = <1>; 110dee80553SKumar Gala compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; 111dee80553SKumar Gala reg = <0x21300 0x4>; 112dee80553SKumar Gala ranges = <0x0 0x21100 0x200>; 113dee80553SKumar Gala cell-index = <0>; 114dee80553SKumar Gala dma-channel@0 { 115dee80553SKumar Gala compatible = "fsl,mpc8555-dma-channel", 116dee80553SKumar Gala "fsl,eloplus-dma-channel"; 117dee80553SKumar Gala reg = <0x0 0x80>; 118dee80553SKumar Gala cell-index = <0>; 119dee80553SKumar Gala interrupt-parent = <&mpic>; 120dee80553SKumar Gala interrupts = <20 2>; 121dee80553SKumar Gala }; 122dee80553SKumar Gala dma-channel@80 { 123dee80553SKumar Gala compatible = "fsl,mpc8555-dma-channel", 124dee80553SKumar Gala "fsl,eloplus-dma-channel"; 125dee80553SKumar Gala reg = <0x80 0x80>; 126dee80553SKumar Gala cell-index = <1>; 127dee80553SKumar Gala interrupt-parent = <&mpic>; 128dee80553SKumar Gala interrupts = <21 2>; 129dee80553SKumar Gala }; 130dee80553SKumar Gala dma-channel@100 { 131dee80553SKumar Gala compatible = "fsl,mpc8555-dma-channel", 132dee80553SKumar Gala "fsl,eloplus-dma-channel"; 133dee80553SKumar Gala reg = <0x100 0x80>; 134dee80553SKumar Gala cell-index = <2>; 135dee80553SKumar Gala interrupt-parent = <&mpic>; 136dee80553SKumar Gala interrupts = <22 2>; 137dee80553SKumar Gala }; 138dee80553SKumar Gala dma-channel@180 { 139dee80553SKumar Gala compatible = "fsl,mpc8555-dma-channel", 140dee80553SKumar Gala "fsl,eloplus-dma-channel"; 141dee80553SKumar Gala reg = <0x180 0x80>; 142dee80553SKumar Gala cell-index = <3>; 143dee80553SKumar Gala interrupt-parent = <&mpic>; 144dee80553SKumar Gala interrupts = <23 2>; 145dee80553SKumar Gala }; 146dee80553SKumar Gala }; 147dee80553SKumar Gala 14884ba4a58SAnton Vorontsov enet0: ethernet@24000 { 14984ba4a58SAnton Vorontsov #address-cells = <1>; 15084ba4a58SAnton Vorontsov #size-cells = <1>; 15184ba4a58SAnton Vorontsov cell-index = <0>; 15284ba4a58SAnton Vorontsov device_type = "network"; 15384ba4a58SAnton Vorontsov model = "TSEC"; 15484ba4a58SAnton Vorontsov compatible = "gianfar"; 15584ba4a58SAnton Vorontsov reg = <0x24000 0x1000>; 15684ba4a58SAnton Vorontsov ranges = <0x0 0x24000 0x1000>; 15784ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 15884ba4a58SAnton Vorontsov interrupts = <29 2 30 2 34 2>; 15984ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 16084ba4a58SAnton Vorontsov tbi-handle = <&tbi0>; 16184ba4a58SAnton Vorontsov phy-handle = <&phy2>; 16284ba4a58SAnton Vorontsov 16384ba4a58SAnton Vorontsov mdio@520 { 1640052bc5dSKumar Gala #address-cells = <1>; 1650052bc5dSKumar Gala #size-cells = <0>; 1660052bc5dSKumar Gala compatible = "fsl,gianfar-mdio"; 16784ba4a58SAnton Vorontsov reg = <0x520 0x20>; 1680052bc5dSKumar Gala 1690052bc5dSKumar Gala phy1: ethernet-phy@1 { 1700052bc5dSKumar Gala interrupt-parent = <&mpic>; 1710052bc5dSKumar Gala interrupts = <8 1>; 1720052bc5dSKumar Gala reg = <1>; 1730052bc5dSKumar Gala }; 1740052bc5dSKumar Gala phy2: ethernet-phy@2 { 1750052bc5dSKumar Gala interrupt-parent = <&mpic>; 1760052bc5dSKumar Gala interrupts = <8 1>; 1770052bc5dSKumar Gala reg = <2>; 1780052bc5dSKumar Gala }; 1790052bc5dSKumar Gala phy3: ethernet-phy@3 { 1800052bc5dSKumar Gala interrupt-parent = <&mpic>; 1810052bc5dSKumar Gala interrupts = <8 1>; 1820052bc5dSKumar Gala reg = <3>; 1830052bc5dSKumar Gala }; 184b31a1d8bSAndy Fleming tbi0: tbi-phy@11 { 185b31a1d8bSAndy Fleming reg = <0x11>; 186b31a1d8bSAndy Fleming device_type = "tbi-phy"; 187b31a1d8bSAndy Fleming }; 188b31a1d8bSAndy Fleming }; 18984ba4a58SAnton Vorontsov }; 190b31a1d8bSAndy Fleming 19184ba4a58SAnton Vorontsov enet1: ethernet@25000 { 19284ba4a58SAnton Vorontsov #address-cells = <1>; 19384ba4a58SAnton Vorontsov #size-cells = <1>; 19484ba4a58SAnton Vorontsov cell-index = <1>; 19584ba4a58SAnton Vorontsov device_type = "network"; 19684ba4a58SAnton Vorontsov model = "TSEC"; 19784ba4a58SAnton Vorontsov compatible = "gianfar"; 19884ba4a58SAnton Vorontsov reg = <0x25000 0x1000>; 19984ba4a58SAnton Vorontsov ranges = <0x0 0x25000 0x1000>; 20084ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 20184ba4a58SAnton Vorontsov interrupts = <35 2 36 2 40 2>; 20284ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 20384ba4a58SAnton Vorontsov tbi-handle = <&tbi1>; 20484ba4a58SAnton Vorontsov phy-handle = <&phy1>; 20584ba4a58SAnton Vorontsov 20684ba4a58SAnton Vorontsov mdio@520 { 207b31a1d8bSAndy Fleming #address-cells = <1>; 208b31a1d8bSAndy Fleming #size-cells = <0>; 209b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 21084ba4a58SAnton Vorontsov reg = <0x520 0x20>; 211b31a1d8bSAndy Fleming 212b31a1d8bSAndy Fleming tbi1: tbi-phy@11 { 213b31a1d8bSAndy Fleming reg = <0x11>; 214b31a1d8bSAndy Fleming device_type = "tbi-phy"; 215b31a1d8bSAndy Fleming }; 2160052bc5dSKumar Gala }; 2170052bc5dSKumar Gala }; 2180052bc5dSKumar Gala 2190052bc5dSKumar Gala serial0: serial@4500 { 2200052bc5dSKumar Gala cell-index = <0>; 2210052bc5dSKumar Gala device_type = "serial"; 222f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 2230052bc5dSKumar Gala reg = <0x4500 0x100>; // reg base, size 2240052bc5dSKumar Gala clock-frequency = <0>; // should we fill in in uboot? 2250052bc5dSKumar Gala interrupts = <42 2>; 2260052bc5dSKumar Gala interrupt-parent = <&mpic>; 2270052bc5dSKumar Gala }; 2280052bc5dSKumar Gala 2290052bc5dSKumar Gala serial1: serial@4600 { 2300052bc5dSKumar Gala cell-index = <1>; 2310052bc5dSKumar Gala device_type = "serial"; 232f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 2330052bc5dSKumar Gala reg = <0x4600 0x100>; // reg base, size 2340052bc5dSKumar Gala clock-frequency = <0>; // should we fill in in uboot? 2350052bc5dSKumar Gala interrupts = <42 2>; 2360052bc5dSKumar Gala interrupt-parent = <&mpic>; 2370052bc5dSKumar Gala }; 2380052bc5dSKumar Gala 2393fd44736SKim Phillips crypto@30000 { 2403fd44736SKim Phillips compatible = "fsl,sec2.0"; 2413fd44736SKim Phillips reg = <0x30000 0x10000>; 2423fd44736SKim Phillips interrupts = <45 2>; 2433fd44736SKim Phillips interrupt-parent = <&mpic>; 2443fd44736SKim Phillips fsl,num-channels = <4>; 2453fd44736SKim Phillips fsl,channel-fifo-len = <24>; 2463fd44736SKim Phillips fsl,exec-units-mask = <0x7e>; 2473fd44736SKim Phillips fsl,descriptor-types-mask = <0x01010ebf>; 2483fd44736SKim Phillips }; 2493fd44736SKim Phillips 2500052bc5dSKumar Gala mpic: pic@40000 { 2510052bc5dSKumar Gala interrupt-controller; 2520052bc5dSKumar Gala #address-cells = <0>; 2530052bc5dSKumar Gala #interrupt-cells = <2>; 2540052bc5dSKumar Gala reg = <0x40000 0x40000>; 2550052bc5dSKumar Gala device_type = "open-pic"; 256acd4b715SKumar Gala compatible = "chrp,open-pic"; 2570052bc5dSKumar Gala }; 2580052bc5dSKumar Gala 2590052bc5dSKumar Gala cpm@919c0 { 2600052bc5dSKumar Gala #address-cells = <1>; 2610052bc5dSKumar Gala #size-cells = <1>; 2620052bc5dSKumar Gala compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus"; 2630052bc5dSKumar Gala reg = <0x919c0 0x30>; 2640052bc5dSKumar Gala ranges; 2650052bc5dSKumar Gala 2660052bc5dSKumar Gala muram@80000 { 2670052bc5dSKumar Gala #address-cells = <1>; 2680052bc5dSKumar Gala #size-cells = <1>; 2690052bc5dSKumar Gala ranges = <0 0x80000 0x10000>; 2700052bc5dSKumar Gala 2710052bc5dSKumar Gala data@0 { 2720052bc5dSKumar Gala compatible = "fsl,cpm-muram-data"; 2730052bc5dSKumar Gala reg = <0 0x2000 0x9000 0x1000>; 2740052bc5dSKumar Gala }; 2750052bc5dSKumar Gala }; 2760052bc5dSKumar Gala 2770052bc5dSKumar Gala brg@919f0 { 2780052bc5dSKumar Gala compatible = "fsl,mpc8555-brg", 2790052bc5dSKumar Gala "fsl,cpm2-brg", 2800052bc5dSKumar Gala "fsl,cpm-brg"; 2810052bc5dSKumar Gala reg = <0x919f0 0x10 0x915f0 0x10>; 2820052bc5dSKumar Gala clock-frequency = <0>; 2830052bc5dSKumar Gala }; 2840052bc5dSKumar Gala 2850052bc5dSKumar Gala cpmpic: pic@90c00 { 2860052bc5dSKumar Gala interrupt-controller; 2870052bc5dSKumar Gala #address-cells = <0>; 2880052bc5dSKumar Gala #interrupt-cells = <2>; 2890052bc5dSKumar Gala interrupts = <46 2>; 2900052bc5dSKumar Gala interrupt-parent = <&mpic>; 2910052bc5dSKumar Gala reg = <0x90c00 0x80>; 2920052bc5dSKumar Gala compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; 2930052bc5dSKumar Gala }; 2940052bc5dSKumar Gala }; 2950052bc5dSKumar Gala }; 2960052bc5dSKumar Gala 2970052bc5dSKumar Gala pci0: pci@e0008000 { 2980052bc5dSKumar Gala #interrupt-cells = <1>; 2990052bc5dSKumar Gala #size-cells = <2>; 3000052bc5dSKumar Gala #address-cells = <3>; 3010052bc5dSKumar Gala compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 3020052bc5dSKumar Gala device_type = "pci"; 3030052bc5dSKumar Gala reg = <0xe0008000 0x1000>; 3040052bc5dSKumar Gala clock-frequency = <66666666>; 3050052bc5dSKumar Gala interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 3060052bc5dSKumar Gala interrupt-map = < 3070052bc5dSKumar Gala /* IDSEL 28 */ 3080052bc5dSKumar Gala 0xe000 0 0 1 &mpic 2 1 30907c63839SDmitry Eremin-Solenikov 0xe000 0 0 2 &mpic 3 1 31007c63839SDmitry Eremin-Solenikov 0xe000 0 0 3 &mpic 6 1 31107c63839SDmitry Eremin-Solenikov 0xe000 0 0 4 &mpic 5 1 31207c63839SDmitry Eremin-Solenikov 31307c63839SDmitry Eremin-Solenikov /* IDSEL 11 */ 31407c63839SDmitry Eremin-Solenikov 0x5800 0 0 1 &mpic 6 1 31507c63839SDmitry Eremin-Solenikov 0x5800 0 0 2 &mpic 5 1 31607c63839SDmitry Eremin-Solenikov >; 3170052bc5dSKumar Gala 3180052bc5dSKumar Gala interrupt-parent = <&mpic>; 3190052bc5dSKumar Gala interrupts = <24 2>; 3200052bc5dSKumar Gala bus-range = <0 0>; 3210052bc5dSKumar Gala ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 3220052bc5dSKumar Gala 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 3230052bc5dSKumar Gala }; 3240052bc5dSKumar Gala}; 325