1/*
2 * TQM8548 Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16	model = "tqc,tqm8548";
17	compatible = "tqc,tqm8548";
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	aliases {
22		ethernet0 = &enet0;
23		ethernet1 = &enet1;
24		ethernet2 = &enet2;
25		ethernet3 = &enet3;
26
27		serial0 = &serial0;
28		serial1 = &serial1;
29		pci0 = &pci0;
30		pci1 = &pci1;
31	};
32
33	cpus {
34		#address-cells = <1>;
35		#size-cells = <0>;
36
37		PowerPC,8548@0 {
38			device_type = "cpu";
39			reg = <0>;
40			d-cache-line-size = <32>;	// 32 bytes
41			i-cache-line-size = <32>;	// 32 bytes
42			d-cache-size = <0x8000>;	// L1, 32K
43			i-cache-size = <0x8000>;	// L1, 32K
44			next-level-cache = <&L2>;
45		};
46	};
47
48	memory {
49		device_type = "memory";
50		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
51	};
52
53	soc@e0000000 {
54		#address-cells = <1>;
55		#size-cells = <1>;
56		device_type = "soc";
57		ranges = <0x0 0xe0000000 0x100000>;
58		bus-frequency = <0>;
59		compatible = "fsl,mpc8548-immr", "simple-bus";
60
61		ecm-law@0 {
62			compatible = "fsl,ecm-law";
63			reg = <0x0 0x1000>;
64			fsl,num-laws = <10>;
65		};
66
67		ecm@1000 {
68			compatible = "fsl,mpc8548-ecm", "fsl,ecm";
69			reg = <0x1000 0x1000>;
70			interrupts = <17 2>;
71			interrupt-parent = <&mpic>;
72		};
73
74		memory-controller@2000 {
75			compatible = "fsl,mpc8548-memory-controller";
76			reg = <0x2000 0x1000>;
77			interrupt-parent = <&mpic>;
78			interrupts = <18 2>;
79		};
80
81		L2: l2-cache-controller@20000 {
82			compatible = "fsl,mpc8548-l2-cache-controller";
83			reg = <0x20000 0x1000>;
84			cache-line-size = <32>;	// 32 bytes
85			cache-size = <0x80000>;	// L2, 512K
86			interrupt-parent = <&mpic>;
87			interrupts = <16 2>;
88		};
89
90		i2c@3000 {
91			#address-cells = <1>;
92			#size-cells = <0>;
93			cell-index = <0>;
94			compatible = "fsl-i2c";
95			reg = <0x3000 0x100>;
96			interrupts = <43 2>;
97			interrupt-parent = <&mpic>;
98			dfsrr;
99
100			dtt@48 {
101				compatible = "national,lm75";
102				reg = <0x48>;
103			};
104
105			rtc@68 {
106				compatible = "dallas,ds1337";
107				reg = <0x68>;
108			};
109		};
110
111		i2c@3100 {
112			#address-cells = <1>;
113			#size-cells = <0>;
114			cell-index = <1>;
115			compatible = "fsl-i2c";
116			reg = <0x3100 0x100>;
117			interrupts = <43 2>;
118			interrupt-parent = <&mpic>;
119			dfsrr;
120		};
121
122		dma@21300 {
123			#address-cells = <1>;
124			#size-cells = <1>;
125			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
126			reg = <0x21300 0x4>;
127			ranges = <0x0 0x21100 0x200>;
128			cell-index = <0>;
129			dma-channel@0 {
130				compatible = "fsl,mpc8548-dma-channel",
131						"fsl,eloplus-dma-channel";
132				reg = <0x0 0x80>;
133				cell-index = <0>;
134				interrupt-parent = <&mpic>;
135				interrupts = <20 2>;
136			};
137			dma-channel@80 {
138				compatible = "fsl,mpc8548-dma-channel",
139						"fsl,eloplus-dma-channel";
140				reg = <0x80 0x80>;
141				cell-index = <1>;
142				interrupt-parent = <&mpic>;
143				interrupts = <21 2>;
144			};
145			dma-channel@100 {
146				compatible = "fsl,mpc8548-dma-channel",
147						"fsl,eloplus-dma-channel";
148				reg = <0x100 0x80>;
149				cell-index = <2>;
150				interrupt-parent = <&mpic>;
151				interrupts = <22 2>;
152			};
153			dma-channel@180 {
154				compatible = "fsl,mpc8548-dma-channel",
155						"fsl,eloplus-dma-channel";
156				reg = <0x180 0x80>;
157				cell-index = <3>;
158				interrupt-parent = <&mpic>;
159				interrupts = <23 2>;
160			};
161		};
162
163		enet0: ethernet@24000 {
164			#address-cells = <1>;
165			#size-cells = <1>;
166			cell-index = <0>;
167			device_type = "network";
168			model = "eTSEC";
169			compatible = "gianfar";
170			reg = <0x24000 0x1000>;
171			ranges = <0x0 0x24000 0x1000>;
172			local-mac-address = [ 00 00 00 00 00 00 ];
173			interrupts = <29 2 30 2 34 2>;
174			interrupt-parent = <&mpic>;
175			tbi-handle = <&tbi0>;
176			phy-handle = <&phy2>;
177
178			mdio@520 {
179				#address-cells = <1>;
180				#size-cells = <0>;
181				compatible = "fsl,gianfar-mdio";
182				reg = <0x520 0x20>;
183
184				phy1: ethernet-phy@0 {
185					interrupt-parent = <&mpic>;
186					interrupts = <8 1>;
187					reg = <1>;
188					device_type = "ethernet-phy";
189				};
190				phy2: ethernet-phy@1 {
191					interrupt-parent = <&mpic>;
192					interrupts = <8 1>;
193					reg = <2>;
194					device_type = "ethernet-phy";
195				};
196				phy3: ethernet-phy@3 {
197					interrupt-parent = <&mpic>;
198					interrupts = <8 1>;
199					reg = <3>;
200					device_type = "ethernet-phy";
201				};
202				phy4: ethernet-phy@4 {
203					interrupt-parent = <&mpic>;
204					interrupts = <8 1>;
205					reg = <4>;
206					device_type = "ethernet-phy";
207				};
208				phy5: ethernet-phy@5 {
209					interrupt-parent = <&mpic>;
210					interrupts = <8 1>;
211					reg = <5>;
212					device_type = "ethernet-phy";
213				};
214				tbi0: tbi-phy@11 {
215					reg = <0x11>;
216					device_type = "tbi-phy";
217				};
218			};
219		};
220
221		enet1: ethernet@25000 {
222			#address-cells = <1>;
223			#size-cells = <1>;
224			cell-index = <1>;
225			device_type = "network";
226			model = "eTSEC";
227			compatible = "gianfar";
228			reg = <0x25000 0x1000>;
229			ranges = <0x0 0x25000 0x1000>;
230			local-mac-address = [ 00 00 00 00 00 00 ];
231			interrupts = <35 2 36 2 40 2>;
232			interrupt-parent = <&mpic>;
233			tbi-handle = <&tbi1>;
234			phy-handle = <&phy1>;
235
236			mdio@520 {
237				#address-cells = <1>;
238				#size-cells = <0>;
239				compatible = "fsl,gianfar-tbi";
240				reg = <0x520 0x20>;
241
242				tbi1: tbi-phy@11 {
243					reg = <0x11>;
244					device_type = "tbi-phy";
245				};
246			};
247		};
248
249		enet2: ethernet@26000 {
250			#address-cells = <1>;
251			#size-cells = <1>;
252			cell-index = <2>;
253			device_type = "network";
254			model = "eTSEC";
255			compatible = "gianfar";
256			reg = <0x26000 0x1000>;
257			ranges = <0x0 0x26000 0x1000>;
258			local-mac-address = [ 00 00 00 00 00 00 ];
259			interrupts = <31 2 32 2 33 2>;
260			interrupt-parent = <&mpic>;
261			tbi-handle = <&tbi2>;
262			phy-handle = <&phy4>;
263
264			mdio@520 {
265				#address-cells = <1>;
266				#size-cells = <0>;
267				compatible = "fsl,gianfar-tbi";
268				reg = <0x520 0x20>;
269
270				tbi2: tbi-phy@11 {
271					reg = <0x11>;
272					device_type = "tbi-phy";
273				};
274			};
275		};
276
277		enet3: ethernet@27000 {
278			#address-cells = <1>;
279			#size-cells = <1>;
280			cell-index = <3>;
281			device_type = "network";
282			model = "eTSEC";
283			compatible = "gianfar";
284			reg = <0x27000 0x1000>;
285			ranges = <0x0 0x27000 0x1000>;
286			local-mac-address = [ 00 00 00 00 00 00 ];
287			interrupts = <37 2 38 2 39 2>;
288			interrupt-parent = <&mpic>;
289			tbi-handle = <&tbi3>;
290			phy-handle = <&phy5>;
291
292			mdio@520 {
293				#address-cells = <1>;
294				#size-cells = <0>;
295				compatible = "fsl,gianfar-tbi";
296				reg = <0x520 0x20>;
297
298				tbi3: tbi-phy@11 {
299					reg = <0x11>;
300					device_type = "tbi-phy";
301				};
302			};
303		};
304
305		serial0: serial@4500 {
306			cell-index = <0>;
307			device_type = "serial";
308			compatible = "ns16550";
309			reg = <0x4500 0x100>;	// reg base, size
310			clock-frequency = <0>;	// should we fill in in uboot?
311			current-speed = <115200>;
312			interrupts = <42 2>;
313			interrupt-parent = <&mpic>;
314		};
315
316		serial1: serial@4600 {
317			cell-index = <1>;
318			device_type = "serial";
319			compatible = "ns16550";
320			reg = <0x4600 0x100>;	// reg base, size
321			clock-frequency = <0>;	// should we fill in in uboot?
322			current-speed = <115200>;
323			interrupts = <42 2>;
324			interrupt-parent = <&mpic>;
325		};
326
327		global-utilities@e0000 {	// global utilities reg
328			compatible = "fsl,mpc8548-guts";
329			reg = <0xe0000 0x1000>;
330			fsl,has-rstcr;
331		};
332
333		mpic: pic@40000 {
334			interrupt-controller;
335			#address-cells = <0>;
336			#interrupt-cells = <2>;
337			reg = <0x40000 0x40000>;
338			compatible = "chrp,open-pic";
339			device_type = "open-pic";
340		};
341	};
342
343	localbus@e0005000 {
344		compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
345			     "simple-bus";
346		#address-cells = <2>;
347		#size-cells = <1>;
348		reg = <0xe0005000 0x100>;	// BRx, ORx, etc.
349
350		ranges = <
351			0 0x0 0xfc000000 0x04000000	// NOR FLASH bank 1
352			1 0x0 0xf8000000 0x08000000	// NOR FLASH bank 0
353			2 0x0 0xe3000000 0x00008000	// CAN (2 x i82527)
354			3 0x0 0xe3010000 0x00008000	// NAND FLASH
355
356		>;
357
358		flash@1,0 {
359			#address-cells = <1>;
360			#size-cells = <1>;
361			compatible = "cfi-flash";
362			reg = <1 0x0 0x8000000>;
363			bank-width = <4>;
364			device-width = <1>;
365
366			partition@0 {
367				label = "kernel";
368				reg = <0x00000000 0x00200000>;
369			};
370			partition@200000 {
371				label = "root";
372				reg = <0x00200000 0x00300000>;
373			};
374			partition@500000 {
375				label = "user";
376				reg = <0x00500000 0x07a00000>;
377			};
378			partition@7f00000 {
379				label = "env1";
380				reg = <0x07f00000 0x00040000>;
381			};
382			partition@7f40000 {
383				label = "env2";
384				reg = <0x07f40000 0x00040000>;
385			};
386			partition@7f80000 {
387				label = "u-boot";
388				reg = <0x07f80000 0x00080000>;
389				read-only;
390			};
391		};
392
393		/* Note: CAN support needs be enabled in U-Boot */
394		can0@2,0 {
395			compatible = "intel,82527"; // Bosch CC770
396			reg = <2 0x0 0x100>;
397			interrupts = <4 1>;
398			interrupt-parent = <&mpic>;
399		};
400
401		can1@2,100 {
402			compatible = "intel,82527"; // Bosch CC770
403			reg = <2 0x100 0x100>;
404			interrupts = <4 1>;
405			interrupt-parent = <&mpic>;
406		};
407
408		/* Note: NAND support needs to be enabled in U-Boot */
409		upm@3,0 {
410			#address-cells = <0>;
411			#size-cells = <0>;
412			compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
413			reg = <3 0x0 0x800>;
414			fsl,upm-addr-offset = <0x10>;
415			fsl,upm-cmd-offset = <0x08>;
416			/* Micron MT29F8G08FAB multi-chip device */
417			fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
418			fsl,upm-wait-flags = <0x5>;
419			chip-delay = <25>; // in micro-seconds
420
421			nand@0 {
422				#address-cells = <1>;
423				#size-cells = <1>;
424
425				partition@0 {
426					    label = "fs";
427					    reg = <0x00000000 0x10000000>;
428				};
429			};
430		};
431	};
432
433	pci0: pci@e0008000 {
434		#interrupt-cells = <1>;
435		#size-cells = <2>;
436		#address-cells = <3>;
437		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
438		device_type = "pci";
439		reg = <0xe0008000 0x1000>;
440		clock-frequency = <33333333>;
441		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
442		interrupt-map = <
443				/* IDSEL 28 */
444				 0xe000 0 0 1 &mpic 2 1
445				 0xe000 0 0 2 &mpic 3 1>;
446
447		interrupt-parent = <&mpic>;
448		interrupts = <24 2>;
449		bus-range = <0 0>;
450		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
451			  0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
452	};
453
454	pci1: pcie@e000a000 {
455		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
456		interrupt-map = <
457			/* IDSEL 0x0 (PEX) */
458			0x00000 0 0 1 &mpic 0 1
459			0x00000 0 0 2 &mpic 1 1
460			0x00000 0 0 3 &mpic 2 1
461			0x00000 0 0 4 &mpic 3 1>;
462
463		interrupt-parent = <&mpic>;
464		interrupts = <26 2>;
465		bus-range = <0 0xff>;
466		ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
467			  0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
468		clock-frequency = <33333333>;
469		#interrupt-cells = <1>;
470		#size-cells = <2>;
471		#address-cells = <3>;
472		reg = <0xe000a000 0x1000>;
473		compatible = "fsl,mpc8548-pcie";
474		device_type = "pci";
475		pcie@0 {
476			reg = <0 0 0 0 0>;
477			#size-cells = <2>;
478			#address-cells = <3>;
479			device_type = "pci";
480			ranges = <0x02000000 0 0xc0000000 0x02000000 0
481			          0xc0000000 0 0x20000000
482				  0x01000000 0 0x00000000 0x01000000 0
483				  0x00000000 0 0x08000000>;
484		};
485	};
486};
487