1/*
2 * TQM8548 Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16	model = "tqc,tqm8548";
17	compatible = "tqc,tqm8548";
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	aliases {
22		ethernet0 = &enet0;
23		ethernet1 = &enet1;
24		ethernet2 = &enet2;
25		ethernet3 = &enet3;
26
27		serial0 = &serial0;
28		serial1 = &serial1;
29		pci0 = &pci0;
30		pci1 = &pci1;
31	};
32
33	cpus {
34		#address-cells = <1>;
35		#size-cells = <0>;
36
37		PowerPC,8548@0 {
38			device_type = "cpu";
39			reg = <0>;
40			d-cache-line-size = <32>;	// 32 bytes
41			i-cache-line-size = <32>;	// 32 bytes
42			d-cache-size = <0x8000>;	// L1, 32K
43			i-cache-size = <0x8000>;	// L1, 32K
44			next-level-cache = <&L2>;
45		};
46	};
47
48	memory {
49		device_type = "memory";
50		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
51	};
52
53	soc@e0000000 {
54		#address-cells = <1>;
55		#size-cells = <1>;
56		device_type = "soc";
57		ranges = <0x0 0xe0000000 0x100000>;
58		reg = <0xe0000000 0x1000>;	// CCSRBAR
59		bus-frequency = <0>;
60		compatible = "fsl,mpc8548-immr", "simple-bus";
61
62		memory-controller@2000 {
63			compatible = "fsl,mpc8548-memory-controller";
64			reg = <0x2000 0x1000>;
65			interrupt-parent = <&mpic>;
66			interrupts = <18 2>;
67		};
68
69		L2: l2-cache-controller@20000 {
70			compatible = "fsl,mpc8548-l2-cache-controller";
71			reg = <0x20000 0x1000>;
72			cache-line-size = <32>;	// 32 bytes
73			cache-size = <0x80000>;	// L2, 512K
74			interrupt-parent = <&mpic>;
75			interrupts = <16 2>;
76		};
77
78		i2c@3000 {
79			#address-cells = <1>;
80			#size-cells = <0>;
81			cell-index = <0>;
82			compatible = "fsl-i2c";
83			reg = <0x3000 0x100>;
84			interrupts = <43 2>;
85			interrupt-parent = <&mpic>;
86			dfsrr;
87
88			dtt@48 {
89				compatible = "national,lm75";
90				reg = <0x48>;
91			};
92
93			rtc@68 {
94				compatible = "dallas,ds1337";
95				reg = <0x68>;
96			};
97		};
98
99		i2c@3100 {
100			#address-cells = <1>;
101			#size-cells = <0>;
102			cell-index = <1>;
103			compatible = "fsl-i2c";
104			reg = <0x3100 0x100>;
105			interrupts = <43 2>;
106			interrupt-parent = <&mpic>;
107			dfsrr;
108		};
109
110		dma@21300 {
111			#address-cells = <1>;
112			#size-cells = <1>;
113			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
114			reg = <0x21300 0x4>;
115			ranges = <0x0 0x21100 0x200>;
116			cell-index = <0>;
117			dma-channel@0 {
118				compatible = "fsl,mpc8548-dma-channel",
119						"fsl,eloplus-dma-channel";
120				reg = <0x0 0x80>;
121				cell-index = <0>;
122				interrupt-parent = <&mpic>;
123				interrupts = <20 2>;
124			};
125			dma-channel@80 {
126				compatible = "fsl,mpc8548-dma-channel",
127						"fsl,eloplus-dma-channel";
128				reg = <0x80 0x80>;
129				cell-index = <1>;
130				interrupt-parent = <&mpic>;
131				interrupts = <21 2>;
132			};
133			dma-channel@100 {
134				compatible = "fsl,mpc8548-dma-channel",
135						"fsl,eloplus-dma-channel";
136				reg = <0x100 0x80>;
137				cell-index = <2>;
138				interrupt-parent = <&mpic>;
139				interrupts = <22 2>;
140			};
141			dma-channel@180 {
142				compatible = "fsl,mpc8548-dma-channel",
143						"fsl,eloplus-dma-channel";
144				reg = <0x180 0x80>;
145				cell-index = <3>;
146				interrupt-parent = <&mpic>;
147				interrupts = <23 2>;
148			};
149		};
150
151		enet0: ethernet@24000 {
152			#address-cells = <1>;
153			#size-cells = <1>;
154			cell-index = <0>;
155			device_type = "network";
156			model = "eTSEC";
157			compatible = "gianfar";
158			reg = <0x24000 0x1000>;
159			ranges = <0x0 0x24000 0x1000>;
160			local-mac-address = [ 00 00 00 00 00 00 ];
161			interrupts = <29 2 30 2 34 2>;
162			interrupt-parent = <&mpic>;
163			tbi-handle = <&tbi0>;
164			phy-handle = <&phy2>;
165
166			mdio@520 {
167				#address-cells = <1>;
168				#size-cells = <0>;
169				compatible = "fsl,gianfar-mdio";
170				reg = <0x520 0x20>;
171
172				phy1: ethernet-phy@0 {
173					interrupt-parent = <&mpic>;
174					interrupts = <8 1>;
175					reg = <1>;
176					device_type = "ethernet-phy";
177				};
178				phy2: ethernet-phy@1 {
179					interrupt-parent = <&mpic>;
180					interrupts = <8 1>;
181					reg = <2>;
182					device_type = "ethernet-phy";
183				};
184				phy3: ethernet-phy@3 {
185					interrupt-parent = <&mpic>;
186					interrupts = <8 1>;
187					reg = <3>;
188					device_type = "ethernet-phy";
189				};
190				phy4: ethernet-phy@4 {
191					interrupt-parent = <&mpic>;
192					interrupts = <8 1>;
193					reg = <4>;
194					device_type = "ethernet-phy";
195				};
196				phy5: ethernet-phy@5 {
197					interrupt-parent = <&mpic>;
198					interrupts = <8 1>;
199					reg = <5>;
200					device_type = "ethernet-phy";
201				};
202				tbi0: tbi-phy@11 {
203					reg = <0x11>;
204					device_type = "tbi-phy";
205				};
206			};
207		};
208
209		enet1: ethernet@25000 {
210			#address-cells = <1>;
211			#size-cells = <1>;
212			cell-index = <1>;
213			device_type = "network";
214			model = "eTSEC";
215			compatible = "gianfar";
216			reg = <0x25000 0x1000>;
217			ranges = <0x0 0x25000 0x1000>;
218			local-mac-address = [ 00 00 00 00 00 00 ];
219			interrupts = <35 2 36 2 40 2>;
220			interrupt-parent = <&mpic>;
221			tbi-handle = <&tbi1>;
222			phy-handle = <&phy1>;
223
224			mdio@520 {
225				#address-cells = <1>;
226				#size-cells = <0>;
227				compatible = "fsl,gianfar-tbi";
228				reg = <0x520 0x20>;
229
230				tbi1: tbi-phy@11 {
231					reg = <0x11>;
232					device_type = "tbi-phy";
233				};
234			};
235		};
236
237		enet2: ethernet@26000 {
238			#address-cells = <1>;
239			#size-cells = <1>;
240			cell-index = <2>;
241			device_type = "network";
242			model = "eTSEC";
243			compatible = "gianfar";
244			reg = <0x26000 0x1000>;
245			ranges = <0x0 0x26000 0x1000>;
246			local-mac-address = [ 00 00 00 00 00 00 ];
247			interrupts = <31 2 32 2 33 2>;
248			interrupt-parent = <&mpic>;
249			tbi-handle = <&tbi2>;
250			phy-handle = <&phy4>;
251
252			mdio@520 {
253				#address-cells = <1>;
254				#size-cells = <0>;
255				compatible = "fsl,gianfar-tbi";
256				reg = <0x520 0x20>;
257
258				tbi2: tbi-phy@11 {
259					reg = <0x11>;
260					device_type = "tbi-phy";
261				};
262			};
263		};
264
265		enet3: ethernet@27000 {
266			#address-cells = <1>;
267			#size-cells = <1>;
268			cell-index = <3>;
269			device_type = "network";
270			model = "eTSEC";
271			compatible = "gianfar";
272			reg = <0x27000 0x1000>;
273			ranges = <0x0 0x27000 0x1000>;
274			local-mac-address = [ 00 00 00 00 00 00 ];
275			interrupts = <37 2 38 2 39 2>;
276			interrupt-parent = <&mpic>;
277			tbi-handle = <&tbi3>;
278			phy-handle = <&phy5>;
279
280			mdio@520 {
281				#address-cells = <1>;
282				#size-cells = <0>;
283				compatible = "fsl,gianfar-tbi";
284				reg = <0x520 0x20>;
285
286				tbi3: tbi-phy@11 {
287					reg = <0x11>;
288					device_type = "tbi-phy";
289				};
290			};
291		};
292
293		serial0: serial@4500 {
294			cell-index = <0>;
295			device_type = "serial";
296			compatible = "ns16550";
297			reg = <0x4500 0x100>;	// reg base, size
298			clock-frequency = <0>;	// should we fill in in uboot?
299			current-speed = <115200>;
300			interrupts = <42 2>;
301			interrupt-parent = <&mpic>;
302		};
303
304		serial1: serial@4600 {
305			cell-index = <1>;
306			device_type = "serial";
307			compatible = "ns16550";
308			reg = <0x4600 0x100>;	// reg base, size
309			clock-frequency = <0>;	// should we fill in in uboot?
310			current-speed = <115200>;
311			interrupts = <42 2>;
312			interrupt-parent = <&mpic>;
313		};
314
315		global-utilities@e0000 {	// global utilities reg
316			compatible = "fsl,mpc8548-guts";
317			reg = <0xe0000 0x1000>;
318			fsl,has-rstcr;
319		};
320
321		mpic: pic@40000 {
322			interrupt-controller;
323			#address-cells = <0>;
324			#interrupt-cells = <2>;
325			reg = <0x40000 0x40000>;
326			compatible = "chrp,open-pic";
327			device_type = "open-pic";
328		};
329	};
330
331	localbus@e0005000 {
332		compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
333			     "simple-bus";
334		#address-cells = <2>;
335		#size-cells = <1>;
336		reg = <0xe0005000 0x100>;	// BRx, ORx, etc.
337
338		ranges = <
339			0 0x0 0xfc000000 0x04000000	// NOR FLASH bank 1
340			1 0x0 0xf8000000 0x08000000	// NOR FLASH bank 0
341			2 0x0 0xe3000000 0x00008000	// CAN (2 x i82527)
342			3 0x0 0xe3010000 0x00008000	// NAND FLASH
343
344		>;
345
346		flash@1,0 {
347			#address-cells = <1>;
348			#size-cells = <1>;
349			compatible = "cfi-flash";
350			reg = <1 0x0 0x8000000>;
351			bank-width = <4>;
352			device-width = <1>;
353
354			partition@0 {
355				label = "kernel";
356				reg = <0x00000000 0x00200000>;
357			};
358			partition@200000 {
359				label = "root";
360				reg = <0x00200000 0x00300000>;
361			};
362			partition@500000 {
363				label = "user";
364				reg = <0x00500000 0x07a00000>;
365			};
366			partition@7f00000 {
367				label = "env1";
368				reg = <0x07f00000 0x00040000>;
369			};
370			partition@7f40000 {
371				label = "env2";
372				reg = <0x07f40000 0x00040000>;
373			};
374			partition@7f80000 {
375				label = "u-boot";
376				reg = <0x07f80000 0x00080000>;
377				read-only;
378			};
379		};
380
381		/* Note: CAN support needs be enabled in U-Boot */
382		can0@2,0 {
383			compatible = "intel,82527"; // Bosch CC770
384			reg = <2 0x0 0x100>;
385			interrupts = <4 1>;
386			interrupt-parent = <&mpic>;
387		};
388
389		can1@2,100 {
390			compatible = "intel,82527"; // Bosch CC770
391			reg = <2 0x100 0x100>;
392			interrupts = <4 1>;
393			interrupt-parent = <&mpic>;
394		};
395
396		/* Note: NAND support needs to be enabled in U-Boot */
397		upm@3,0 {
398			#address-cells = <0>;
399			#size-cells = <0>;
400			compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
401			reg = <3 0x0 0x800>;
402			fsl,upm-addr-offset = <0x10>;
403			fsl,upm-cmd-offset = <0x08>;
404			/* Micron MT29F8G08FAB multi-chip device */
405			fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
406			fsl,upm-wait-flags = <0x5>;
407			chip-delay = <25>; // in micro-seconds
408
409			nand@0 {
410				#address-cells = <1>;
411				#size-cells = <1>;
412
413				partition@0 {
414					    label = "fs";
415					    reg = <0x00000000 0x10000000>;
416				};
417			};
418		};
419	};
420
421	pci0: pci@e0008000 {
422		cell-index = <0>;
423		#interrupt-cells = <1>;
424		#size-cells = <2>;
425		#address-cells = <3>;
426		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
427		device_type = "pci";
428		reg = <0xe0008000 0x1000>;
429		clock-frequency = <33333333>;
430		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
431		interrupt-map = <
432				/* IDSEL 28 */
433				 0xe000 0 0 1 &mpic 2 1
434				 0xe000 0 0 2 &mpic 3 1>;
435
436		interrupt-parent = <&mpic>;
437		interrupts = <24 2>;
438		bus-range = <0 0>;
439		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
440			  0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
441	};
442
443	pci1: pcie@e000a000 {
444		cell-index = <2>;
445		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
446		interrupt-map = <
447			/* IDSEL 0x0 (PEX) */
448			0x00000 0 0 1 &mpic 0 1
449			0x00000 0 0 2 &mpic 1 1
450			0x00000 0 0 3 &mpic 2 1
451			0x00000 0 0 4 &mpic 3 1>;
452
453		interrupt-parent = <&mpic>;
454		interrupts = <26 2>;
455		bus-range = <0 0xff>;
456		ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
457			  0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
458		clock-frequency = <33333333>;
459		#interrupt-cells = <1>;
460		#size-cells = <2>;
461		#address-cells = <3>;
462		reg = <0xe000a000 0x1000>;
463		compatible = "fsl,mpc8548-pcie";
464		device_type = "pci";
465		pcie@0 {
466			reg = <0 0 0 0 0>;
467			#size-cells = <2>;
468			#address-cells = <3>;
469			device_type = "pci";
470			ranges = <0x02000000 0 0xc0000000 0x02000000 0
471			          0xc0000000 0 0x20000000
472				  0x01000000 0 0x00000000 0x01000000 0
473				  0x00000000 0 0x08000000>;
474		};
475	};
476};
477