16dd1b64aSWolfgang Grandegger/* 26dd1b64aSWolfgang Grandegger * TQM8548 Device Tree Source 36dd1b64aSWolfgang Grandegger * 46dd1b64aSWolfgang Grandegger * Copyright 2006 Freescale Semiconductor Inc. 56dd1b64aSWolfgang Grandegger * Copyright 2008 Wolfgang Grandegger <wg@denx.de> 66dd1b64aSWolfgang Grandegger * 76dd1b64aSWolfgang Grandegger * This program is free software; you can redistribute it and/or modify it 86dd1b64aSWolfgang Grandegger * under the terms of the GNU General Public License as published by the 96dd1b64aSWolfgang Grandegger * Free Software Foundation; either version 2 of the License, or (at your 106dd1b64aSWolfgang Grandegger * option) any later version. 116dd1b64aSWolfgang Grandegger */ 126dd1b64aSWolfgang Grandegger 136dd1b64aSWolfgang Grandegger/dts-v1/; 146dd1b64aSWolfgang Grandegger 156dd1b64aSWolfgang Grandegger/ { 166dd1b64aSWolfgang Grandegger model = "tqc,tqm8548"; 176dd1b64aSWolfgang Grandegger compatible = "tqc,tqm8548"; 186dd1b64aSWolfgang Grandegger #address-cells = <1>; 196dd1b64aSWolfgang Grandegger #size-cells = <1>; 206dd1b64aSWolfgang Grandegger 216dd1b64aSWolfgang Grandegger aliases { 226dd1b64aSWolfgang Grandegger ethernet0 = &enet0; 236dd1b64aSWolfgang Grandegger ethernet1 = &enet1; 246dd1b64aSWolfgang Grandegger ethernet2 = &enet2; 256dd1b64aSWolfgang Grandegger ethernet3 = &enet3; 266dd1b64aSWolfgang Grandegger 276dd1b64aSWolfgang Grandegger serial0 = &serial0; 286dd1b64aSWolfgang Grandegger serial1 = &serial1; 296dd1b64aSWolfgang Grandegger pci0 = &pci0; 306dd1b64aSWolfgang Grandegger pci1 = &pci1; 316dd1b64aSWolfgang Grandegger }; 326dd1b64aSWolfgang Grandegger 336dd1b64aSWolfgang Grandegger cpus { 346dd1b64aSWolfgang Grandegger #address-cells = <1>; 356dd1b64aSWolfgang Grandegger #size-cells = <0>; 366dd1b64aSWolfgang Grandegger 376dd1b64aSWolfgang Grandegger PowerPC,8548@0 { 386dd1b64aSWolfgang Grandegger device_type = "cpu"; 396dd1b64aSWolfgang Grandegger reg = <0>; 406dd1b64aSWolfgang Grandegger d-cache-line-size = <32>; // 32 bytes 416dd1b64aSWolfgang Grandegger i-cache-line-size = <32>; // 32 bytes 426dd1b64aSWolfgang Grandegger d-cache-size = <0x8000>; // L1, 32K 436dd1b64aSWolfgang Grandegger i-cache-size = <0x8000>; // L1, 32K 446dd1b64aSWolfgang Grandegger next-level-cache = <&L2>; 456dd1b64aSWolfgang Grandegger }; 466dd1b64aSWolfgang Grandegger }; 476dd1b64aSWolfgang Grandegger 486dd1b64aSWolfgang Grandegger memory { 496dd1b64aSWolfgang Grandegger device_type = "memory"; 506dd1b64aSWolfgang Grandegger reg = <0x00000000 0x00000000>; // Filled in by U-Boot 516dd1b64aSWolfgang Grandegger }; 526dd1b64aSWolfgang Grandegger 53d27a736cSWolfgang Grandegger soc@e0000000 { 546dd1b64aSWolfgang Grandegger #address-cells = <1>; 556dd1b64aSWolfgang Grandegger #size-cells = <1>; 566dd1b64aSWolfgang Grandegger device_type = "soc"; 576dd1b64aSWolfgang Grandegger ranges = <0x0 0xe0000000 0x100000>; 586dd1b64aSWolfgang Grandegger reg = <0xe0000000 0x1000>; // CCSRBAR 596dd1b64aSWolfgang Grandegger bus-frequency = <0>; 60d27a736cSWolfgang Grandegger compatible = "fsl,mpc8548-immr", "simple-bus"; 616dd1b64aSWolfgang Grandegger 62e1a22897SKumar Gala ecm-law@0 { 63e1a22897SKumar Gala compatible = "fsl,ecm-law"; 64e1a22897SKumar Gala reg = <0x0 0x1000>; 65e1a22897SKumar Gala fsl,num-laws = <10>; 66e1a22897SKumar Gala }; 67e1a22897SKumar Gala 68e1a22897SKumar Gala ecm@1000 { 69e1a22897SKumar Gala compatible = "fsl,mpc8548-ecm", "fsl,ecm"; 70e1a22897SKumar Gala reg = <0x1000 0x1000>; 71e1a22897SKumar Gala interrupts = <17 2>; 72e1a22897SKumar Gala interrupt-parent = <&mpic>; 73e1a22897SKumar Gala }; 74e1a22897SKumar Gala 756dd1b64aSWolfgang Grandegger memory-controller@2000 { 766dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-memory-controller"; 776dd1b64aSWolfgang Grandegger reg = <0x2000 0x1000>; 786dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 796dd1b64aSWolfgang Grandegger interrupts = <18 2>; 806dd1b64aSWolfgang Grandegger }; 816dd1b64aSWolfgang Grandegger 826dd1b64aSWolfgang Grandegger L2: l2-cache-controller@20000 { 836dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-l2-cache-controller"; 846dd1b64aSWolfgang Grandegger reg = <0x20000 0x1000>; 856dd1b64aSWolfgang Grandegger cache-line-size = <32>; // 32 bytes 866dd1b64aSWolfgang Grandegger cache-size = <0x80000>; // L2, 512K 876dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 886dd1b64aSWolfgang Grandegger interrupts = <16 2>; 896dd1b64aSWolfgang Grandegger }; 906dd1b64aSWolfgang Grandegger 916dd1b64aSWolfgang Grandegger i2c@3000 { 926dd1b64aSWolfgang Grandegger #address-cells = <1>; 936dd1b64aSWolfgang Grandegger #size-cells = <0>; 946dd1b64aSWolfgang Grandegger cell-index = <0>; 956dd1b64aSWolfgang Grandegger compatible = "fsl-i2c"; 966dd1b64aSWolfgang Grandegger reg = <0x3000 0x100>; 976dd1b64aSWolfgang Grandegger interrupts = <43 2>; 986dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 996dd1b64aSWolfgang Grandegger dfsrr; 100a3083220SWolfgang Grandegger 1016467cae3SWolfgang Grandegger dtt@48 { 1020f73a449SWolfgang Grandegger compatible = "national,lm75"; 1036467cae3SWolfgang Grandegger reg = <0x48>; 1040f73a449SWolfgang Grandegger }; 1050f73a449SWolfgang Grandegger 106a3083220SWolfgang Grandegger rtc@68 { 107a3083220SWolfgang Grandegger compatible = "dallas,ds1337"; 108a3083220SWolfgang Grandegger reg = <0x68>; 109a3083220SWolfgang Grandegger }; 1106dd1b64aSWolfgang Grandegger }; 1116dd1b64aSWolfgang Grandegger 1126dd1b64aSWolfgang Grandegger i2c@3100 { 1136dd1b64aSWolfgang Grandegger #address-cells = <1>; 1146dd1b64aSWolfgang Grandegger #size-cells = <0>; 1156dd1b64aSWolfgang Grandegger cell-index = <1>; 1166dd1b64aSWolfgang Grandegger compatible = "fsl-i2c"; 1176dd1b64aSWolfgang Grandegger reg = <0x3100 0x100>; 1186dd1b64aSWolfgang Grandegger interrupts = <43 2>; 1196dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1206dd1b64aSWolfgang Grandegger dfsrr; 1216dd1b64aSWolfgang Grandegger }; 1226dd1b64aSWolfgang Grandegger 123dee80553SKumar Gala dma@21300 { 124dee80553SKumar Gala #address-cells = <1>; 125dee80553SKumar Gala #size-cells = <1>; 126dee80553SKumar Gala compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 127dee80553SKumar Gala reg = <0x21300 0x4>; 128dee80553SKumar Gala ranges = <0x0 0x21100 0x200>; 129dee80553SKumar Gala cell-index = <0>; 130dee80553SKumar Gala dma-channel@0 { 131dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 132dee80553SKumar Gala "fsl,eloplus-dma-channel"; 133dee80553SKumar Gala reg = <0x0 0x80>; 134dee80553SKumar Gala cell-index = <0>; 135dee80553SKumar Gala interrupt-parent = <&mpic>; 136dee80553SKumar Gala interrupts = <20 2>; 137dee80553SKumar Gala }; 138dee80553SKumar Gala dma-channel@80 { 139dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 140dee80553SKumar Gala "fsl,eloplus-dma-channel"; 141dee80553SKumar Gala reg = <0x80 0x80>; 142dee80553SKumar Gala cell-index = <1>; 143dee80553SKumar Gala interrupt-parent = <&mpic>; 144dee80553SKumar Gala interrupts = <21 2>; 145dee80553SKumar Gala }; 146dee80553SKumar Gala dma-channel@100 { 147dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 148dee80553SKumar Gala "fsl,eloplus-dma-channel"; 149dee80553SKumar Gala reg = <0x100 0x80>; 150dee80553SKumar Gala cell-index = <2>; 151dee80553SKumar Gala interrupt-parent = <&mpic>; 152dee80553SKumar Gala interrupts = <22 2>; 153dee80553SKumar Gala }; 154dee80553SKumar Gala dma-channel@180 { 155dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 156dee80553SKumar Gala "fsl,eloplus-dma-channel"; 157dee80553SKumar Gala reg = <0x180 0x80>; 158dee80553SKumar Gala cell-index = <3>; 159dee80553SKumar Gala interrupt-parent = <&mpic>; 160dee80553SKumar Gala interrupts = <23 2>; 161dee80553SKumar Gala }; 162dee80553SKumar Gala }; 163dee80553SKumar Gala 16484ba4a58SAnton Vorontsov enet0: ethernet@24000 { 16584ba4a58SAnton Vorontsov #address-cells = <1>; 16684ba4a58SAnton Vorontsov #size-cells = <1>; 16784ba4a58SAnton Vorontsov cell-index = <0>; 16884ba4a58SAnton Vorontsov device_type = "network"; 16984ba4a58SAnton Vorontsov model = "eTSEC"; 17084ba4a58SAnton Vorontsov compatible = "gianfar"; 17184ba4a58SAnton Vorontsov reg = <0x24000 0x1000>; 17284ba4a58SAnton Vorontsov ranges = <0x0 0x24000 0x1000>; 17384ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 17484ba4a58SAnton Vorontsov interrupts = <29 2 30 2 34 2>; 17584ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 17684ba4a58SAnton Vorontsov tbi-handle = <&tbi0>; 17784ba4a58SAnton Vorontsov phy-handle = <&phy2>; 17884ba4a58SAnton Vorontsov 17984ba4a58SAnton Vorontsov mdio@520 { 1806dd1b64aSWolfgang Grandegger #address-cells = <1>; 1816dd1b64aSWolfgang Grandegger #size-cells = <0>; 1826dd1b64aSWolfgang Grandegger compatible = "fsl,gianfar-mdio"; 18384ba4a58SAnton Vorontsov reg = <0x520 0x20>; 1846dd1b64aSWolfgang Grandegger 1856dd1b64aSWolfgang Grandegger phy1: ethernet-phy@0 { 1866dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1876dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1886dd1b64aSWolfgang Grandegger reg = <1>; 1896dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1906dd1b64aSWolfgang Grandegger }; 1916dd1b64aSWolfgang Grandegger phy2: ethernet-phy@1 { 1926dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1936dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1946dd1b64aSWolfgang Grandegger reg = <2>; 1956dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1966dd1b64aSWolfgang Grandegger }; 1976dd1b64aSWolfgang Grandegger phy3: ethernet-phy@3 { 1986dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1996dd1b64aSWolfgang Grandegger interrupts = <8 1>; 2006dd1b64aSWolfgang Grandegger reg = <3>; 2016dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 2026dd1b64aSWolfgang Grandegger }; 2036dd1b64aSWolfgang Grandegger phy4: ethernet-phy@4 { 2046dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 2056dd1b64aSWolfgang Grandegger interrupts = <8 1>; 2066dd1b64aSWolfgang Grandegger reg = <4>; 2076dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 2086dd1b64aSWolfgang Grandegger }; 2096dd1b64aSWolfgang Grandegger phy5: ethernet-phy@5 { 2106dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 2116dd1b64aSWolfgang Grandegger interrupts = <8 1>; 2126dd1b64aSWolfgang Grandegger reg = <5>; 2136dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 2146dd1b64aSWolfgang Grandegger }; 215b31a1d8bSAndy Fleming tbi0: tbi-phy@11 { 216b31a1d8bSAndy Fleming reg = <0x11>; 217b31a1d8bSAndy Fleming device_type = "tbi-phy"; 218b31a1d8bSAndy Fleming }; 219b31a1d8bSAndy Fleming }; 22084ba4a58SAnton Vorontsov }; 221b31a1d8bSAndy Fleming 22284ba4a58SAnton Vorontsov enet1: ethernet@25000 { 22384ba4a58SAnton Vorontsov #address-cells = <1>; 22484ba4a58SAnton Vorontsov #size-cells = <1>; 22584ba4a58SAnton Vorontsov cell-index = <1>; 22684ba4a58SAnton Vorontsov device_type = "network"; 22784ba4a58SAnton Vorontsov model = "eTSEC"; 22884ba4a58SAnton Vorontsov compatible = "gianfar"; 22984ba4a58SAnton Vorontsov reg = <0x25000 0x1000>; 23084ba4a58SAnton Vorontsov ranges = <0x0 0x25000 0x1000>; 23184ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 23284ba4a58SAnton Vorontsov interrupts = <35 2 36 2 40 2>; 23384ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 23484ba4a58SAnton Vorontsov tbi-handle = <&tbi1>; 23584ba4a58SAnton Vorontsov phy-handle = <&phy1>; 23684ba4a58SAnton Vorontsov 23784ba4a58SAnton Vorontsov mdio@520 { 238b31a1d8bSAndy Fleming #address-cells = <1>; 239b31a1d8bSAndy Fleming #size-cells = <0>; 240b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 24184ba4a58SAnton Vorontsov reg = <0x520 0x20>; 242b31a1d8bSAndy Fleming 243b31a1d8bSAndy Fleming tbi1: tbi-phy@11 { 244b31a1d8bSAndy Fleming reg = <0x11>; 245b31a1d8bSAndy Fleming device_type = "tbi-phy"; 246b31a1d8bSAndy Fleming }; 247b31a1d8bSAndy Fleming }; 24884ba4a58SAnton Vorontsov }; 249b31a1d8bSAndy Fleming 25084ba4a58SAnton Vorontsov enet2: ethernet@26000 { 25184ba4a58SAnton Vorontsov #address-cells = <1>; 25284ba4a58SAnton Vorontsov #size-cells = <1>; 25384ba4a58SAnton Vorontsov cell-index = <2>; 25484ba4a58SAnton Vorontsov device_type = "network"; 25584ba4a58SAnton Vorontsov model = "eTSEC"; 25684ba4a58SAnton Vorontsov compatible = "gianfar"; 25784ba4a58SAnton Vorontsov reg = <0x26000 0x1000>; 25884ba4a58SAnton Vorontsov ranges = <0x0 0x26000 0x1000>; 25984ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 26084ba4a58SAnton Vorontsov interrupts = <31 2 32 2 33 2>; 26184ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 26284ba4a58SAnton Vorontsov tbi-handle = <&tbi2>; 263655544c6SWolfgang Grandegger phy-handle = <&phy4>; 26484ba4a58SAnton Vorontsov 26584ba4a58SAnton Vorontsov mdio@520 { 266b31a1d8bSAndy Fleming #address-cells = <1>; 267b31a1d8bSAndy Fleming #size-cells = <0>; 268b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 26984ba4a58SAnton Vorontsov reg = <0x520 0x20>; 270b31a1d8bSAndy Fleming 271b31a1d8bSAndy Fleming tbi2: tbi-phy@11 { 272b31a1d8bSAndy Fleming reg = <0x11>; 273b31a1d8bSAndy Fleming device_type = "tbi-phy"; 274b31a1d8bSAndy Fleming }; 275b31a1d8bSAndy Fleming }; 27684ba4a58SAnton Vorontsov }; 277b31a1d8bSAndy Fleming 27884ba4a58SAnton Vorontsov enet3: ethernet@27000 { 27984ba4a58SAnton Vorontsov #address-cells = <1>; 28084ba4a58SAnton Vorontsov #size-cells = <1>; 28184ba4a58SAnton Vorontsov cell-index = <3>; 28284ba4a58SAnton Vorontsov device_type = "network"; 28384ba4a58SAnton Vorontsov model = "eTSEC"; 28484ba4a58SAnton Vorontsov compatible = "gianfar"; 28584ba4a58SAnton Vorontsov reg = <0x27000 0x1000>; 28684ba4a58SAnton Vorontsov ranges = <0x0 0x27000 0x1000>; 28784ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 28884ba4a58SAnton Vorontsov interrupts = <37 2 38 2 39 2>; 28984ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 29084ba4a58SAnton Vorontsov tbi-handle = <&tbi3>; 291655544c6SWolfgang Grandegger phy-handle = <&phy5>; 29284ba4a58SAnton Vorontsov 29384ba4a58SAnton Vorontsov mdio@520 { 294b31a1d8bSAndy Fleming #address-cells = <1>; 295b31a1d8bSAndy Fleming #size-cells = <0>; 296b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 29784ba4a58SAnton Vorontsov reg = <0x520 0x20>; 298b31a1d8bSAndy Fleming 299b31a1d8bSAndy Fleming tbi3: tbi-phy@11 { 300b31a1d8bSAndy Fleming reg = <0x11>; 301b31a1d8bSAndy Fleming device_type = "tbi-phy"; 302b31a1d8bSAndy Fleming }; 3036dd1b64aSWolfgang Grandegger }; 3046dd1b64aSWolfgang Grandegger }; 3056dd1b64aSWolfgang Grandegger 3066dd1b64aSWolfgang Grandegger serial0: serial@4500 { 3076dd1b64aSWolfgang Grandegger cell-index = <0>; 3086dd1b64aSWolfgang Grandegger device_type = "serial"; 3096dd1b64aSWolfgang Grandegger compatible = "ns16550"; 3106dd1b64aSWolfgang Grandegger reg = <0x4500 0x100>; // reg base, size 3116dd1b64aSWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 3126dd1b64aSWolfgang Grandegger current-speed = <115200>; 3136dd1b64aSWolfgang Grandegger interrupts = <42 2>; 3146dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 3156dd1b64aSWolfgang Grandegger }; 3166dd1b64aSWolfgang Grandegger 3176dd1b64aSWolfgang Grandegger serial1: serial@4600 { 3186dd1b64aSWolfgang Grandegger cell-index = <1>; 3196dd1b64aSWolfgang Grandegger device_type = "serial"; 3206dd1b64aSWolfgang Grandegger compatible = "ns16550"; 3216dd1b64aSWolfgang Grandegger reg = <0x4600 0x100>; // reg base, size 3226dd1b64aSWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 3236dd1b64aSWolfgang Grandegger current-speed = <115200>; 3246dd1b64aSWolfgang Grandegger interrupts = <42 2>; 3256dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 3266dd1b64aSWolfgang Grandegger }; 3276dd1b64aSWolfgang Grandegger 3286dd1b64aSWolfgang Grandegger global-utilities@e0000 { // global utilities reg 3296dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-guts"; 3306dd1b64aSWolfgang Grandegger reg = <0xe0000 0x1000>; 3316dd1b64aSWolfgang Grandegger fsl,has-rstcr; 3326dd1b64aSWolfgang Grandegger }; 3336dd1b64aSWolfgang Grandegger 3346dd1b64aSWolfgang Grandegger mpic: pic@40000 { 3356dd1b64aSWolfgang Grandegger interrupt-controller; 3366dd1b64aSWolfgang Grandegger #address-cells = <0>; 3376dd1b64aSWolfgang Grandegger #interrupt-cells = <2>; 3386dd1b64aSWolfgang Grandegger reg = <0x40000 0x40000>; 3396dd1b64aSWolfgang Grandegger compatible = "chrp,open-pic"; 3406dd1b64aSWolfgang Grandegger device_type = "open-pic"; 3416dd1b64aSWolfgang Grandegger }; 3426dd1b64aSWolfgang Grandegger }; 3436dd1b64aSWolfgang Grandegger 3446dd1b64aSWolfgang Grandegger localbus@e0005000 { 3456dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 3466dd1b64aSWolfgang Grandegger "simple-bus"; 3476dd1b64aSWolfgang Grandegger #address-cells = <2>; 3486dd1b64aSWolfgang Grandegger #size-cells = <1>; 3496dd1b64aSWolfgang Grandegger reg = <0xe0005000 0x100>; // BRx, ORx, etc. 3506dd1b64aSWolfgang Grandegger 3516dd1b64aSWolfgang Grandegger ranges = < 3526dd1b64aSWolfgang Grandegger 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 3536dd1b64aSWolfgang Grandegger 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 3546dd1b64aSWolfgang Grandegger 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) 3556dd1b64aSWolfgang Grandegger 3 0x0 0xe3010000 0x00008000 // NAND FLASH 3566dd1b64aSWolfgang Grandegger 3576dd1b64aSWolfgang Grandegger >; 3586dd1b64aSWolfgang Grandegger 3596dd1b64aSWolfgang Grandegger flash@1,0 { 3606dd1b64aSWolfgang Grandegger #address-cells = <1>; 3616dd1b64aSWolfgang Grandegger #size-cells = <1>; 3626dd1b64aSWolfgang Grandegger compatible = "cfi-flash"; 3636dd1b64aSWolfgang Grandegger reg = <1 0x0 0x8000000>; 3646dd1b64aSWolfgang Grandegger bank-width = <4>; 3656dd1b64aSWolfgang Grandegger device-width = <1>; 3666dd1b64aSWolfgang Grandegger 3676dd1b64aSWolfgang Grandegger partition@0 { 3686dd1b64aSWolfgang Grandegger label = "kernel"; 3696dd1b64aSWolfgang Grandegger reg = <0x00000000 0x00200000>; 3706dd1b64aSWolfgang Grandegger }; 3716dd1b64aSWolfgang Grandegger partition@200000 { 3726dd1b64aSWolfgang Grandegger label = "root"; 3736dd1b64aSWolfgang Grandegger reg = <0x00200000 0x00300000>; 3746dd1b64aSWolfgang Grandegger }; 3756dd1b64aSWolfgang Grandegger partition@500000 { 3766dd1b64aSWolfgang Grandegger label = "user"; 3776dd1b64aSWolfgang Grandegger reg = <0x00500000 0x07a00000>; 3786dd1b64aSWolfgang Grandegger }; 3796dd1b64aSWolfgang Grandegger partition@7f00000 { 3806dd1b64aSWolfgang Grandegger label = "env1"; 3816dd1b64aSWolfgang Grandegger reg = <0x07f00000 0x00040000>; 3826dd1b64aSWolfgang Grandegger }; 3836dd1b64aSWolfgang Grandegger partition@7f40000 { 3846dd1b64aSWolfgang Grandegger label = "env2"; 3856dd1b64aSWolfgang Grandegger reg = <0x07f40000 0x00040000>; 3866dd1b64aSWolfgang Grandegger }; 3876dd1b64aSWolfgang Grandegger partition@7f80000 { 3886dd1b64aSWolfgang Grandegger label = "u-boot"; 3896dd1b64aSWolfgang Grandegger reg = <0x07f80000 0x00080000>; 3906dd1b64aSWolfgang Grandegger read-only; 3916dd1b64aSWolfgang Grandegger }; 3926dd1b64aSWolfgang Grandegger }; 3936dd1b64aSWolfgang Grandegger 3946dd1b64aSWolfgang Grandegger /* Note: CAN support needs be enabled in U-Boot */ 3956dd1b64aSWolfgang Grandegger can0@2,0 { 3966dd1b64aSWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 3976dd1b64aSWolfgang Grandegger reg = <2 0x0 0x100>; 3987a385241SWolfgang Grandegger interrupts = <4 1>; 3996dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 4006dd1b64aSWolfgang Grandegger }; 4016dd1b64aSWolfgang Grandegger 4026dd1b64aSWolfgang Grandegger can1@2,100 { 4036dd1b64aSWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 4046dd1b64aSWolfgang Grandegger reg = <2 0x100 0x100>; 4057a385241SWolfgang Grandegger interrupts = <4 1>; 4066dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 4076dd1b64aSWolfgang Grandegger }; 4086dd1b64aSWolfgang Grandegger 4096dd1b64aSWolfgang Grandegger /* Note: NAND support needs to be enabled in U-Boot */ 4106dd1b64aSWolfgang Grandegger upm@3,0 { 4116dd1b64aSWolfgang Grandegger #address-cells = <0>; 4126dd1b64aSWolfgang Grandegger #size-cells = <0>; 4137995c7e9SWolfgang Grandegger compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; 4146dd1b64aSWolfgang Grandegger reg = <3 0x0 0x800>; 4156dd1b64aSWolfgang Grandegger fsl,upm-addr-offset = <0x10>; 4166dd1b64aSWolfgang Grandegger fsl,upm-cmd-offset = <0x08>; 4177995c7e9SWolfgang Grandegger /* Micron MT29F8G08FAB multi-chip device */ 4187995c7e9SWolfgang Grandegger fsl,upm-addr-line-cs-offsets = <0x0 0x200>; 4197995c7e9SWolfgang Grandegger fsl,upm-wait-flags = <0x5>; 4206dd1b64aSWolfgang Grandegger chip-delay = <25>; // in micro-seconds 4216dd1b64aSWolfgang Grandegger 4226dd1b64aSWolfgang Grandegger nand@0 { 4236dd1b64aSWolfgang Grandegger #address-cells = <1>; 4246dd1b64aSWolfgang Grandegger #size-cells = <1>; 4256dd1b64aSWolfgang Grandegger 4266dd1b64aSWolfgang Grandegger partition@0 { 4276dd1b64aSWolfgang Grandegger label = "fs"; 4287995c7e9SWolfgang Grandegger reg = <0x00000000 0x10000000>; 4296dd1b64aSWolfgang Grandegger }; 4306dd1b64aSWolfgang Grandegger }; 4316dd1b64aSWolfgang Grandegger }; 4326dd1b64aSWolfgang Grandegger }; 4336dd1b64aSWolfgang Grandegger 4346dd1b64aSWolfgang Grandegger pci0: pci@e0008000 { 4356dd1b64aSWolfgang Grandegger #interrupt-cells = <1>; 4366dd1b64aSWolfgang Grandegger #size-cells = <2>; 4376dd1b64aSWolfgang Grandegger #address-cells = <3>; 4386dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 4396dd1b64aSWolfgang Grandegger device_type = "pci"; 4406dd1b64aSWolfgang Grandegger reg = <0xe0008000 0x1000>; 4416dd1b64aSWolfgang Grandegger clock-frequency = <33333333>; 4426dd1b64aSWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 4436dd1b64aSWolfgang Grandegger interrupt-map = < 4446dd1b64aSWolfgang Grandegger /* IDSEL 28 */ 4456dd1b64aSWolfgang Grandegger 0xe000 0 0 1 &mpic 2 1 4466dd1b64aSWolfgang Grandegger 0xe000 0 0 2 &mpic 3 1>; 4476dd1b64aSWolfgang Grandegger 4486dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 4496dd1b64aSWolfgang Grandegger interrupts = <24 2>; 4506dd1b64aSWolfgang Grandegger bus-range = <0 0>; 4516dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 4526dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 4536dd1b64aSWolfgang Grandegger }; 4546dd1b64aSWolfgang Grandegger 4556dd1b64aSWolfgang Grandegger pci1: pcie@e000a000 { 4566dd1b64aSWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 4576dd1b64aSWolfgang Grandegger interrupt-map = < 4586dd1b64aSWolfgang Grandegger /* IDSEL 0x0 (PEX) */ 4596dd1b64aSWolfgang Grandegger 0x00000 0 0 1 &mpic 0 1 4606dd1b64aSWolfgang Grandegger 0x00000 0 0 2 &mpic 1 1 4616dd1b64aSWolfgang Grandegger 0x00000 0 0 3 &mpic 2 1 4626dd1b64aSWolfgang Grandegger 0x00000 0 0 4 &mpic 3 1>; 4636dd1b64aSWolfgang Grandegger 4646dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 4656dd1b64aSWolfgang Grandegger interrupts = <26 2>; 4666dd1b64aSWolfgang Grandegger bus-range = <0 0xff>; 4676dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000 4686dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0xef000000 0 0x08000000>; 4696dd1b64aSWolfgang Grandegger clock-frequency = <33333333>; 4706dd1b64aSWolfgang Grandegger #interrupt-cells = <1>; 4716dd1b64aSWolfgang Grandegger #size-cells = <2>; 4726dd1b64aSWolfgang Grandegger #address-cells = <3>; 4736dd1b64aSWolfgang Grandegger reg = <0xe000a000 0x1000>; 4746dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-pcie"; 4756dd1b64aSWolfgang Grandegger device_type = "pci"; 4766dd1b64aSWolfgang Grandegger pcie@0 { 4776dd1b64aSWolfgang Grandegger reg = <0 0 0 0 0>; 4786dd1b64aSWolfgang Grandegger #size-cells = <2>; 4796dd1b64aSWolfgang Grandegger #address-cells = <3>; 4806dd1b64aSWolfgang Grandegger device_type = "pci"; 4816dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0xc0000000 0x02000000 0 4826dd1b64aSWolfgang Grandegger 0xc0000000 0 0x20000000 4836dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0x01000000 0 4846dd1b64aSWolfgang Grandegger 0x00000000 0 0x08000000>; 4856dd1b64aSWolfgang Grandegger }; 4866dd1b64aSWolfgang Grandegger }; 4876dd1b64aSWolfgang Grandegger}; 488