16dd1b64aSWolfgang Grandegger/* 26dd1b64aSWolfgang Grandegger * TQM8548 Device Tree Source 36dd1b64aSWolfgang Grandegger * 46dd1b64aSWolfgang Grandegger * Copyright 2006 Freescale Semiconductor Inc. 56dd1b64aSWolfgang Grandegger * Copyright 2008 Wolfgang Grandegger <wg@denx.de> 66dd1b64aSWolfgang Grandegger * 76dd1b64aSWolfgang Grandegger * This program is free software; you can redistribute it and/or modify it 86dd1b64aSWolfgang Grandegger * under the terms of the GNU General Public License as published by the 96dd1b64aSWolfgang Grandegger * Free Software Foundation; either version 2 of the License, or (at your 106dd1b64aSWolfgang Grandegger * option) any later version. 116dd1b64aSWolfgang Grandegger */ 126dd1b64aSWolfgang Grandegger 136dd1b64aSWolfgang Grandegger/dts-v1/; 146dd1b64aSWolfgang Grandegger 156dd1b64aSWolfgang Grandegger/ { 166dd1b64aSWolfgang Grandegger model = "tqc,tqm8548"; 176dd1b64aSWolfgang Grandegger compatible = "tqc,tqm8548"; 186dd1b64aSWolfgang Grandegger #address-cells = <1>; 196dd1b64aSWolfgang Grandegger #size-cells = <1>; 206dd1b64aSWolfgang Grandegger 216dd1b64aSWolfgang Grandegger aliases { 226dd1b64aSWolfgang Grandegger ethernet0 = &enet0; 236dd1b64aSWolfgang Grandegger ethernet1 = &enet1; 246dd1b64aSWolfgang Grandegger ethernet2 = &enet2; 256dd1b64aSWolfgang Grandegger ethernet3 = &enet3; 266dd1b64aSWolfgang Grandegger 276dd1b64aSWolfgang Grandegger serial0 = &serial0; 286dd1b64aSWolfgang Grandegger serial1 = &serial1; 296dd1b64aSWolfgang Grandegger pci0 = &pci0; 306dd1b64aSWolfgang Grandegger pci1 = &pci1; 316dd1b64aSWolfgang Grandegger }; 326dd1b64aSWolfgang Grandegger 336dd1b64aSWolfgang Grandegger cpus { 346dd1b64aSWolfgang Grandegger #address-cells = <1>; 356dd1b64aSWolfgang Grandegger #size-cells = <0>; 366dd1b64aSWolfgang Grandegger 376dd1b64aSWolfgang Grandegger PowerPC,8548@0 { 386dd1b64aSWolfgang Grandegger device_type = "cpu"; 396dd1b64aSWolfgang Grandegger reg = <0>; 406dd1b64aSWolfgang Grandegger d-cache-line-size = <32>; // 32 bytes 416dd1b64aSWolfgang Grandegger i-cache-line-size = <32>; // 32 bytes 426dd1b64aSWolfgang Grandegger d-cache-size = <0x8000>; // L1, 32K 436dd1b64aSWolfgang Grandegger i-cache-size = <0x8000>; // L1, 32K 446dd1b64aSWolfgang Grandegger next-level-cache = <&L2>; 456dd1b64aSWolfgang Grandegger }; 466dd1b64aSWolfgang Grandegger }; 476dd1b64aSWolfgang Grandegger 486dd1b64aSWolfgang Grandegger memory { 496dd1b64aSWolfgang Grandegger device_type = "memory"; 506dd1b64aSWolfgang Grandegger reg = <0x00000000 0x00000000>; // Filled in by U-Boot 516dd1b64aSWolfgang Grandegger }; 526dd1b64aSWolfgang Grandegger 53d27a736cSWolfgang Grandegger soc@e0000000 { 546dd1b64aSWolfgang Grandegger #address-cells = <1>; 556dd1b64aSWolfgang Grandegger #size-cells = <1>; 566dd1b64aSWolfgang Grandegger device_type = "soc"; 576dd1b64aSWolfgang Grandegger ranges = <0x0 0xe0000000 0x100000>; 586dd1b64aSWolfgang Grandegger reg = <0xe0000000 0x1000>; // CCSRBAR 596dd1b64aSWolfgang Grandegger bus-frequency = <0>; 60d27a736cSWolfgang Grandegger compatible = "fsl,mpc8548-immr", "simple-bus"; 616dd1b64aSWolfgang Grandegger 626dd1b64aSWolfgang Grandegger memory-controller@2000 { 636dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-memory-controller"; 646dd1b64aSWolfgang Grandegger reg = <0x2000 0x1000>; 656dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 666dd1b64aSWolfgang Grandegger interrupts = <18 2>; 676dd1b64aSWolfgang Grandegger }; 686dd1b64aSWolfgang Grandegger 696dd1b64aSWolfgang Grandegger L2: l2-cache-controller@20000 { 706dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-l2-cache-controller"; 716dd1b64aSWolfgang Grandegger reg = <0x20000 0x1000>; 726dd1b64aSWolfgang Grandegger cache-line-size = <32>; // 32 bytes 736dd1b64aSWolfgang Grandegger cache-size = <0x80000>; // L2, 512K 746dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 756dd1b64aSWolfgang Grandegger interrupts = <16 2>; 766dd1b64aSWolfgang Grandegger }; 776dd1b64aSWolfgang Grandegger 786dd1b64aSWolfgang Grandegger i2c@3000 { 796dd1b64aSWolfgang Grandegger #address-cells = <1>; 806dd1b64aSWolfgang Grandegger #size-cells = <0>; 816dd1b64aSWolfgang Grandegger cell-index = <0>; 826dd1b64aSWolfgang Grandegger compatible = "fsl-i2c"; 836dd1b64aSWolfgang Grandegger reg = <0x3000 0x100>; 846dd1b64aSWolfgang Grandegger interrupts = <43 2>; 856dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 866dd1b64aSWolfgang Grandegger dfsrr; 87a3083220SWolfgang Grandegger 88a3083220SWolfgang Grandegger rtc@68 { 89a3083220SWolfgang Grandegger compatible = "dallas,ds1337"; 90a3083220SWolfgang Grandegger reg = <0x68>; 91a3083220SWolfgang Grandegger }; 926dd1b64aSWolfgang Grandegger }; 936dd1b64aSWolfgang Grandegger 946dd1b64aSWolfgang Grandegger i2c@3100 { 956dd1b64aSWolfgang Grandegger #address-cells = <1>; 966dd1b64aSWolfgang Grandegger #size-cells = <0>; 976dd1b64aSWolfgang Grandegger cell-index = <1>; 986dd1b64aSWolfgang Grandegger compatible = "fsl-i2c"; 996dd1b64aSWolfgang Grandegger reg = <0x3100 0x100>; 1006dd1b64aSWolfgang Grandegger interrupts = <43 2>; 1016dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1026dd1b64aSWolfgang Grandegger dfsrr; 1036dd1b64aSWolfgang Grandegger }; 1046dd1b64aSWolfgang Grandegger 105dee80553SKumar Gala dma@21300 { 106dee80553SKumar Gala #address-cells = <1>; 107dee80553SKumar Gala #size-cells = <1>; 108dee80553SKumar Gala compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 109dee80553SKumar Gala reg = <0x21300 0x4>; 110dee80553SKumar Gala ranges = <0x0 0x21100 0x200>; 111dee80553SKumar Gala cell-index = <0>; 112dee80553SKumar Gala dma-channel@0 { 113dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 114dee80553SKumar Gala "fsl,eloplus-dma-channel"; 115dee80553SKumar Gala reg = <0x0 0x80>; 116dee80553SKumar Gala cell-index = <0>; 117dee80553SKumar Gala interrupt-parent = <&mpic>; 118dee80553SKumar Gala interrupts = <20 2>; 119dee80553SKumar Gala }; 120dee80553SKumar Gala dma-channel@80 { 121dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 122dee80553SKumar Gala "fsl,eloplus-dma-channel"; 123dee80553SKumar Gala reg = <0x80 0x80>; 124dee80553SKumar Gala cell-index = <1>; 125dee80553SKumar Gala interrupt-parent = <&mpic>; 126dee80553SKumar Gala interrupts = <21 2>; 127dee80553SKumar Gala }; 128dee80553SKumar Gala dma-channel@100 { 129dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 130dee80553SKumar Gala "fsl,eloplus-dma-channel"; 131dee80553SKumar Gala reg = <0x100 0x80>; 132dee80553SKumar Gala cell-index = <2>; 133dee80553SKumar Gala interrupt-parent = <&mpic>; 134dee80553SKumar Gala interrupts = <22 2>; 135dee80553SKumar Gala }; 136dee80553SKumar Gala dma-channel@180 { 137dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 138dee80553SKumar Gala "fsl,eloplus-dma-channel"; 139dee80553SKumar Gala reg = <0x180 0x80>; 140dee80553SKumar Gala cell-index = <3>; 141dee80553SKumar Gala interrupt-parent = <&mpic>; 142dee80553SKumar Gala interrupts = <23 2>; 143dee80553SKumar Gala }; 144dee80553SKumar Gala }; 145dee80553SKumar Gala 1466dd1b64aSWolfgang Grandegger mdio@24520 { 1476dd1b64aSWolfgang Grandegger #address-cells = <1>; 1486dd1b64aSWolfgang Grandegger #size-cells = <0>; 1496dd1b64aSWolfgang Grandegger compatible = "fsl,gianfar-mdio"; 1506dd1b64aSWolfgang Grandegger reg = <0x24520 0x20>; 1516dd1b64aSWolfgang Grandegger 1526dd1b64aSWolfgang Grandegger phy1: ethernet-phy@0 { 1536dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1546dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1556dd1b64aSWolfgang Grandegger reg = <1>; 1566dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1576dd1b64aSWolfgang Grandegger }; 1586dd1b64aSWolfgang Grandegger phy2: ethernet-phy@1 { 1596dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1606dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1616dd1b64aSWolfgang Grandegger reg = <2>; 1626dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1636dd1b64aSWolfgang Grandegger }; 1646dd1b64aSWolfgang Grandegger phy3: ethernet-phy@3 { 1656dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1666dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1676dd1b64aSWolfgang Grandegger reg = <3>; 1686dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1696dd1b64aSWolfgang Grandegger }; 1706dd1b64aSWolfgang Grandegger phy4: ethernet-phy@4 { 1716dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1726dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1736dd1b64aSWolfgang Grandegger reg = <4>; 1746dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1756dd1b64aSWolfgang Grandegger }; 1766dd1b64aSWolfgang Grandegger phy5: ethernet-phy@5 { 1776dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1786dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1796dd1b64aSWolfgang Grandegger reg = <5>; 1806dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1816dd1b64aSWolfgang Grandegger }; 182b31a1d8bSAndy Fleming tbi0: tbi-phy@11 { 183b31a1d8bSAndy Fleming reg = <0x11>; 184b31a1d8bSAndy Fleming device_type = "tbi-phy"; 185b31a1d8bSAndy Fleming }; 186b31a1d8bSAndy Fleming }; 187b31a1d8bSAndy Fleming 188b31a1d8bSAndy Fleming mdio@25520 { 189b31a1d8bSAndy Fleming #address-cells = <1>; 190b31a1d8bSAndy Fleming #size-cells = <0>; 191b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 192b31a1d8bSAndy Fleming reg = <0x25520 0x20>; 193b31a1d8bSAndy Fleming 194b31a1d8bSAndy Fleming tbi1: tbi-phy@11 { 195b31a1d8bSAndy Fleming reg = <0x11>; 196b31a1d8bSAndy Fleming device_type = "tbi-phy"; 197b31a1d8bSAndy Fleming }; 198b31a1d8bSAndy Fleming }; 199b31a1d8bSAndy Fleming 200b31a1d8bSAndy Fleming mdio@26520 { 201b31a1d8bSAndy Fleming #address-cells = <1>; 202b31a1d8bSAndy Fleming #size-cells = <0>; 203b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 204b31a1d8bSAndy Fleming reg = <0x26520 0x20>; 205b31a1d8bSAndy Fleming 206b31a1d8bSAndy Fleming tbi2: tbi-phy@11 { 207b31a1d8bSAndy Fleming reg = <0x11>; 208b31a1d8bSAndy Fleming device_type = "tbi-phy"; 209b31a1d8bSAndy Fleming }; 210b31a1d8bSAndy Fleming }; 211b31a1d8bSAndy Fleming 212b31a1d8bSAndy Fleming mdio@27520 { 213b31a1d8bSAndy Fleming #address-cells = <1>; 214b31a1d8bSAndy Fleming #size-cells = <0>; 215b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 216b31a1d8bSAndy Fleming reg = <0x27520 0x20>; 217b31a1d8bSAndy Fleming 218b31a1d8bSAndy Fleming tbi3: tbi-phy@11 { 219b31a1d8bSAndy Fleming reg = <0x11>; 220b31a1d8bSAndy Fleming device_type = "tbi-phy"; 221b31a1d8bSAndy Fleming }; 2226dd1b64aSWolfgang Grandegger }; 2236dd1b64aSWolfgang Grandegger 2246dd1b64aSWolfgang Grandegger enet0: ethernet@24000 { 2256dd1b64aSWolfgang Grandegger cell-index = <0>; 2266dd1b64aSWolfgang Grandegger device_type = "network"; 2276dd1b64aSWolfgang Grandegger model = "eTSEC"; 2286dd1b64aSWolfgang Grandegger compatible = "gianfar"; 2296dd1b64aSWolfgang Grandegger reg = <0x24000 0x1000>; 2306dd1b64aSWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 2316dd1b64aSWolfgang Grandegger interrupts = <29 2 30 2 34 2>; 2326dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 233b31a1d8bSAndy Fleming tbi-handle = <&tbi0>; 2346dd1b64aSWolfgang Grandegger phy-handle = <&phy2>; 2356dd1b64aSWolfgang Grandegger }; 2366dd1b64aSWolfgang Grandegger 2376dd1b64aSWolfgang Grandegger enet1: ethernet@25000 { 2386dd1b64aSWolfgang Grandegger cell-index = <1>; 2396dd1b64aSWolfgang Grandegger device_type = "network"; 2406dd1b64aSWolfgang Grandegger model = "eTSEC"; 2416dd1b64aSWolfgang Grandegger compatible = "gianfar"; 2426dd1b64aSWolfgang Grandegger reg = <0x25000 0x1000>; 2436dd1b64aSWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 2446dd1b64aSWolfgang Grandegger interrupts = <35 2 36 2 40 2>; 2456dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 246b31a1d8bSAndy Fleming tbi-handle = <&tbi1>; 2476dd1b64aSWolfgang Grandegger phy-handle = <&phy1>; 2486dd1b64aSWolfgang Grandegger }; 2496dd1b64aSWolfgang Grandegger 2506dd1b64aSWolfgang Grandegger enet2: ethernet@26000 { 2516dd1b64aSWolfgang Grandegger cell-index = <2>; 2526dd1b64aSWolfgang Grandegger device_type = "network"; 2536dd1b64aSWolfgang Grandegger model = "eTSEC"; 2546dd1b64aSWolfgang Grandegger compatible = "gianfar"; 2556dd1b64aSWolfgang Grandegger reg = <0x26000 0x1000>; 2566dd1b64aSWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 2576dd1b64aSWolfgang Grandegger interrupts = <31 2 32 2 33 2>; 2586dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 259b31a1d8bSAndy Fleming tbi-handle = <&tbi2>; 2606dd1b64aSWolfgang Grandegger phy-handle = <&phy3>; 2616dd1b64aSWolfgang Grandegger }; 2626dd1b64aSWolfgang Grandegger 2636dd1b64aSWolfgang Grandegger enet3: ethernet@27000 { 2646dd1b64aSWolfgang Grandegger cell-index = <3>; 2656dd1b64aSWolfgang Grandegger device_type = "network"; 2666dd1b64aSWolfgang Grandegger model = "eTSEC"; 2676dd1b64aSWolfgang Grandegger compatible = "gianfar"; 2686dd1b64aSWolfgang Grandegger reg = <0x27000 0x1000>; 2696dd1b64aSWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 2706dd1b64aSWolfgang Grandegger interrupts = <37 2 38 2 39 2>; 2716dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 272b31a1d8bSAndy Fleming tbi-handle = <&tbi3>; 2736dd1b64aSWolfgang Grandegger phy-handle = <&phy4>; 2746dd1b64aSWolfgang Grandegger }; 2756dd1b64aSWolfgang Grandegger 2766dd1b64aSWolfgang Grandegger serial0: serial@4500 { 2776dd1b64aSWolfgang Grandegger cell-index = <0>; 2786dd1b64aSWolfgang Grandegger device_type = "serial"; 2796dd1b64aSWolfgang Grandegger compatible = "ns16550"; 2806dd1b64aSWolfgang Grandegger reg = <0x4500 0x100>; // reg base, size 2816dd1b64aSWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 2826dd1b64aSWolfgang Grandegger current-speed = <115200>; 2836dd1b64aSWolfgang Grandegger interrupts = <42 2>; 2846dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 2856dd1b64aSWolfgang Grandegger }; 2866dd1b64aSWolfgang Grandegger 2876dd1b64aSWolfgang Grandegger serial1: serial@4600 { 2886dd1b64aSWolfgang Grandegger cell-index = <1>; 2896dd1b64aSWolfgang Grandegger device_type = "serial"; 2906dd1b64aSWolfgang Grandegger compatible = "ns16550"; 2916dd1b64aSWolfgang Grandegger reg = <0x4600 0x100>; // reg base, size 2926dd1b64aSWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 2936dd1b64aSWolfgang Grandegger current-speed = <115200>; 2946dd1b64aSWolfgang Grandegger interrupts = <42 2>; 2956dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 2966dd1b64aSWolfgang Grandegger }; 2976dd1b64aSWolfgang Grandegger 2986dd1b64aSWolfgang Grandegger global-utilities@e0000 { // global utilities reg 2996dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-guts"; 3006dd1b64aSWolfgang Grandegger reg = <0xe0000 0x1000>; 3016dd1b64aSWolfgang Grandegger fsl,has-rstcr; 3026dd1b64aSWolfgang Grandegger }; 3036dd1b64aSWolfgang Grandegger 3046dd1b64aSWolfgang Grandegger mpic: pic@40000 { 3056dd1b64aSWolfgang Grandegger interrupt-controller; 3066dd1b64aSWolfgang Grandegger #address-cells = <0>; 3076dd1b64aSWolfgang Grandegger #interrupt-cells = <2>; 3086dd1b64aSWolfgang Grandegger reg = <0x40000 0x40000>; 3096dd1b64aSWolfgang Grandegger compatible = "chrp,open-pic"; 3106dd1b64aSWolfgang Grandegger device_type = "open-pic"; 3116dd1b64aSWolfgang Grandegger }; 3126dd1b64aSWolfgang Grandegger }; 3136dd1b64aSWolfgang Grandegger 3146dd1b64aSWolfgang Grandegger localbus@e0005000 { 3156dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 3166dd1b64aSWolfgang Grandegger "simple-bus"; 3176dd1b64aSWolfgang Grandegger #address-cells = <2>; 3186dd1b64aSWolfgang Grandegger #size-cells = <1>; 3196dd1b64aSWolfgang Grandegger reg = <0xe0005000 0x100>; // BRx, ORx, etc. 3206dd1b64aSWolfgang Grandegger 3216dd1b64aSWolfgang Grandegger ranges = < 3226dd1b64aSWolfgang Grandegger 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 3236dd1b64aSWolfgang Grandegger 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 3246dd1b64aSWolfgang Grandegger 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) 3256dd1b64aSWolfgang Grandegger 3 0x0 0xe3010000 0x00008000 // NAND FLASH 3266dd1b64aSWolfgang Grandegger 3276dd1b64aSWolfgang Grandegger >; 3286dd1b64aSWolfgang Grandegger 3296dd1b64aSWolfgang Grandegger flash@1,0 { 3306dd1b64aSWolfgang Grandegger #address-cells = <1>; 3316dd1b64aSWolfgang Grandegger #size-cells = <1>; 3326dd1b64aSWolfgang Grandegger compatible = "cfi-flash"; 3336dd1b64aSWolfgang Grandegger reg = <1 0x0 0x8000000>; 3346dd1b64aSWolfgang Grandegger bank-width = <4>; 3356dd1b64aSWolfgang Grandegger device-width = <1>; 3366dd1b64aSWolfgang Grandegger 3376dd1b64aSWolfgang Grandegger partition@0 { 3386dd1b64aSWolfgang Grandegger label = "kernel"; 3396dd1b64aSWolfgang Grandegger reg = <0x00000000 0x00200000>; 3406dd1b64aSWolfgang Grandegger }; 3416dd1b64aSWolfgang Grandegger partition@200000 { 3426dd1b64aSWolfgang Grandegger label = "root"; 3436dd1b64aSWolfgang Grandegger reg = <0x00200000 0x00300000>; 3446dd1b64aSWolfgang Grandegger }; 3456dd1b64aSWolfgang Grandegger partition@500000 { 3466dd1b64aSWolfgang Grandegger label = "user"; 3476dd1b64aSWolfgang Grandegger reg = <0x00500000 0x07a00000>; 3486dd1b64aSWolfgang Grandegger }; 3496dd1b64aSWolfgang Grandegger partition@7f00000 { 3506dd1b64aSWolfgang Grandegger label = "env1"; 3516dd1b64aSWolfgang Grandegger reg = <0x07f00000 0x00040000>; 3526dd1b64aSWolfgang Grandegger }; 3536dd1b64aSWolfgang Grandegger partition@7f40000 { 3546dd1b64aSWolfgang Grandegger label = "env2"; 3556dd1b64aSWolfgang Grandegger reg = <0x07f40000 0x00040000>; 3566dd1b64aSWolfgang Grandegger }; 3576dd1b64aSWolfgang Grandegger partition@7f80000 { 3586dd1b64aSWolfgang Grandegger label = "u-boot"; 3596dd1b64aSWolfgang Grandegger reg = <0x07f80000 0x00080000>; 3606dd1b64aSWolfgang Grandegger read-only; 3616dd1b64aSWolfgang Grandegger }; 3626dd1b64aSWolfgang Grandegger }; 3636dd1b64aSWolfgang Grandegger 3646dd1b64aSWolfgang Grandegger /* Note: CAN support needs be enabled in U-Boot */ 3656dd1b64aSWolfgang Grandegger can0@2,0 { 3666dd1b64aSWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 3676dd1b64aSWolfgang Grandegger reg = <2 0x0 0x100>; 3686dd1b64aSWolfgang Grandegger interrupts = <4 0>; 3696dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 3706dd1b64aSWolfgang Grandegger }; 3716dd1b64aSWolfgang Grandegger 3726dd1b64aSWolfgang Grandegger can1@2,100 { 3736dd1b64aSWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 3746dd1b64aSWolfgang Grandegger reg = <2 0x100 0x100>; 3756dd1b64aSWolfgang Grandegger interrupts = <4 0>; 3766dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 3776dd1b64aSWolfgang Grandegger }; 3786dd1b64aSWolfgang Grandegger 3796dd1b64aSWolfgang Grandegger /* Note: NAND support needs to be enabled in U-Boot */ 3806dd1b64aSWolfgang Grandegger upm@3,0 { 3816dd1b64aSWolfgang Grandegger #address-cells = <0>; 3826dd1b64aSWolfgang Grandegger #size-cells = <0>; 3837995c7e9SWolfgang Grandegger compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; 3846dd1b64aSWolfgang Grandegger reg = <3 0x0 0x800>; 3856dd1b64aSWolfgang Grandegger fsl,upm-addr-offset = <0x10>; 3866dd1b64aSWolfgang Grandegger fsl,upm-cmd-offset = <0x08>; 3877995c7e9SWolfgang Grandegger /* Micron MT29F8G08FAB multi-chip device */ 3887995c7e9SWolfgang Grandegger fsl,upm-addr-line-cs-offsets = <0x0 0x200>; 3897995c7e9SWolfgang Grandegger fsl,upm-wait-flags = <0x5>; 3906dd1b64aSWolfgang Grandegger chip-delay = <25>; // in micro-seconds 3916dd1b64aSWolfgang Grandegger 3926dd1b64aSWolfgang Grandegger nand@0 { 3936dd1b64aSWolfgang Grandegger #address-cells = <1>; 3946dd1b64aSWolfgang Grandegger #size-cells = <1>; 3956dd1b64aSWolfgang Grandegger 3966dd1b64aSWolfgang Grandegger partition@0 { 3976dd1b64aSWolfgang Grandegger label = "fs"; 3987995c7e9SWolfgang Grandegger reg = <0x00000000 0x10000000>; 3996dd1b64aSWolfgang Grandegger }; 4006dd1b64aSWolfgang Grandegger }; 4016dd1b64aSWolfgang Grandegger }; 4026dd1b64aSWolfgang Grandegger }; 4036dd1b64aSWolfgang Grandegger 4046dd1b64aSWolfgang Grandegger pci0: pci@e0008000 { 4056dd1b64aSWolfgang Grandegger cell-index = <0>; 4066dd1b64aSWolfgang Grandegger #interrupt-cells = <1>; 4076dd1b64aSWolfgang Grandegger #size-cells = <2>; 4086dd1b64aSWolfgang Grandegger #address-cells = <3>; 4096dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 4106dd1b64aSWolfgang Grandegger device_type = "pci"; 4116dd1b64aSWolfgang Grandegger reg = <0xe0008000 0x1000>; 4126dd1b64aSWolfgang Grandegger clock-frequency = <33333333>; 4136dd1b64aSWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 4146dd1b64aSWolfgang Grandegger interrupt-map = < 4156dd1b64aSWolfgang Grandegger /* IDSEL 28 */ 4166dd1b64aSWolfgang Grandegger 0xe000 0 0 1 &mpic 2 1 4176dd1b64aSWolfgang Grandegger 0xe000 0 0 2 &mpic 3 1>; 4186dd1b64aSWolfgang Grandegger 4196dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 4206dd1b64aSWolfgang Grandegger interrupts = <24 2>; 4216dd1b64aSWolfgang Grandegger bus-range = <0 0>; 4226dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 4236dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 4246dd1b64aSWolfgang Grandegger }; 4256dd1b64aSWolfgang Grandegger 4266dd1b64aSWolfgang Grandegger pci1: pcie@e000a000 { 4276dd1b64aSWolfgang Grandegger cell-index = <2>; 4286dd1b64aSWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 4296dd1b64aSWolfgang Grandegger interrupt-map = < 4306dd1b64aSWolfgang Grandegger /* IDSEL 0x0 (PEX) */ 4316dd1b64aSWolfgang Grandegger 0x00000 0 0 1 &mpic 0 1 4326dd1b64aSWolfgang Grandegger 0x00000 0 0 2 &mpic 1 1 4336dd1b64aSWolfgang Grandegger 0x00000 0 0 3 &mpic 2 1 4346dd1b64aSWolfgang Grandegger 0x00000 0 0 4 &mpic 3 1>; 4356dd1b64aSWolfgang Grandegger 4366dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 4376dd1b64aSWolfgang Grandegger interrupts = <26 2>; 4386dd1b64aSWolfgang Grandegger bus-range = <0 0xff>; 4396dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000 4406dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0xef000000 0 0x08000000>; 4416dd1b64aSWolfgang Grandegger clock-frequency = <33333333>; 4426dd1b64aSWolfgang Grandegger #interrupt-cells = <1>; 4436dd1b64aSWolfgang Grandegger #size-cells = <2>; 4446dd1b64aSWolfgang Grandegger #address-cells = <3>; 4456dd1b64aSWolfgang Grandegger reg = <0xe000a000 0x1000>; 4466dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-pcie"; 4476dd1b64aSWolfgang Grandegger device_type = "pci"; 4486dd1b64aSWolfgang Grandegger pcie@0 { 4496dd1b64aSWolfgang Grandegger reg = <0 0 0 0 0>; 4506dd1b64aSWolfgang Grandegger #size-cells = <2>; 4516dd1b64aSWolfgang Grandegger #address-cells = <3>; 4526dd1b64aSWolfgang Grandegger device_type = "pci"; 4536dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0xc0000000 0x02000000 0 4546dd1b64aSWolfgang Grandegger 0xc0000000 0 0x20000000 4556dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0x01000000 0 4566dd1b64aSWolfgang Grandegger 0x00000000 0 0x08000000>; 4576dd1b64aSWolfgang Grandegger }; 4586dd1b64aSWolfgang Grandegger }; 4596dd1b64aSWolfgang Grandegger}; 460