16dd1b64aSWolfgang Grandegger/* 26dd1b64aSWolfgang Grandegger * TQM8548 Device Tree Source 36dd1b64aSWolfgang Grandegger * 46dd1b64aSWolfgang Grandegger * Copyright 2006 Freescale Semiconductor Inc. 56dd1b64aSWolfgang Grandegger * Copyright 2008 Wolfgang Grandegger <wg@denx.de> 66dd1b64aSWolfgang Grandegger * 76dd1b64aSWolfgang Grandegger * This program is free software; you can redistribute it and/or modify it 86dd1b64aSWolfgang Grandegger * under the terms of the GNU General Public License as published by the 96dd1b64aSWolfgang Grandegger * Free Software Foundation; either version 2 of the License, or (at your 106dd1b64aSWolfgang Grandegger * option) any later version. 116dd1b64aSWolfgang Grandegger */ 126dd1b64aSWolfgang Grandegger 136dd1b64aSWolfgang Grandegger/dts-v1/; 146dd1b64aSWolfgang Grandegger 156dd1b64aSWolfgang Grandegger/ { 166dd1b64aSWolfgang Grandegger model = "tqc,tqm8548"; 176dd1b64aSWolfgang Grandegger compatible = "tqc,tqm8548"; 186dd1b64aSWolfgang Grandegger #address-cells = <1>; 196dd1b64aSWolfgang Grandegger #size-cells = <1>; 206dd1b64aSWolfgang Grandegger 216dd1b64aSWolfgang Grandegger aliases { 226dd1b64aSWolfgang Grandegger ethernet0 = &enet0; 236dd1b64aSWolfgang Grandegger ethernet1 = &enet1; 246dd1b64aSWolfgang Grandegger ethernet2 = &enet2; 256dd1b64aSWolfgang Grandegger ethernet3 = &enet3; 266dd1b64aSWolfgang Grandegger 276dd1b64aSWolfgang Grandegger serial0 = &serial0; 286dd1b64aSWolfgang Grandegger serial1 = &serial1; 296dd1b64aSWolfgang Grandegger pci0 = &pci0; 306dd1b64aSWolfgang Grandegger pci1 = &pci1; 316dd1b64aSWolfgang Grandegger }; 326dd1b64aSWolfgang Grandegger 336dd1b64aSWolfgang Grandegger cpus { 346dd1b64aSWolfgang Grandegger #address-cells = <1>; 356dd1b64aSWolfgang Grandegger #size-cells = <0>; 366dd1b64aSWolfgang Grandegger 376dd1b64aSWolfgang Grandegger PowerPC,8548@0 { 386dd1b64aSWolfgang Grandegger device_type = "cpu"; 396dd1b64aSWolfgang Grandegger reg = <0>; 406dd1b64aSWolfgang Grandegger d-cache-line-size = <32>; // 32 bytes 416dd1b64aSWolfgang Grandegger i-cache-line-size = <32>; // 32 bytes 426dd1b64aSWolfgang Grandegger d-cache-size = <0x8000>; // L1, 32K 436dd1b64aSWolfgang Grandegger i-cache-size = <0x8000>; // L1, 32K 446dd1b64aSWolfgang Grandegger next-level-cache = <&L2>; 456dd1b64aSWolfgang Grandegger }; 466dd1b64aSWolfgang Grandegger }; 476dd1b64aSWolfgang Grandegger 486dd1b64aSWolfgang Grandegger memory { 496dd1b64aSWolfgang Grandegger device_type = "memory"; 506dd1b64aSWolfgang Grandegger reg = <0x00000000 0x00000000>; // Filled in by U-Boot 516dd1b64aSWolfgang Grandegger }; 526dd1b64aSWolfgang Grandegger 536dd1b64aSWolfgang Grandegger soc8548@e0000000 { 546dd1b64aSWolfgang Grandegger #address-cells = <1>; 556dd1b64aSWolfgang Grandegger #size-cells = <1>; 566dd1b64aSWolfgang Grandegger device_type = "soc"; 576dd1b64aSWolfgang Grandegger ranges = <0x0 0xe0000000 0x100000>; 586dd1b64aSWolfgang Grandegger reg = <0xe0000000 0x1000>; // CCSRBAR 596dd1b64aSWolfgang Grandegger bus-frequency = <0>; 606dd1b64aSWolfgang Grandegger 616dd1b64aSWolfgang Grandegger memory-controller@2000 { 626dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-memory-controller"; 636dd1b64aSWolfgang Grandegger reg = <0x2000 0x1000>; 646dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 656dd1b64aSWolfgang Grandegger interrupts = <18 2>; 666dd1b64aSWolfgang Grandegger }; 676dd1b64aSWolfgang Grandegger 686dd1b64aSWolfgang Grandegger L2: l2-cache-controller@20000 { 696dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-l2-cache-controller"; 706dd1b64aSWolfgang Grandegger reg = <0x20000 0x1000>; 716dd1b64aSWolfgang Grandegger cache-line-size = <32>; // 32 bytes 726dd1b64aSWolfgang Grandegger cache-size = <0x80000>; // L2, 512K 736dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 746dd1b64aSWolfgang Grandegger interrupts = <16 2>; 756dd1b64aSWolfgang Grandegger }; 766dd1b64aSWolfgang Grandegger 776dd1b64aSWolfgang Grandegger i2c@3000 { 786dd1b64aSWolfgang Grandegger #address-cells = <1>; 796dd1b64aSWolfgang Grandegger #size-cells = <0>; 806dd1b64aSWolfgang Grandegger cell-index = <0>; 816dd1b64aSWolfgang Grandegger compatible = "fsl-i2c"; 826dd1b64aSWolfgang Grandegger reg = <0x3000 0x100>; 836dd1b64aSWolfgang Grandegger interrupts = <43 2>; 846dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 856dd1b64aSWolfgang Grandegger dfsrr; 866dd1b64aSWolfgang Grandegger }; 876dd1b64aSWolfgang Grandegger 886dd1b64aSWolfgang Grandegger i2c@3100 { 896dd1b64aSWolfgang Grandegger #address-cells = <1>; 906dd1b64aSWolfgang Grandegger #size-cells = <0>; 916dd1b64aSWolfgang Grandegger cell-index = <1>; 926dd1b64aSWolfgang Grandegger compatible = "fsl-i2c"; 936dd1b64aSWolfgang Grandegger reg = <0x3100 0x100>; 946dd1b64aSWolfgang Grandegger interrupts = <43 2>; 956dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 966dd1b64aSWolfgang Grandegger dfsrr; 976dd1b64aSWolfgang Grandegger }; 986dd1b64aSWolfgang Grandegger 996dd1b64aSWolfgang Grandegger mdio@24520 { 1006dd1b64aSWolfgang Grandegger #address-cells = <1>; 1016dd1b64aSWolfgang Grandegger #size-cells = <0>; 1026dd1b64aSWolfgang Grandegger compatible = "fsl,gianfar-mdio"; 1036dd1b64aSWolfgang Grandegger reg = <0x24520 0x20>; 1046dd1b64aSWolfgang Grandegger 1056dd1b64aSWolfgang Grandegger phy1: ethernet-phy@0 { 1066dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1076dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1086dd1b64aSWolfgang Grandegger reg = <1>; 1096dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1106dd1b64aSWolfgang Grandegger }; 1116dd1b64aSWolfgang Grandegger phy2: ethernet-phy@1 { 1126dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1136dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1146dd1b64aSWolfgang Grandegger reg = <2>; 1156dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1166dd1b64aSWolfgang Grandegger }; 1176dd1b64aSWolfgang Grandegger phy3: ethernet-phy@3 { 1186dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1196dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1206dd1b64aSWolfgang Grandegger reg = <3>; 1216dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1226dd1b64aSWolfgang Grandegger }; 1236dd1b64aSWolfgang Grandegger phy4: ethernet-phy@4 { 1246dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1256dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1266dd1b64aSWolfgang Grandegger reg = <4>; 1276dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1286dd1b64aSWolfgang Grandegger }; 1296dd1b64aSWolfgang Grandegger phy5: ethernet-phy@5 { 1306dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1316dd1b64aSWolfgang Grandegger interrupts = <8 1>; 1326dd1b64aSWolfgang Grandegger reg = <5>; 1336dd1b64aSWolfgang Grandegger device_type = "ethernet-phy"; 1346dd1b64aSWolfgang Grandegger }; 1356dd1b64aSWolfgang Grandegger }; 1366dd1b64aSWolfgang Grandegger 1376dd1b64aSWolfgang Grandegger enet0: ethernet@24000 { 1386dd1b64aSWolfgang Grandegger cell-index = <0>; 1396dd1b64aSWolfgang Grandegger device_type = "network"; 1406dd1b64aSWolfgang Grandegger model = "eTSEC"; 1416dd1b64aSWolfgang Grandegger compatible = "gianfar"; 1426dd1b64aSWolfgang Grandegger reg = <0x24000 0x1000>; 1436dd1b64aSWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 1446dd1b64aSWolfgang Grandegger interrupts = <29 2 30 2 34 2>; 1456dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1466dd1b64aSWolfgang Grandegger phy-handle = <&phy2>; 1476dd1b64aSWolfgang Grandegger }; 1486dd1b64aSWolfgang Grandegger 1496dd1b64aSWolfgang Grandegger enet1: ethernet@25000 { 1506dd1b64aSWolfgang Grandegger cell-index = <1>; 1516dd1b64aSWolfgang Grandegger device_type = "network"; 1526dd1b64aSWolfgang Grandegger model = "eTSEC"; 1536dd1b64aSWolfgang Grandegger compatible = "gianfar"; 1546dd1b64aSWolfgang Grandegger reg = <0x25000 0x1000>; 1556dd1b64aSWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 1566dd1b64aSWolfgang Grandegger interrupts = <35 2 36 2 40 2>; 1576dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1586dd1b64aSWolfgang Grandegger phy-handle = <&phy1>; 1596dd1b64aSWolfgang Grandegger }; 1606dd1b64aSWolfgang Grandegger 1616dd1b64aSWolfgang Grandegger enet2: ethernet@26000 { 1626dd1b64aSWolfgang Grandegger cell-index = <2>; 1636dd1b64aSWolfgang Grandegger device_type = "network"; 1646dd1b64aSWolfgang Grandegger model = "eTSEC"; 1656dd1b64aSWolfgang Grandegger compatible = "gianfar"; 1666dd1b64aSWolfgang Grandegger reg = <0x26000 0x1000>; 1676dd1b64aSWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 1686dd1b64aSWolfgang Grandegger interrupts = <31 2 32 2 33 2>; 1696dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1706dd1b64aSWolfgang Grandegger phy-handle = <&phy3>; 1716dd1b64aSWolfgang Grandegger }; 1726dd1b64aSWolfgang Grandegger 1736dd1b64aSWolfgang Grandegger enet3: ethernet@27000 { 1746dd1b64aSWolfgang Grandegger cell-index = <3>; 1756dd1b64aSWolfgang Grandegger device_type = "network"; 1766dd1b64aSWolfgang Grandegger model = "eTSEC"; 1776dd1b64aSWolfgang Grandegger compatible = "gianfar"; 1786dd1b64aSWolfgang Grandegger reg = <0x27000 0x1000>; 1796dd1b64aSWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 1806dd1b64aSWolfgang Grandegger interrupts = <37 2 38 2 39 2>; 1816dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1826dd1b64aSWolfgang Grandegger phy-handle = <&phy4>; 1836dd1b64aSWolfgang Grandegger }; 1846dd1b64aSWolfgang Grandegger 1856dd1b64aSWolfgang Grandegger serial0: serial@4500 { 1866dd1b64aSWolfgang Grandegger cell-index = <0>; 1876dd1b64aSWolfgang Grandegger device_type = "serial"; 1886dd1b64aSWolfgang Grandegger compatible = "ns16550"; 1896dd1b64aSWolfgang Grandegger reg = <0x4500 0x100>; // reg base, size 1906dd1b64aSWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 1916dd1b64aSWolfgang Grandegger current-speed = <115200>; 1926dd1b64aSWolfgang Grandegger interrupts = <42 2>; 1936dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 1946dd1b64aSWolfgang Grandegger }; 1956dd1b64aSWolfgang Grandegger 1966dd1b64aSWolfgang Grandegger serial1: serial@4600 { 1976dd1b64aSWolfgang Grandegger cell-index = <1>; 1986dd1b64aSWolfgang Grandegger device_type = "serial"; 1996dd1b64aSWolfgang Grandegger compatible = "ns16550"; 2006dd1b64aSWolfgang Grandegger reg = <0x4600 0x100>; // reg base, size 2016dd1b64aSWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 2026dd1b64aSWolfgang Grandegger current-speed = <115200>; 2036dd1b64aSWolfgang Grandegger interrupts = <42 2>; 2046dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 2056dd1b64aSWolfgang Grandegger }; 2066dd1b64aSWolfgang Grandegger 2076dd1b64aSWolfgang Grandegger global-utilities@e0000 { // global utilities reg 2086dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-guts"; 2096dd1b64aSWolfgang Grandegger reg = <0xe0000 0x1000>; 2106dd1b64aSWolfgang Grandegger fsl,has-rstcr; 2116dd1b64aSWolfgang Grandegger }; 2126dd1b64aSWolfgang Grandegger 2136dd1b64aSWolfgang Grandegger mpic: pic@40000 { 2146dd1b64aSWolfgang Grandegger interrupt-controller; 2156dd1b64aSWolfgang Grandegger #address-cells = <0>; 2166dd1b64aSWolfgang Grandegger #interrupt-cells = <2>; 2176dd1b64aSWolfgang Grandegger reg = <0x40000 0x40000>; 2186dd1b64aSWolfgang Grandegger compatible = "chrp,open-pic"; 2196dd1b64aSWolfgang Grandegger device_type = "open-pic"; 2206dd1b64aSWolfgang Grandegger }; 2216dd1b64aSWolfgang Grandegger }; 2226dd1b64aSWolfgang Grandegger 2236dd1b64aSWolfgang Grandegger localbus@e0005000 { 2246dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 2256dd1b64aSWolfgang Grandegger "simple-bus"; 2266dd1b64aSWolfgang Grandegger #address-cells = <2>; 2276dd1b64aSWolfgang Grandegger #size-cells = <1>; 2286dd1b64aSWolfgang Grandegger reg = <0xe0005000 0x100>; // BRx, ORx, etc. 2296dd1b64aSWolfgang Grandegger 2306dd1b64aSWolfgang Grandegger ranges = < 2316dd1b64aSWolfgang Grandegger 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 2326dd1b64aSWolfgang Grandegger 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 2336dd1b64aSWolfgang Grandegger 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) 2346dd1b64aSWolfgang Grandegger 3 0x0 0xe3010000 0x00008000 // NAND FLASH 2356dd1b64aSWolfgang Grandegger 2366dd1b64aSWolfgang Grandegger >; 2376dd1b64aSWolfgang Grandegger 2386dd1b64aSWolfgang Grandegger flash@1,0 { 2396dd1b64aSWolfgang Grandegger #address-cells = <1>; 2406dd1b64aSWolfgang Grandegger #size-cells = <1>; 2416dd1b64aSWolfgang Grandegger compatible = "cfi-flash"; 2426dd1b64aSWolfgang Grandegger reg = <1 0x0 0x8000000>; 2436dd1b64aSWolfgang Grandegger bank-width = <4>; 2446dd1b64aSWolfgang Grandegger device-width = <1>; 2456dd1b64aSWolfgang Grandegger 2466dd1b64aSWolfgang Grandegger partition@0 { 2476dd1b64aSWolfgang Grandegger label = "kernel"; 2486dd1b64aSWolfgang Grandegger reg = <0x00000000 0x00200000>; 2496dd1b64aSWolfgang Grandegger }; 2506dd1b64aSWolfgang Grandegger partition@200000 { 2516dd1b64aSWolfgang Grandegger label = "root"; 2526dd1b64aSWolfgang Grandegger reg = <0x00200000 0x00300000>; 2536dd1b64aSWolfgang Grandegger }; 2546dd1b64aSWolfgang Grandegger partition@500000 { 2556dd1b64aSWolfgang Grandegger label = "user"; 2566dd1b64aSWolfgang Grandegger reg = <0x00500000 0x07a00000>; 2576dd1b64aSWolfgang Grandegger }; 2586dd1b64aSWolfgang Grandegger partition@7f00000 { 2596dd1b64aSWolfgang Grandegger label = "env1"; 2606dd1b64aSWolfgang Grandegger reg = <0x07f00000 0x00040000>; 2616dd1b64aSWolfgang Grandegger }; 2626dd1b64aSWolfgang Grandegger partition@7f40000 { 2636dd1b64aSWolfgang Grandegger label = "env2"; 2646dd1b64aSWolfgang Grandegger reg = <0x07f40000 0x00040000>; 2656dd1b64aSWolfgang Grandegger }; 2666dd1b64aSWolfgang Grandegger partition@7f80000 { 2676dd1b64aSWolfgang Grandegger label = "u-boot"; 2686dd1b64aSWolfgang Grandegger reg = <0x07f80000 0x00080000>; 2696dd1b64aSWolfgang Grandegger read-only; 2706dd1b64aSWolfgang Grandegger }; 2716dd1b64aSWolfgang Grandegger }; 2726dd1b64aSWolfgang Grandegger 2736dd1b64aSWolfgang Grandegger /* Note: CAN support needs be enabled in U-Boot */ 2746dd1b64aSWolfgang Grandegger can0@2,0 { 2756dd1b64aSWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 2766dd1b64aSWolfgang Grandegger reg = <2 0x0 0x100>; 2776dd1b64aSWolfgang Grandegger interrupts = <4 0>; 2786dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 2796dd1b64aSWolfgang Grandegger }; 2806dd1b64aSWolfgang Grandegger 2816dd1b64aSWolfgang Grandegger can1@2,100 { 2826dd1b64aSWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 2836dd1b64aSWolfgang Grandegger reg = <2 0x100 0x100>; 2846dd1b64aSWolfgang Grandegger interrupts = <4 0>; 2856dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 2866dd1b64aSWolfgang Grandegger }; 2876dd1b64aSWolfgang Grandegger 2886dd1b64aSWolfgang Grandegger /* Note: NAND support needs to be enabled in U-Boot */ 2896dd1b64aSWolfgang Grandegger upm@3,0 { 2906dd1b64aSWolfgang Grandegger #address-cells = <0>; 2916dd1b64aSWolfgang Grandegger #size-cells = <0>; 2926dd1b64aSWolfgang Grandegger compatible = "fsl,upm-nand"; 2936dd1b64aSWolfgang Grandegger reg = <3 0x0 0x800>; 2946dd1b64aSWolfgang Grandegger fsl,upm-addr-offset = <0x10>; 2956dd1b64aSWolfgang Grandegger fsl,upm-cmd-offset = <0x08>; 2966dd1b64aSWolfgang Grandegger chip-delay = <25>; // in micro-seconds 2976dd1b64aSWolfgang Grandegger 2986dd1b64aSWolfgang Grandegger nand@0 { 2996dd1b64aSWolfgang Grandegger #address-cells = <1>; 3006dd1b64aSWolfgang Grandegger #size-cells = <1>; 3016dd1b64aSWolfgang Grandegger 3026dd1b64aSWolfgang Grandegger partition@0 { 3036dd1b64aSWolfgang Grandegger label = "fs"; 3046dd1b64aSWolfgang Grandegger reg = <0x00000000 0x01000000>; 3056dd1b64aSWolfgang Grandegger }; 3066dd1b64aSWolfgang Grandegger }; 3076dd1b64aSWolfgang Grandegger }; 3086dd1b64aSWolfgang Grandegger }; 3096dd1b64aSWolfgang Grandegger 3106dd1b64aSWolfgang Grandegger pci0: pci@e0008000 { 3116dd1b64aSWolfgang Grandegger cell-index = <0>; 3126dd1b64aSWolfgang Grandegger #interrupt-cells = <1>; 3136dd1b64aSWolfgang Grandegger #size-cells = <2>; 3146dd1b64aSWolfgang Grandegger #address-cells = <3>; 3156dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 3166dd1b64aSWolfgang Grandegger device_type = "pci"; 3176dd1b64aSWolfgang Grandegger reg = <0xe0008000 0x1000>; 3186dd1b64aSWolfgang Grandegger clock-frequency = <33333333>; 3196dd1b64aSWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 3206dd1b64aSWolfgang Grandegger interrupt-map = < 3216dd1b64aSWolfgang Grandegger /* IDSEL 28 */ 3226dd1b64aSWolfgang Grandegger 0xe000 0 0 1 &mpic 2 1 3236dd1b64aSWolfgang Grandegger 0xe000 0 0 2 &mpic 3 1>; 3246dd1b64aSWolfgang Grandegger 3256dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 3266dd1b64aSWolfgang Grandegger interrupts = <24 2>; 3276dd1b64aSWolfgang Grandegger bus-range = <0 0>; 3286dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 3296dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 3306dd1b64aSWolfgang Grandegger }; 3316dd1b64aSWolfgang Grandegger 3326dd1b64aSWolfgang Grandegger pci1: pcie@e000a000 { 3336dd1b64aSWolfgang Grandegger cell-index = <2>; 3346dd1b64aSWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 3356dd1b64aSWolfgang Grandegger interrupt-map = < 3366dd1b64aSWolfgang Grandegger /* IDSEL 0x0 (PEX) */ 3376dd1b64aSWolfgang Grandegger 0x00000 0 0 1 &mpic 0 1 3386dd1b64aSWolfgang Grandegger 0x00000 0 0 2 &mpic 1 1 3396dd1b64aSWolfgang Grandegger 0x00000 0 0 3 &mpic 2 1 3406dd1b64aSWolfgang Grandegger 0x00000 0 0 4 &mpic 3 1>; 3416dd1b64aSWolfgang Grandegger 3426dd1b64aSWolfgang Grandegger interrupt-parent = <&mpic>; 3436dd1b64aSWolfgang Grandegger interrupts = <26 2>; 3446dd1b64aSWolfgang Grandegger bus-range = <0 0xff>; 3456dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000 3466dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0xef000000 0 0x08000000>; 3476dd1b64aSWolfgang Grandegger clock-frequency = <33333333>; 3486dd1b64aSWolfgang Grandegger #interrupt-cells = <1>; 3496dd1b64aSWolfgang Grandegger #size-cells = <2>; 3506dd1b64aSWolfgang Grandegger #address-cells = <3>; 3516dd1b64aSWolfgang Grandegger reg = <0xe000a000 0x1000>; 3526dd1b64aSWolfgang Grandegger compatible = "fsl,mpc8548-pcie"; 3536dd1b64aSWolfgang Grandegger device_type = "pci"; 3546dd1b64aSWolfgang Grandegger pcie@0 { 3556dd1b64aSWolfgang Grandegger reg = <0 0 0 0 0>; 3566dd1b64aSWolfgang Grandegger #size-cells = <2>; 3576dd1b64aSWolfgang Grandegger #address-cells = <3>; 3586dd1b64aSWolfgang Grandegger device_type = "pci"; 3596dd1b64aSWolfgang Grandegger ranges = <0x02000000 0 0xc0000000 0x02000000 0 3606dd1b64aSWolfgang Grandegger 0xc0000000 0 0x20000000 3616dd1b64aSWolfgang Grandegger 0x01000000 0 0x00000000 0x01000000 0 3626dd1b64aSWolfgang Grandegger 0x00000000 0 0x08000000>; 3636dd1b64aSWolfgang Grandegger }; 3646dd1b64aSWolfgang Grandegger }; 3656dd1b64aSWolfgang Grandegger}; 366