1/*
2 * TQM8548 Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16	model = "tqc,tqm8548";
17	compatible = "tqc,tqm8548";
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	aliases {
22		ethernet0 = &enet0;
23		ethernet1 = &enet1;
24		ethernet2 = &enet2;
25		ethernet3 = &enet3;
26
27		serial0 = &serial0;
28		serial1 = &serial1;
29		pci0 = &pci0;
30		pci1 = &pci1;
31	};
32
33	cpus {
34		#address-cells = <1>;
35		#size-cells = <0>;
36
37		PowerPC,8548@0 {
38			device_type = "cpu";
39			reg = <0>;
40			d-cache-line-size = <32>;	// 32 bytes
41			i-cache-line-size = <32>;	// 32 bytes
42			d-cache-size = <0x8000>;	// L1, 32K
43			i-cache-size = <0x8000>;	// L1, 32K
44			next-level-cache = <&L2>;
45		};
46	};
47
48	memory {
49		device_type = "memory";
50		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
51	};
52
53	soc@a0000000 {
54		#address-cells = <1>;
55		#size-cells = <1>;
56		device_type = "soc";
57		ranges = <0x0 0xa0000000 0x100000>;
58		reg = <0xa0000000 0x1000>;	// CCSRBAR
59		bus-frequency = <0>;
60		compatible = "fsl,mpc8548-immr", "simple-bus";
61
62		ecm-law@0 {
63			compatible = "fsl,ecm-law";
64			reg = <0x0 0x1000>;
65			fsl,num-laws = <10>;
66		};
67
68		ecm@1000 {
69			compatible = "fsl,mpc8548-ecm", "fsl,ecm";
70			reg = <0x1000 0x1000>;
71			interrupts = <17 2>;
72			interrupt-parent = <&mpic>;
73		};
74
75		memory-controller@2000 {
76			compatible = "fsl,mpc8548-memory-controller";
77			reg = <0x2000 0x1000>;
78			interrupt-parent = <&mpic>;
79			interrupts = <18 2>;
80		};
81
82		L2: l2-cache-controller@20000 {
83			compatible = "fsl,mpc8548-l2-cache-controller";
84			reg = <0x20000 0x1000>;
85			cache-line-size = <32>;	// 32 bytes
86			cache-size = <0x80000>;	// L2, 512K
87			interrupt-parent = <&mpic>;
88			interrupts = <16 2>;
89		};
90
91		i2c@3000 {
92			#address-cells = <1>;
93			#size-cells = <0>;
94			cell-index = <0>;
95			compatible = "fsl-i2c";
96			reg = <0x3000 0x100>;
97			interrupts = <43 2>;
98			interrupt-parent = <&mpic>;
99			dfsrr;
100
101			dtt@48 {
102				compatible = "national,lm75";
103				reg = <0x48>;
104			};
105
106			rtc@68 {
107				compatible = "dallas,ds1337";
108				reg = <0x68>;
109			};
110		};
111
112		i2c@3100 {
113			#address-cells = <1>;
114			#size-cells = <0>;
115			cell-index = <1>;
116			compatible = "fsl-i2c";
117			reg = <0x3100 0x100>;
118			interrupts = <43 2>;
119			interrupt-parent = <&mpic>;
120			dfsrr;
121		};
122
123		dma@21300 {
124			#address-cells = <1>;
125			#size-cells = <1>;
126			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
127			reg = <0x21300 0x4>;
128			ranges = <0x0 0x21100 0x200>;
129			cell-index = <0>;
130			dma-channel@0 {
131				compatible = "fsl,mpc8548-dma-channel",
132						"fsl,eloplus-dma-channel";
133				reg = <0x0 0x80>;
134				cell-index = <0>;
135				interrupt-parent = <&mpic>;
136				interrupts = <20 2>;
137			};
138			dma-channel@80 {
139				compatible = "fsl,mpc8548-dma-channel",
140						"fsl,eloplus-dma-channel";
141				reg = <0x80 0x80>;
142				cell-index = <1>;
143				interrupt-parent = <&mpic>;
144				interrupts = <21 2>;
145			};
146			dma-channel@100 {
147				compatible = "fsl,mpc8548-dma-channel",
148						"fsl,eloplus-dma-channel";
149				reg = <0x100 0x80>;
150				cell-index = <2>;
151				interrupt-parent = <&mpic>;
152				interrupts = <22 2>;
153			};
154			dma-channel@180 {
155				compatible = "fsl,mpc8548-dma-channel",
156						"fsl,eloplus-dma-channel";
157				reg = <0x180 0x80>;
158				cell-index = <3>;
159				interrupt-parent = <&mpic>;
160				interrupts = <23 2>;
161			};
162		};
163
164		enet0: ethernet@24000 {
165			#address-cells = <1>;
166			#size-cells = <1>;
167			cell-index = <0>;
168			device_type = "network";
169			model = "eTSEC";
170			compatible = "gianfar";
171			reg = <0x24000 0x1000>;
172			ranges = <0x0 0x24000 0x1000>;
173			local-mac-address = [ 00 00 00 00 00 00 ];
174			interrupts = <29 2 30 2 34 2>;
175			interrupt-parent = <&mpic>;
176			tbi-handle = <&tbi0>;
177			phy-handle = <&phy2>;
178
179			mdio@520 {
180				#address-cells = <1>;
181				#size-cells = <0>;
182				compatible = "fsl,gianfar-mdio";
183				reg = <0x520 0x20>;
184
185				phy1: ethernet-phy@0 {
186					interrupt-parent = <&mpic>;
187					interrupts = <8 1>;
188					reg = <1>;
189					device_type = "ethernet-phy";
190				};
191				phy2: ethernet-phy@1 {
192					interrupt-parent = <&mpic>;
193					interrupts = <8 1>;
194					reg = <2>;
195					device_type = "ethernet-phy";
196				};
197				phy3: ethernet-phy@3 {
198					interrupt-parent = <&mpic>;
199					interrupts = <8 1>;
200					reg = <3>;
201					device_type = "ethernet-phy";
202				};
203				phy4: ethernet-phy@4 {
204					interrupt-parent = <&mpic>;
205					interrupts = <8 1>;
206					reg = <4>;
207					device_type = "ethernet-phy";
208				};
209				phy5: ethernet-phy@5 {
210					interrupt-parent = <&mpic>;
211					interrupts = <8 1>;
212					reg = <5>;
213					device_type = "ethernet-phy";
214				};
215				tbi0: tbi-phy@11 {
216					reg = <0x11>;
217					device_type = "tbi-phy";
218				};
219			};
220		};
221
222		enet1: ethernet@25000 {
223			#address-cells = <1>;
224			#size-cells = <1>;
225			cell-index = <1>;
226			device_type = "network";
227			model = "eTSEC";
228			compatible = "gianfar";
229			reg = <0x25000 0x1000>;
230			ranges = <0x0 0x25000 0x1000>;
231			local-mac-address = [ 00 00 00 00 00 00 ];
232			interrupts = <35 2 36 2 40 2>;
233			interrupt-parent = <&mpic>;
234			tbi-handle = <&tbi1>;
235			phy-handle = <&phy1>;
236
237			mdio@520 {
238				#address-cells = <1>;
239				#size-cells = <0>;
240				compatible = "fsl,gianfar-tbi";
241				reg = <0x520 0x20>;
242
243				tbi1: tbi-phy@11 {
244					reg = <0x11>;
245					device_type = "tbi-phy";
246				};
247			};
248		};
249
250		enet2: ethernet@26000 {
251			#address-cells = <1>;
252			#size-cells = <1>;
253			cell-index = <2>;
254			device_type = "network";
255			model = "eTSEC";
256			compatible = "gianfar";
257			reg = <0x26000 0x1000>;
258			ranges = <0x0 0x26000 0x1000>;
259			local-mac-address = [ 00 00 00 00 00 00 ];
260			interrupts = <31 2 32 2 33 2>;
261			interrupt-parent = <&mpic>;
262			tbi-handle = <&tbi2>;
263			phy-handle = <&phy4>;
264
265			mdio@520 {
266				#address-cells = <1>;
267				#size-cells = <0>;
268				compatible = "fsl,gianfar-tbi";
269				reg = <0x520 0x20>;
270
271				tbi2: tbi-phy@11 {
272					reg = <0x11>;
273					device_type = "tbi-phy";
274				};
275			};
276		};
277
278		enet3: ethernet@27000 {
279			#address-cells = <1>;
280			#size-cells = <1>;
281			cell-index = <3>;
282			device_type = "network";
283			model = "eTSEC";
284			compatible = "gianfar";
285			reg = <0x27000 0x1000>;
286			ranges = <0x0 0x27000 0x1000>;
287			local-mac-address = [ 00 00 00 00 00 00 ];
288			interrupts = <37 2 38 2 39 2>;
289			interrupt-parent = <&mpic>;
290			tbi-handle = <&tbi3>;
291			phy-handle = <&phy5>;
292
293			mdio@520 {
294				#address-cells = <1>;
295				#size-cells = <0>;
296				compatible = "fsl,gianfar-tbi";
297				reg = <0x520 0x20>;
298
299				tbi3: tbi-phy@11 {
300					reg = <0x11>;
301					device_type = "tbi-phy";
302				};
303			};
304		};
305
306		serial0: serial@4500 {
307			cell-index = <0>;
308			device_type = "serial";
309			compatible = "ns16550";
310			reg = <0x4500 0x100>;	// reg base, size
311			clock-frequency = <0>;	// should we fill in in uboot?
312			current-speed = <115200>;
313			interrupts = <42 2>;
314			interrupt-parent = <&mpic>;
315		};
316
317		serial1: serial@4600 {
318			cell-index = <1>;
319			device_type = "serial";
320			compatible = "ns16550";
321			reg = <0x4600 0x100>;	// reg base, size
322			clock-frequency = <0>;	// should we fill in in uboot?
323			current-speed = <115200>;
324			interrupts = <42 2>;
325			interrupt-parent = <&mpic>;
326		};
327
328		global-utilities@e0000 {	// global utilities reg
329			compatible = "fsl,mpc8548-guts";
330			reg = <0xe0000 0x1000>;
331			fsl,has-rstcr;
332		};
333
334		mpic: pic@40000 {
335			interrupt-controller;
336			#address-cells = <0>;
337			#interrupt-cells = <2>;
338			reg = <0x40000 0x40000>;
339			compatible = "chrp,open-pic";
340			device_type = "open-pic";
341		};
342	};
343
344	localbus@a0005000 {
345		compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
346			     "simple-bus";
347		#address-cells = <2>;
348		#size-cells = <1>;
349		reg = <0xa0005000 0x100>;	// BRx, ORx, etc.
350
351		ranges = <
352			0 0x0 0xfc000000 0x04000000	// NOR FLASH bank 1
353			1 0x0 0xf8000000 0x08000000	// NOR FLASH bank 0
354			2 0x0 0xa3000000 0x00008000	// CAN (2 x i82527)
355			3 0x0 0xa3010000 0x00008000	// NAND FLASH
356
357		>;
358
359		flash@1,0 {
360			#address-cells = <1>;
361			#size-cells = <1>;
362			compatible = "cfi-flash";
363			reg = <1 0x0 0x8000000>;
364			bank-width = <4>;
365			device-width = <1>;
366
367			partition@0 {
368				label = "kernel";
369				reg = <0x00000000 0x00200000>;
370			};
371			partition@200000 {
372				label = "root";
373				reg = <0x00200000 0x00300000>;
374			};
375			partition@500000 {
376				label = "user";
377				reg = <0x00500000 0x07a00000>;
378			};
379			partition@7f00000 {
380				label = "env1";
381				reg = <0x07f00000 0x00040000>;
382			};
383			partition@7f40000 {
384				label = "env2";
385				reg = <0x07f40000 0x00040000>;
386			};
387			partition@7f80000 {
388				label = "u-boot";
389				reg = <0x07f80000 0x00080000>;
390				read-only;
391			};
392		};
393
394		/* Note: CAN support needs be enabled in U-Boot */
395		can0@2,0 {
396			compatible = "intel,82527"; // Bosch CC770
397			reg = <2 0x0 0x100>;
398			interrupts = <4 1>;
399			interrupt-parent = <&mpic>;
400		};
401
402		can1@2,100 {
403			compatible = "intel,82527"; // Bosch CC770
404			reg = <2 0x100 0x100>;
405			interrupts = <4 1>;
406			interrupt-parent = <&mpic>;
407		};
408
409		/* Note: NAND support needs to be enabled in U-Boot */
410		upm@3,0 {
411			#address-cells = <0>;
412			#size-cells = <0>;
413			compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
414			reg = <3 0x0 0x800>;
415			fsl,upm-addr-offset = <0x10>;
416			fsl,upm-cmd-offset = <0x08>;
417			/* Micron MT29F8G08FAB multi-chip device */
418			fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
419			fsl,upm-wait-flags = <0x5>;
420			chip-delay = <25>; // in micro-seconds
421
422			nand@0 {
423				#address-cells = <1>;
424				#size-cells = <1>;
425
426				partition@0 {
427					    label = "fs";
428					    reg = <0x00000000 0x10000000>;
429				};
430			};
431		};
432	};
433
434	pci0: pci@a0008000 {
435		#interrupt-cells = <1>;
436		#size-cells = <2>;
437		#address-cells = <3>;
438		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
439		device_type = "pci";
440		reg = <0xa0008000 0x1000>;
441		clock-frequency = <33333333>;
442		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
443		interrupt-map = <
444				/* IDSEL 28 */
445				 0xe000 0 0 1 &mpic 2 1
446				 0xe000 0 0 2 &mpic 3 1>;
447
448		interrupt-parent = <&mpic>;
449		interrupts = <24 2>;
450		bus-range = <0 0>;
451		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
452			  0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
453	};
454
455	pci1: pcie@a000a000 {
456		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
457		interrupt-map = <
458			/* IDSEL 0x0 (PEX) */
459			0x00000 0 0 1 &mpic 0 1
460			0x00000 0 0 2 &mpic 1 1
461			0x00000 0 0 3 &mpic 2 1
462			0x00000 0 0 4 &mpic 3 1>;
463
464		interrupt-parent = <&mpic>;
465		interrupts = <26 2>;
466		bus-range = <0 0xff>;
467		ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
468			  0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
469		clock-frequency = <33333333>;
470		#interrupt-cells = <1>;
471		#size-cells = <2>;
472		#address-cells = <3>;
473		reg = <0xa000a000 0x1000>;
474		compatible = "fsl,mpc8548-pcie";
475		device_type = "pci";
476		pcie@0 {
477			reg = <0 0 0 0 0>;
478			#size-cells = <2>;
479			#address-cells = <3>;
480			device_type = "pci";
481			ranges = <0x02000000 0 0xb0000000 0x02000000 0
482			          0xb0000000 0 0x10000000
483				  0x01000000 0 0x00000000 0x01000000 0
484				  0x00000000 0 0x08000000>;
485		};
486	};
487};
488