102b8a3d1SWolfgang Grandegger/* 202b8a3d1SWolfgang Grandegger * TQM8548 Device Tree Source 302b8a3d1SWolfgang Grandegger * 402b8a3d1SWolfgang Grandegger * Copyright 2006 Freescale Semiconductor Inc. 502b8a3d1SWolfgang Grandegger * Copyright 2008 Wolfgang Grandegger <wg@denx.de> 602b8a3d1SWolfgang Grandegger * 702b8a3d1SWolfgang Grandegger * This program is free software; you can redistribute it and/or modify it 802b8a3d1SWolfgang Grandegger * under the terms of the GNU General Public License as published by the 902b8a3d1SWolfgang Grandegger * Free Software Foundation; either version 2 of the License, or (at your 1002b8a3d1SWolfgang Grandegger * option) any later version. 1102b8a3d1SWolfgang Grandegger */ 1202b8a3d1SWolfgang Grandegger 1302b8a3d1SWolfgang Grandegger/dts-v1/; 1402b8a3d1SWolfgang Grandegger 1502b8a3d1SWolfgang Grandegger/ { 1602b8a3d1SWolfgang Grandegger model = "tqc,tqm8548"; 1702b8a3d1SWolfgang Grandegger compatible = "tqc,tqm8548"; 1802b8a3d1SWolfgang Grandegger #address-cells = <1>; 1902b8a3d1SWolfgang Grandegger #size-cells = <1>; 2002b8a3d1SWolfgang Grandegger 2102b8a3d1SWolfgang Grandegger aliases { 2202b8a3d1SWolfgang Grandegger ethernet0 = &enet0; 2302b8a3d1SWolfgang Grandegger ethernet1 = &enet1; 2402b8a3d1SWolfgang Grandegger ethernet2 = &enet2; 2502b8a3d1SWolfgang Grandegger ethernet3 = &enet3; 2602b8a3d1SWolfgang Grandegger 2702b8a3d1SWolfgang Grandegger serial0 = &serial0; 2802b8a3d1SWolfgang Grandegger serial1 = &serial1; 2902b8a3d1SWolfgang Grandegger pci0 = &pci0; 3002b8a3d1SWolfgang Grandegger pci1 = &pci1; 3102b8a3d1SWolfgang Grandegger }; 3202b8a3d1SWolfgang Grandegger 3302b8a3d1SWolfgang Grandegger cpus { 3402b8a3d1SWolfgang Grandegger #address-cells = <1>; 3502b8a3d1SWolfgang Grandegger #size-cells = <0>; 3602b8a3d1SWolfgang Grandegger 3702b8a3d1SWolfgang Grandegger PowerPC,8548@0 { 3802b8a3d1SWolfgang Grandegger device_type = "cpu"; 3902b8a3d1SWolfgang Grandegger reg = <0>; 4002b8a3d1SWolfgang Grandegger d-cache-line-size = <32>; // 32 bytes 4102b8a3d1SWolfgang Grandegger i-cache-line-size = <32>; // 32 bytes 4202b8a3d1SWolfgang Grandegger d-cache-size = <0x8000>; // L1, 32K 4302b8a3d1SWolfgang Grandegger i-cache-size = <0x8000>; // L1, 32K 4402b8a3d1SWolfgang Grandegger next-level-cache = <&L2>; 4502b8a3d1SWolfgang Grandegger }; 4602b8a3d1SWolfgang Grandegger }; 4702b8a3d1SWolfgang Grandegger 4802b8a3d1SWolfgang Grandegger memory { 4902b8a3d1SWolfgang Grandegger device_type = "memory"; 5002b8a3d1SWolfgang Grandegger reg = <0x00000000 0x00000000>; // Filled in by U-Boot 5102b8a3d1SWolfgang Grandegger }; 5202b8a3d1SWolfgang Grandegger 53d27a736cSWolfgang Grandegger soc@a0000000 { 5402b8a3d1SWolfgang Grandegger #address-cells = <1>; 5502b8a3d1SWolfgang Grandegger #size-cells = <1>; 5602b8a3d1SWolfgang Grandegger device_type = "soc"; 5702b8a3d1SWolfgang Grandegger ranges = <0x0 0xa0000000 0x100000>; 5802b8a3d1SWolfgang Grandegger reg = <0xa0000000 0x1000>; // CCSRBAR 5902b8a3d1SWolfgang Grandegger bus-frequency = <0>; 60d27a736cSWolfgang Grandegger compatible = "fsl,mpc8548-immr", "simple-bus"; 6102b8a3d1SWolfgang Grandegger 62e1a22897SKumar Gala ecm-law@0 { 63e1a22897SKumar Gala compatible = "fsl,ecm-law"; 64e1a22897SKumar Gala reg = <0x0 0x1000>; 65e1a22897SKumar Gala fsl,num-laws = <10>; 66e1a22897SKumar Gala }; 67e1a22897SKumar Gala 68e1a22897SKumar Gala ecm@1000 { 69e1a22897SKumar Gala compatible = "fsl,mpc8548-ecm", "fsl,ecm"; 70e1a22897SKumar Gala reg = <0x1000 0x1000>; 71e1a22897SKumar Gala interrupts = <17 2>; 72e1a22897SKumar Gala interrupt-parent = <&mpic>; 73e1a22897SKumar Gala }; 74e1a22897SKumar Gala 7502b8a3d1SWolfgang Grandegger memory-controller@2000 { 7602b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-memory-controller"; 7702b8a3d1SWolfgang Grandegger reg = <0x2000 0x1000>; 7802b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 7902b8a3d1SWolfgang Grandegger interrupts = <18 2>; 8002b8a3d1SWolfgang Grandegger }; 8102b8a3d1SWolfgang Grandegger 8202b8a3d1SWolfgang Grandegger L2: l2-cache-controller@20000 { 8302b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-l2-cache-controller"; 8402b8a3d1SWolfgang Grandegger reg = <0x20000 0x1000>; 8502b8a3d1SWolfgang Grandegger cache-line-size = <32>; // 32 bytes 8602b8a3d1SWolfgang Grandegger cache-size = <0x80000>; // L2, 512K 8702b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 8802b8a3d1SWolfgang Grandegger interrupts = <16 2>; 8902b8a3d1SWolfgang Grandegger }; 9002b8a3d1SWolfgang Grandegger 9102b8a3d1SWolfgang Grandegger i2c@3000 { 9202b8a3d1SWolfgang Grandegger #address-cells = <1>; 9302b8a3d1SWolfgang Grandegger #size-cells = <0>; 9402b8a3d1SWolfgang Grandegger cell-index = <0>; 9502b8a3d1SWolfgang Grandegger compatible = "fsl-i2c"; 9602b8a3d1SWolfgang Grandegger reg = <0x3000 0x100>; 9702b8a3d1SWolfgang Grandegger interrupts = <43 2>; 9802b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 9902b8a3d1SWolfgang Grandegger dfsrr; 100d27a736cSWolfgang Grandegger 1016467cae3SWolfgang Grandegger dtt@48 { 1020f73a449SWolfgang Grandegger compatible = "national,lm75"; 1036467cae3SWolfgang Grandegger reg = <0x48>; 1040f73a449SWolfgang Grandegger }; 1050f73a449SWolfgang Grandegger 106d27a736cSWolfgang Grandegger rtc@68 { 107d27a736cSWolfgang Grandegger compatible = "dallas,ds1337"; 108d27a736cSWolfgang Grandegger reg = <0x68>; 109d27a736cSWolfgang Grandegger }; 11002b8a3d1SWolfgang Grandegger }; 11102b8a3d1SWolfgang Grandegger 11202b8a3d1SWolfgang Grandegger i2c@3100 { 11302b8a3d1SWolfgang Grandegger #address-cells = <1>; 11402b8a3d1SWolfgang Grandegger #size-cells = <0>; 11502b8a3d1SWolfgang Grandegger cell-index = <1>; 11602b8a3d1SWolfgang Grandegger compatible = "fsl-i2c"; 11702b8a3d1SWolfgang Grandegger reg = <0x3100 0x100>; 11802b8a3d1SWolfgang Grandegger interrupts = <43 2>; 11902b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 12002b8a3d1SWolfgang Grandegger dfsrr; 12102b8a3d1SWolfgang Grandegger }; 12202b8a3d1SWolfgang Grandegger 123dee80553SKumar Gala dma@21300 { 124dee80553SKumar Gala #address-cells = <1>; 125dee80553SKumar Gala #size-cells = <1>; 126dee80553SKumar Gala compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 127dee80553SKumar Gala reg = <0x21300 0x4>; 128dee80553SKumar Gala ranges = <0x0 0x21100 0x200>; 129dee80553SKumar Gala cell-index = <0>; 130dee80553SKumar Gala dma-channel@0 { 131dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 132dee80553SKumar Gala "fsl,eloplus-dma-channel"; 133dee80553SKumar Gala reg = <0x0 0x80>; 134dee80553SKumar Gala cell-index = <0>; 135dee80553SKumar Gala interrupt-parent = <&mpic>; 136dee80553SKumar Gala interrupts = <20 2>; 137dee80553SKumar Gala }; 138dee80553SKumar Gala dma-channel@80 { 139dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 140dee80553SKumar Gala "fsl,eloplus-dma-channel"; 141dee80553SKumar Gala reg = <0x80 0x80>; 142dee80553SKumar Gala cell-index = <1>; 143dee80553SKumar Gala interrupt-parent = <&mpic>; 144dee80553SKumar Gala interrupts = <21 2>; 145dee80553SKumar Gala }; 146dee80553SKumar Gala dma-channel@100 { 147dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 148dee80553SKumar Gala "fsl,eloplus-dma-channel"; 149dee80553SKumar Gala reg = <0x100 0x80>; 150dee80553SKumar Gala cell-index = <2>; 151dee80553SKumar Gala interrupt-parent = <&mpic>; 152dee80553SKumar Gala interrupts = <22 2>; 153dee80553SKumar Gala }; 154dee80553SKumar Gala dma-channel@180 { 155dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 156dee80553SKumar Gala "fsl,eloplus-dma-channel"; 157dee80553SKumar Gala reg = <0x180 0x80>; 158dee80553SKumar Gala cell-index = <3>; 159dee80553SKumar Gala interrupt-parent = <&mpic>; 160dee80553SKumar Gala interrupts = <23 2>; 161dee80553SKumar Gala }; 162dee80553SKumar Gala }; 163dee80553SKumar Gala 16484ba4a58SAnton Vorontsov enet0: ethernet@24000 { 16584ba4a58SAnton Vorontsov #address-cells = <1>; 16684ba4a58SAnton Vorontsov #size-cells = <1>; 16784ba4a58SAnton Vorontsov cell-index = <0>; 16884ba4a58SAnton Vorontsov device_type = "network"; 16984ba4a58SAnton Vorontsov model = "eTSEC"; 17084ba4a58SAnton Vorontsov compatible = "gianfar"; 17184ba4a58SAnton Vorontsov reg = <0x24000 0x1000>; 17284ba4a58SAnton Vorontsov ranges = <0x0 0x24000 0x1000>; 17384ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 17484ba4a58SAnton Vorontsov interrupts = <29 2 30 2 34 2>; 17584ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 17684ba4a58SAnton Vorontsov tbi-handle = <&tbi0>; 17784ba4a58SAnton Vorontsov phy-handle = <&phy2>; 17884ba4a58SAnton Vorontsov 17984ba4a58SAnton Vorontsov mdio@520 { 18002b8a3d1SWolfgang Grandegger #address-cells = <1>; 18102b8a3d1SWolfgang Grandegger #size-cells = <0>; 18202b8a3d1SWolfgang Grandegger compatible = "fsl,gianfar-mdio"; 18384ba4a58SAnton Vorontsov reg = <0x520 0x20>; 18402b8a3d1SWolfgang Grandegger 18502b8a3d1SWolfgang Grandegger phy1: ethernet-phy@0 { 18602b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 18702b8a3d1SWolfgang Grandegger interrupts = <8 1>; 18802b8a3d1SWolfgang Grandegger reg = <1>; 18902b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 19002b8a3d1SWolfgang Grandegger }; 19102b8a3d1SWolfgang Grandegger phy2: ethernet-phy@1 { 19202b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 19302b8a3d1SWolfgang Grandegger interrupts = <8 1>; 19402b8a3d1SWolfgang Grandegger reg = <2>; 19502b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 19602b8a3d1SWolfgang Grandegger }; 19702b8a3d1SWolfgang Grandegger phy3: ethernet-phy@3 { 19802b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 19902b8a3d1SWolfgang Grandegger interrupts = <8 1>; 20002b8a3d1SWolfgang Grandegger reg = <3>; 20102b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 20202b8a3d1SWolfgang Grandegger }; 20302b8a3d1SWolfgang Grandegger phy4: ethernet-phy@4 { 20402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 20502b8a3d1SWolfgang Grandegger interrupts = <8 1>; 20602b8a3d1SWolfgang Grandegger reg = <4>; 20702b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 20802b8a3d1SWolfgang Grandegger }; 20902b8a3d1SWolfgang Grandegger phy5: ethernet-phy@5 { 21002b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 21102b8a3d1SWolfgang Grandegger interrupts = <8 1>; 21202b8a3d1SWolfgang Grandegger reg = <5>; 21302b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 21402b8a3d1SWolfgang Grandegger }; 215b31a1d8bSAndy Fleming tbi0: tbi-phy@11 { 216b31a1d8bSAndy Fleming reg = <0x11>; 217b31a1d8bSAndy Fleming device_type = "tbi-phy"; 218b31a1d8bSAndy Fleming }; 219b31a1d8bSAndy Fleming }; 22084ba4a58SAnton Vorontsov }; 221b31a1d8bSAndy Fleming 22284ba4a58SAnton Vorontsov enet1: ethernet@25000 { 22384ba4a58SAnton Vorontsov #address-cells = <1>; 22484ba4a58SAnton Vorontsov #size-cells = <1>; 22584ba4a58SAnton Vorontsov cell-index = <1>; 22684ba4a58SAnton Vorontsov device_type = "network"; 22784ba4a58SAnton Vorontsov model = "eTSEC"; 22884ba4a58SAnton Vorontsov compatible = "gianfar"; 22984ba4a58SAnton Vorontsov reg = <0x25000 0x1000>; 23084ba4a58SAnton Vorontsov ranges = <0x0 0x25000 0x1000>; 23184ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 23284ba4a58SAnton Vorontsov interrupts = <35 2 36 2 40 2>; 23384ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 23484ba4a58SAnton Vorontsov tbi-handle = <&tbi1>; 23584ba4a58SAnton Vorontsov phy-handle = <&phy1>; 23684ba4a58SAnton Vorontsov 23784ba4a58SAnton Vorontsov mdio@520 { 238b31a1d8bSAndy Fleming #address-cells = <1>; 239b31a1d8bSAndy Fleming #size-cells = <0>; 240b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 24184ba4a58SAnton Vorontsov reg = <0x520 0x20>; 242b31a1d8bSAndy Fleming 243b31a1d8bSAndy Fleming tbi1: tbi-phy@11 { 244b31a1d8bSAndy Fleming reg = <0x11>; 245b31a1d8bSAndy Fleming device_type = "tbi-phy"; 246b31a1d8bSAndy Fleming }; 247b31a1d8bSAndy Fleming }; 24884ba4a58SAnton Vorontsov }; 249b31a1d8bSAndy Fleming 25084ba4a58SAnton Vorontsov enet2: ethernet@26000 { 25184ba4a58SAnton Vorontsov #address-cells = <1>; 25284ba4a58SAnton Vorontsov #size-cells = <1>; 25384ba4a58SAnton Vorontsov cell-index = <2>; 25484ba4a58SAnton Vorontsov device_type = "network"; 25584ba4a58SAnton Vorontsov model = "eTSEC"; 25684ba4a58SAnton Vorontsov compatible = "gianfar"; 25784ba4a58SAnton Vorontsov reg = <0x26000 0x1000>; 25884ba4a58SAnton Vorontsov ranges = <0x0 0x26000 0x1000>; 25984ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 26084ba4a58SAnton Vorontsov interrupts = <31 2 32 2 33 2>; 26184ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 26284ba4a58SAnton Vorontsov tbi-handle = <&tbi2>; 263655544c6SWolfgang Grandegger phy-handle = <&phy4>; 26484ba4a58SAnton Vorontsov 26584ba4a58SAnton Vorontsov mdio@520 { 266b31a1d8bSAndy Fleming #address-cells = <1>; 267b31a1d8bSAndy Fleming #size-cells = <0>; 268b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 26984ba4a58SAnton Vorontsov reg = <0x520 0x20>; 270b31a1d8bSAndy Fleming 271b31a1d8bSAndy Fleming tbi2: tbi-phy@11 { 272b31a1d8bSAndy Fleming reg = <0x11>; 273b31a1d8bSAndy Fleming device_type = "tbi-phy"; 274b31a1d8bSAndy Fleming }; 275b31a1d8bSAndy Fleming }; 27684ba4a58SAnton Vorontsov }; 277b31a1d8bSAndy Fleming 27884ba4a58SAnton Vorontsov enet3: ethernet@27000 { 27984ba4a58SAnton Vorontsov #address-cells = <1>; 28084ba4a58SAnton Vorontsov #size-cells = <1>; 28184ba4a58SAnton Vorontsov cell-index = <3>; 28284ba4a58SAnton Vorontsov device_type = "network"; 28384ba4a58SAnton Vorontsov model = "eTSEC"; 28484ba4a58SAnton Vorontsov compatible = "gianfar"; 28584ba4a58SAnton Vorontsov reg = <0x27000 0x1000>; 28684ba4a58SAnton Vorontsov ranges = <0x0 0x27000 0x1000>; 28784ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 28884ba4a58SAnton Vorontsov interrupts = <37 2 38 2 39 2>; 28984ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 29084ba4a58SAnton Vorontsov tbi-handle = <&tbi3>; 291655544c6SWolfgang Grandegger phy-handle = <&phy5>; 29284ba4a58SAnton Vorontsov 29384ba4a58SAnton Vorontsov mdio@520 { 294b31a1d8bSAndy Fleming #address-cells = <1>; 295b31a1d8bSAndy Fleming #size-cells = <0>; 296b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 29784ba4a58SAnton Vorontsov reg = <0x520 0x20>; 298b31a1d8bSAndy Fleming 299b31a1d8bSAndy Fleming tbi3: tbi-phy@11 { 300b31a1d8bSAndy Fleming reg = <0x11>; 301b31a1d8bSAndy Fleming device_type = "tbi-phy"; 302b31a1d8bSAndy Fleming }; 30302b8a3d1SWolfgang Grandegger }; 30402b8a3d1SWolfgang Grandegger }; 30502b8a3d1SWolfgang Grandegger 30602b8a3d1SWolfgang Grandegger serial0: serial@4500 { 30702b8a3d1SWolfgang Grandegger cell-index = <0>; 30802b8a3d1SWolfgang Grandegger device_type = "serial"; 30902b8a3d1SWolfgang Grandegger compatible = "ns16550"; 31002b8a3d1SWolfgang Grandegger reg = <0x4500 0x100>; // reg base, size 31102b8a3d1SWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 31202b8a3d1SWolfgang Grandegger current-speed = <115200>; 31302b8a3d1SWolfgang Grandegger interrupts = <42 2>; 31402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 31502b8a3d1SWolfgang Grandegger }; 31602b8a3d1SWolfgang Grandegger 31702b8a3d1SWolfgang Grandegger serial1: serial@4600 { 31802b8a3d1SWolfgang Grandegger cell-index = <1>; 31902b8a3d1SWolfgang Grandegger device_type = "serial"; 32002b8a3d1SWolfgang Grandegger compatible = "ns16550"; 32102b8a3d1SWolfgang Grandegger reg = <0x4600 0x100>; // reg base, size 32202b8a3d1SWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 32302b8a3d1SWolfgang Grandegger current-speed = <115200>; 32402b8a3d1SWolfgang Grandegger interrupts = <42 2>; 32502b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 32602b8a3d1SWolfgang Grandegger }; 32702b8a3d1SWolfgang Grandegger 32802b8a3d1SWolfgang Grandegger global-utilities@e0000 { // global utilities reg 32902b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-guts"; 33002b8a3d1SWolfgang Grandegger reg = <0xe0000 0x1000>; 33102b8a3d1SWolfgang Grandegger fsl,has-rstcr; 33202b8a3d1SWolfgang Grandegger }; 33302b8a3d1SWolfgang Grandegger 33402b8a3d1SWolfgang Grandegger mpic: pic@40000 { 33502b8a3d1SWolfgang Grandegger interrupt-controller; 33602b8a3d1SWolfgang Grandegger #address-cells = <0>; 33702b8a3d1SWolfgang Grandegger #interrupt-cells = <2>; 33802b8a3d1SWolfgang Grandegger reg = <0x40000 0x40000>; 33902b8a3d1SWolfgang Grandegger compatible = "chrp,open-pic"; 34002b8a3d1SWolfgang Grandegger device_type = "open-pic"; 34102b8a3d1SWolfgang Grandegger }; 34202b8a3d1SWolfgang Grandegger }; 34302b8a3d1SWolfgang Grandegger 34402b8a3d1SWolfgang Grandegger localbus@a0005000 { 34502b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 34602b8a3d1SWolfgang Grandegger "simple-bus"; 34702b8a3d1SWolfgang Grandegger #address-cells = <2>; 34802b8a3d1SWolfgang Grandegger #size-cells = <1>; 34902b8a3d1SWolfgang Grandegger reg = <0xa0005000 0x100>; // BRx, ORx, etc. 35002b8a3d1SWolfgang Grandegger 35102b8a3d1SWolfgang Grandegger ranges = < 35202b8a3d1SWolfgang Grandegger 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 35302b8a3d1SWolfgang Grandegger 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 35402b8a3d1SWolfgang Grandegger 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527) 35502b8a3d1SWolfgang Grandegger 3 0x0 0xa3010000 0x00008000 // NAND FLASH 35602b8a3d1SWolfgang Grandegger 35702b8a3d1SWolfgang Grandegger >; 35802b8a3d1SWolfgang Grandegger 35902b8a3d1SWolfgang Grandegger flash@1,0 { 36002b8a3d1SWolfgang Grandegger #address-cells = <1>; 36102b8a3d1SWolfgang Grandegger #size-cells = <1>; 36202b8a3d1SWolfgang Grandegger compatible = "cfi-flash"; 36302b8a3d1SWolfgang Grandegger reg = <1 0x0 0x8000000>; 36402b8a3d1SWolfgang Grandegger bank-width = <4>; 36502b8a3d1SWolfgang Grandegger device-width = <1>; 36602b8a3d1SWolfgang Grandegger 36702b8a3d1SWolfgang Grandegger partition@0 { 36802b8a3d1SWolfgang Grandegger label = "kernel"; 36902b8a3d1SWolfgang Grandegger reg = <0x00000000 0x00200000>; 37002b8a3d1SWolfgang Grandegger }; 37102b8a3d1SWolfgang Grandegger partition@200000 { 37202b8a3d1SWolfgang Grandegger label = "root"; 37302b8a3d1SWolfgang Grandegger reg = <0x00200000 0x00300000>; 37402b8a3d1SWolfgang Grandegger }; 37502b8a3d1SWolfgang Grandegger partition@500000 { 37602b8a3d1SWolfgang Grandegger label = "user"; 37702b8a3d1SWolfgang Grandegger reg = <0x00500000 0x07a00000>; 37802b8a3d1SWolfgang Grandegger }; 37902b8a3d1SWolfgang Grandegger partition@7f00000 { 38002b8a3d1SWolfgang Grandegger label = "env1"; 38102b8a3d1SWolfgang Grandegger reg = <0x07f00000 0x00040000>; 38202b8a3d1SWolfgang Grandegger }; 38302b8a3d1SWolfgang Grandegger partition@7f40000 { 38402b8a3d1SWolfgang Grandegger label = "env2"; 38502b8a3d1SWolfgang Grandegger reg = <0x07f40000 0x00040000>; 38602b8a3d1SWolfgang Grandegger }; 38702b8a3d1SWolfgang Grandegger partition@7f80000 { 38802b8a3d1SWolfgang Grandegger label = "u-boot"; 38902b8a3d1SWolfgang Grandegger reg = <0x07f80000 0x00080000>; 39002b8a3d1SWolfgang Grandegger read-only; 39102b8a3d1SWolfgang Grandegger }; 39202b8a3d1SWolfgang Grandegger }; 39302b8a3d1SWolfgang Grandegger 39402b8a3d1SWolfgang Grandegger /* Note: CAN support needs be enabled in U-Boot */ 39502b8a3d1SWolfgang Grandegger can0@2,0 { 39602b8a3d1SWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 39702b8a3d1SWolfgang Grandegger reg = <2 0x0 0x100>; 3987a385241SWolfgang Grandegger interrupts = <4 1>; 39902b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 40002b8a3d1SWolfgang Grandegger }; 40102b8a3d1SWolfgang Grandegger 40202b8a3d1SWolfgang Grandegger can1@2,100 { 40302b8a3d1SWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 40402b8a3d1SWolfgang Grandegger reg = <2 0x100 0x100>; 4057a385241SWolfgang Grandegger interrupts = <4 1>; 40602b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 40702b8a3d1SWolfgang Grandegger }; 40802b8a3d1SWolfgang Grandegger 40902b8a3d1SWolfgang Grandegger /* Note: NAND support needs to be enabled in U-Boot */ 41002b8a3d1SWolfgang Grandegger upm@3,0 { 41102b8a3d1SWolfgang Grandegger #address-cells = <0>; 41202b8a3d1SWolfgang Grandegger #size-cells = <0>; 4137995c7e9SWolfgang Grandegger compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; 41402b8a3d1SWolfgang Grandegger reg = <3 0x0 0x800>; 41502b8a3d1SWolfgang Grandegger fsl,upm-addr-offset = <0x10>; 41602b8a3d1SWolfgang Grandegger fsl,upm-cmd-offset = <0x08>; 4177995c7e9SWolfgang Grandegger /* Micron MT29F8G08FAB multi-chip device */ 4187995c7e9SWolfgang Grandegger fsl,upm-addr-line-cs-offsets = <0x0 0x200>; 4197995c7e9SWolfgang Grandegger fsl,upm-wait-flags = <0x5>; 42002b8a3d1SWolfgang Grandegger chip-delay = <25>; // in micro-seconds 42102b8a3d1SWolfgang Grandegger 42202b8a3d1SWolfgang Grandegger nand@0 { 42302b8a3d1SWolfgang Grandegger #address-cells = <1>; 42402b8a3d1SWolfgang Grandegger #size-cells = <1>; 42502b8a3d1SWolfgang Grandegger 42602b8a3d1SWolfgang Grandegger partition@0 { 42702b8a3d1SWolfgang Grandegger label = "fs"; 4287995c7e9SWolfgang Grandegger reg = <0x00000000 0x10000000>; 42902b8a3d1SWolfgang Grandegger }; 43002b8a3d1SWolfgang Grandegger }; 43102b8a3d1SWolfgang Grandegger }; 43202b8a3d1SWolfgang Grandegger }; 43302b8a3d1SWolfgang Grandegger 43402b8a3d1SWolfgang Grandegger pci0: pci@a0008000 { 43502b8a3d1SWolfgang Grandegger #interrupt-cells = <1>; 43602b8a3d1SWolfgang Grandegger #size-cells = <2>; 43702b8a3d1SWolfgang Grandegger #address-cells = <3>; 43802b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 43902b8a3d1SWolfgang Grandegger device_type = "pci"; 44002b8a3d1SWolfgang Grandegger reg = <0xa0008000 0x1000>; 44102b8a3d1SWolfgang Grandegger clock-frequency = <33333333>; 44202b8a3d1SWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 44302b8a3d1SWolfgang Grandegger interrupt-map = < 44402b8a3d1SWolfgang Grandegger /* IDSEL 28 */ 44502b8a3d1SWolfgang Grandegger 0xe000 0 0 1 &mpic 2 1 44602b8a3d1SWolfgang Grandegger 0xe000 0 0 2 &mpic 3 1>; 44702b8a3d1SWolfgang Grandegger 44802b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 44902b8a3d1SWolfgang Grandegger interrupts = <24 2>; 45002b8a3d1SWolfgang Grandegger bus-range = <0 0>; 45102b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 45202b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>; 45302b8a3d1SWolfgang Grandegger }; 45402b8a3d1SWolfgang Grandegger 45502b8a3d1SWolfgang Grandegger pci1: pcie@a000a000 { 45602b8a3d1SWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 45702b8a3d1SWolfgang Grandegger interrupt-map = < 45802b8a3d1SWolfgang Grandegger /* IDSEL 0x0 (PEX) */ 45902b8a3d1SWolfgang Grandegger 0x00000 0 0 1 &mpic 0 1 46002b8a3d1SWolfgang Grandegger 0x00000 0 0 2 &mpic 1 1 46102b8a3d1SWolfgang Grandegger 0x00000 0 0 3 &mpic 2 1 46202b8a3d1SWolfgang Grandegger 0x00000 0 0 4 &mpic 3 1>; 46302b8a3d1SWolfgang Grandegger 46402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 46502b8a3d1SWolfgang Grandegger interrupts = <26 2>; 46602b8a3d1SWolfgang Grandegger bus-range = <0 0xff>; 46702b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000 46802b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>; 46902b8a3d1SWolfgang Grandegger clock-frequency = <33333333>; 47002b8a3d1SWolfgang Grandegger #interrupt-cells = <1>; 47102b8a3d1SWolfgang Grandegger #size-cells = <2>; 47202b8a3d1SWolfgang Grandegger #address-cells = <3>; 47302b8a3d1SWolfgang Grandegger reg = <0xa000a000 0x1000>; 47402b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-pcie"; 47502b8a3d1SWolfgang Grandegger device_type = "pci"; 47602b8a3d1SWolfgang Grandegger pcie@0 { 47702b8a3d1SWolfgang Grandegger reg = <0 0 0 0 0>; 47802b8a3d1SWolfgang Grandegger #size-cells = <2>; 47902b8a3d1SWolfgang Grandegger #address-cells = <3>; 48002b8a3d1SWolfgang Grandegger device_type = "pci"; 48102b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0xb0000000 0x02000000 0 48202b8a3d1SWolfgang Grandegger 0xb0000000 0 0x10000000 48302b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0x01000000 0 48402b8a3d1SWolfgang Grandegger 0x00000000 0 0x08000000>; 48502b8a3d1SWolfgang Grandegger }; 48602b8a3d1SWolfgang Grandegger }; 48702b8a3d1SWolfgang Grandegger}; 488