102b8a3d1SWolfgang Grandegger/* 202b8a3d1SWolfgang Grandegger * TQM8548 Device Tree Source 302b8a3d1SWolfgang Grandegger * 402b8a3d1SWolfgang Grandegger * Copyright 2006 Freescale Semiconductor Inc. 502b8a3d1SWolfgang Grandegger * Copyright 2008 Wolfgang Grandegger <wg@denx.de> 602b8a3d1SWolfgang Grandegger * 702b8a3d1SWolfgang Grandegger * This program is free software; you can redistribute it and/or modify it 802b8a3d1SWolfgang Grandegger * under the terms of the GNU General Public License as published by the 902b8a3d1SWolfgang Grandegger * Free Software Foundation; either version 2 of the License, or (at your 1002b8a3d1SWolfgang Grandegger * option) any later version. 1102b8a3d1SWolfgang Grandegger */ 1202b8a3d1SWolfgang Grandegger 1302b8a3d1SWolfgang Grandegger/dts-v1/; 1402b8a3d1SWolfgang Grandegger 1502b8a3d1SWolfgang Grandegger/ { 1602b8a3d1SWolfgang Grandegger model = "tqc,tqm8548"; 1702b8a3d1SWolfgang Grandegger compatible = "tqc,tqm8548"; 1802b8a3d1SWolfgang Grandegger #address-cells = <1>; 1902b8a3d1SWolfgang Grandegger #size-cells = <1>; 2002b8a3d1SWolfgang Grandegger 2102b8a3d1SWolfgang Grandegger aliases { 2202b8a3d1SWolfgang Grandegger ethernet0 = &enet0; 2302b8a3d1SWolfgang Grandegger ethernet1 = &enet1; 2402b8a3d1SWolfgang Grandegger ethernet2 = &enet2; 2502b8a3d1SWolfgang Grandegger ethernet3 = &enet3; 2602b8a3d1SWolfgang Grandegger 2702b8a3d1SWolfgang Grandegger serial0 = &serial0; 2802b8a3d1SWolfgang Grandegger serial1 = &serial1; 2902b8a3d1SWolfgang Grandegger pci0 = &pci0; 3002b8a3d1SWolfgang Grandegger pci1 = &pci1; 3102b8a3d1SWolfgang Grandegger }; 3202b8a3d1SWolfgang Grandegger 3302b8a3d1SWolfgang Grandegger cpus { 3402b8a3d1SWolfgang Grandegger #address-cells = <1>; 3502b8a3d1SWolfgang Grandegger #size-cells = <0>; 3602b8a3d1SWolfgang Grandegger 3702b8a3d1SWolfgang Grandegger PowerPC,8548@0 { 3802b8a3d1SWolfgang Grandegger device_type = "cpu"; 3902b8a3d1SWolfgang Grandegger reg = <0>; 4002b8a3d1SWolfgang Grandegger d-cache-line-size = <32>; // 32 bytes 4102b8a3d1SWolfgang Grandegger i-cache-line-size = <32>; // 32 bytes 4202b8a3d1SWolfgang Grandegger d-cache-size = <0x8000>; // L1, 32K 4302b8a3d1SWolfgang Grandegger i-cache-size = <0x8000>; // L1, 32K 4402b8a3d1SWolfgang Grandegger next-level-cache = <&L2>; 4502b8a3d1SWolfgang Grandegger }; 4602b8a3d1SWolfgang Grandegger }; 4702b8a3d1SWolfgang Grandegger 4802b8a3d1SWolfgang Grandegger memory { 4902b8a3d1SWolfgang Grandegger device_type = "memory"; 5002b8a3d1SWolfgang Grandegger reg = <0x00000000 0x00000000>; // Filled in by U-Boot 5102b8a3d1SWolfgang Grandegger }; 5202b8a3d1SWolfgang Grandegger 53d27a736cSWolfgang Grandegger soc@a0000000 { 5402b8a3d1SWolfgang Grandegger #address-cells = <1>; 5502b8a3d1SWolfgang Grandegger #size-cells = <1>; 5602b8a3d1SWolfgang Grandegger device_type = "soc"; 5702b8a3d1SWolfgang Grandegger ranges = <0x0 0xa0000000 0x100000>; 5802b8a3d1SWolfgang Grandegger reg = <0xa0000000 0x1000>; // CCSRBAR 5902b8a3d1SWolfgang Grandegger bus-frequency = <0>; 60d27a736cSWolfgang Grandegger compatible = "fsl,mpc8548-immr", "simple-bus"; 6102b8a3d1SWolfgang Grandegger 6202b8a3d1SWolfgang Grandegger memory-controller@2000 { 6302b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-memory-controller"; 6402b8a3d1SWolfgang Grandegger reg = <0x2000 0x1000>; 6502b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 6602b8a3d1SWolfgang Grandegger interrupts = <18 2>; 6702b8a3d1SWolfgang Grandegger }; 6802b8a3d1SWolfgang Grandegger 6902b8a3d1SWolfgang Grandegger L2: l2-cache-controller@20000 { 7002b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-l2-cache-controller"; 7102b8a3d1SWolfgang Grandegger reg = <0x20000 0x1000>; 7202b8a3d1SWolfgang Grandegger cache-line-size = <32>; // 32 bytes 7302b8a3d1SWolfgang Grandegger cache-size = <0x80000>; // L2, 512K 7402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 7502b8a3d1SWolfgang Grandegger interrupts = <16 2>; 7602b8a3d1SWolfgang Grandegger }; 7702b8a3d1SWolfgang Grandegger 7802b8a3d1SWolfgang Grandegger i2c@3000 { 7902b8a3d1SWolfgang Grandegger #address-cells = <1>; 8002b8a3d1SWolfgang Grandegger #size-cells = <0>; 8102b8a3d1SWolfgang Grandegger cell-index = <0>; 8202b8a3d1SWolfgang Grandegger compatible = "fsl-i2c"; 8302b8a3d1SWolfgang Grandegger reg = <0x3000 0x100>; 8402b8a3d1SWolfgang Grandegger interrupts = <43 2>; 8502b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 8602b8a3d1SWolfgang Grandegger dfsrr; 87d27a736cSWolfgang Grandegger 880f73a449SWolfgang Grandegger dtt@50 { 890f73a449SWolfgang Grandegger compatible = "national,lm75"; 900f73a449SWolfgang Grandegger reg = <0x50>; 910f73a449SWolfgang Grandegger }; 920f73a449SWolfgang Grandegger 93d27a736cSWolfgang Grandegger rtc@68 { 94d27a736cSWolfgang Grandegger compatible = "dallas,ds1337"; 95d27a736cSWolfgang Grandegger reg = <0x68>; 96d27a736cSWolfgang Grandegger }; 9702b8a3d1SWolfgang Grandegger }; 9802b8a3d1SWolfgang Grandegger 9902b8a3d1SWolfgang Grandegger i2c@3100 { 10002b8a3d1SWolfgang Grandegger #address-cells = <1>; 10102b8a3d1SWolfgang Grandegger #size-cells = <0>; 10202b8a3d1SWolfgang Grandegger cell-index = <1>; 10302b8a3d1SWolfgang Grandegger compatible = "fsl-i2c"; 10402b8a3d1SWolfgang Grandegger reg = <0x3100 0x100>; 10502b8a3d1SWolfgang Grandegger interrupts = <43 2>; 10602b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 10702b8a3d1SWolfgang Grandegger dfsrr; 10802b8a3d1SWolfgang Grandegger }; 10902b8a3d1SWolfgang Grandegger 110dee80553SKumar Gala dma@21300 { 111dee80553SKumar Gala #address-cells = <1>; 112dee80553SKumar Gala #size-cells = <1>; 113dee80553SKumar Gala compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 114dee80553SKumar Gala reg = <0x21300 0x4>; 115dee80553SKumar Gala ranges = <0x0 0x21100 0x200>; 116dee80553SKumar Gala cell-index = <0>; 117dee80553SKumar Gala dma-channel@0 { 118dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 119dee80553SKumar Gala "fsl,eloplus-dma-channel"; 120dee80553SKumar Gala reg = <0x0 0x80>; 121dee80553SKumar Gala cell-index = <0>; 122dee80553SKumar Gala interrupt-parent = <&mpic>; 123dee80553SKumar Gala interrupts = <20 2>; 124dee80553SKumar Gala }; 125dee80553SKumar Gala dma-channel@80 { 126dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 127dee80553SKumar Gala "fsl,eloplus-dma-channel"; 128dee80553SKumar Gala reg = <0x80 0x80>; 129dee80553SKumar Gala cell-index = <1>; 130dee80553SKumar Gala interrupt-parent = <&mpic>; 131dee80553SKumar Gala interrupts = <21 2>; 132dee80553SKumar Gala }; 133dee80553SKumar Gala dma-channel@100 { 134dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 135dee80553SKumar Gala "fsl,eloplus-dma-channel"; 136dee80553SKumar Gala reg = <0x100 0x80>; 137dee80553SKumar Gala cell-index = <2>; 138dee80553SKumar Gala interrupt-parent = <&mpic>; 139dee80553SKumar Gala interrupts = <22 2>; 140dee80553SKumar Gala }; 141dee80553SKumar Gala dma-channel@180 { 142dee80553SKumar Gala compatible = "fsl,mpc8548-dma-channel", 143dee80553SKumar Gala "fsl,eloplus-dma-channel"; 144dee80553SKumar Gala reg = <0x180 0x80>; 145dee80553SKumar Gala cell-index = <3>; 146dee80553SKumar Gala interrupt-parent = <&mpic>; 147dee80553SKumar Gala interrupts = <23 2>; 148dee80553SKumar Gala }; 149dee80553SKumar Gala }; 150dee80553SKumar Gala 15102b8a3d1SWolfgang Grandegger mdio@24520 { 15202b8a3d1SWolfgang Grandegger #address-cells = <1>; 15302b8a3d1SWolfgang Grandegger #size-cells = <0>; 15402b8a3d1SWolfgang Grandegger compatible = "fsl,gianfar-mdio"; 15502b8a3d1SWolfgang Grandegger reg = <0x24520 0x20>; 15602b8a3d1SWolfgang Grandegger 15702b8a3d1SWolfgang Grandegger phy1: ethernet-phy@0 { 15802b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 15902b8a3d1SWolfgang Grandegger interrupts = <8 1>; 16002b8a3d1SWolfgang Grandegger reg = <1>; 16102b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 16202b8a3d1SWolfgang Grandegger }; 16302b8a3d1SWolfgang Grandegger phy2: ethernet-phy@1 { 16402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 16502b8a3d1SWolfgang Grandegger interrupts = <8 1>; 16602b8a3d1SWolfgang Grandegger reg = <2>; 16702b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 16802b8a3d1SWolfgang Grandegger }; 16902b8a3d1SWolfgang Grandegger phy3: ethernet-phy@3 { 17002b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 17102b8a3d1SWolfgang Grandegger interrupts = <8 1>; 17202b8a3d1SWolfgang Grandegger reg = <3>; 17302b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 17402b8a3d1SWolfgang Grandegger }; 17502b8a3d1SWolfgang Grandegger phy4: ethernet-phy@4 { 17602b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 17702b8a3d1SWolfgang Grandegger interrupts = <8 1>; 17802b8a3d1SWolfgang Grandegger reg = <4>; 17902b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 18002b8a3d1SWolfgang Grandegger }; 18102b8a3d1SWolfgang Grandegger phy5: ethernet-phy@5 { 18202b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 18302b8a3d1SWolfgang Grandegger interrupts = <8 1>; 18402b8a3d1SWolfgang Grandegger reg = <5>; 18502b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 18602b8a3d1SWolfgang Grandegger }; 187b31a1d8bSAndy Fleming tbi0: tbi-phy@11 { 188b31a1d8bSAndy Fleming reg = <0x11>; 189b31a1d8bSAndy Fleming device_type = "tbi-phy"; 190b31a1d8bSAndy Fleming }; 191b31a1d8bSAndy Fleming }; 192b31a1d8bSAndy Fleming 193b31a1d8bSAndy Fleming mdio@25520 { 194b31a1d8bSAndy Fleming #address-cells = <1>; 195b31a1d8bSAndy Fleming #size-cells = <0>; 196b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 197b31a1d8bSAndy Fleming reg = <0x25520 0x20>; 198b31a1d8bSAndy Fleming 199b31a1d8bSAndy Fleming tbi1: tbi-phy@11 { 200b31a1d8bSAndy Fleming reg = <0x11>; 201b31a1d8bSAndy Fleming device_type = "tbi-phy"; 202b31a1d8bSAndy Fleming }; 203b31a1d8bSAndy Fleming }; 204b31a1d8bSAndy Fleming 205b31a1d8bSAndy Fleming mdio@26520 { 206b31a1d8bSAndy Fleming #address-cells = <1>; 207b31a1d8bSAndy Fleming #size-cells = <0>; 208b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 209b31a1d8bSAndy Fleming reg = <0x26520 0x20>; 210b31a1d8bSAndy Fleming 211b31a1d8bSAndy Fleming tbi2: tbi-phy@11 { 212b31a1d8bSAndy Fleming reg = <0x11>; 213b31a1d8bSAndy Fleming device_type = "tbi-phy"; 214b31a1d8bSAndy Fleming }; 215b31a1d8bSAndy Fleming }; 216b31a1d8bSAndy Fleming 217b31a1d8bSAndy Fleming mdio@27520 { 218b31a1d8bSAndy Fleming #address-cells = <1>; 219b31a1d8bSAndy Fleming #size-cells = <0>; 220b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 221b31a1d8bSAndy Fleming reg = <0x27520 0x20>; 222b31a1d8bSAndy Fleming 223b31a1d8bSAndy Fleming tbi3: tbi-phy@11 { 224b31a1d8bSAndy Fleming reg = <0x11>; 225b31a1d8bSAndy Fleming device_type = "tbi-phy"; 226b31a1d8bSAndy Fleming }; 22702b8a3d1SWolfgang Grandegger }; 22802b8a3d1SWolfgang Grandegger 22902b8a3d1SWolfgang Grandegger enet0: ethernet@24000 { 23002b8a3d1SWolfgang Grandegger cell-index = <0>; 23102b8a3d1SWolfgang Grandegger device_type = "network"; 23202b8a3d1SWolfgang Grandegger model = "eTSEC"; 23302b8a3d1SWolfgang Grandegger compatible = "gianfar"; 23402b8a3d1SWolfgang Grandegger reg = <0x24000 0x1000>; 23502b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 23602b8a3d1SWolfgang Grandegger interrupts = <29 2 30 2 34 2>; 23702b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 238b31a1d8bSAndy Fleming tbi-handle = <&tbi0>; 23902b8a3d1SWolfgang Grandegger phy-handle = <&phy2>; 24002b8a3d1SWolfgang Grandegger }; 24102b8a3d1SWolfgang Grandegger 24202b8a3d1SWolfgang Grandegger enet1: ethernet@25000 { 24302b8a3d1SWolfgang Grandegger cell-index = <1>; 24402b8a3d1SWolfgang Grandegger device_type = "network"; 24502b8a3d1SWolfgang Grandegger model = "eTSEC"; 24602b8a3d1SWolfgang Grandegger compatible = "gianfar"; 24702b8a3d1SWolfgang Grandegger reg = <0x25000 0x1000>; 24802b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 24902b8a3d1SWolfgang Grandegger interrupts = <35 2 36 2 40 2>; 25002b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 251b31a1d8bSAndy Fleming tbi-handle = <&tbi1>; 25202b8a3d1SWolfgang Grandegger phy-handle = <&phy1>; 25302b8a3d1SWolfgang Grandegger }; 25402b8a3d1SWolfgang Grandegger 25502b8a3d1SWolfgang Grandegger enet2: ethernet@26000 { 25602b8a3d1SWolfgang Grandegger cell-index = <2>; 25702b8a3d1SWolfgang Grandegger device_type = "network"; 25802b8a3d1SWolfgang Grandegger model = "eTSEC"; 25902b8a3d1SWolfgang Grandegger compatible = "gianfar"; 26002b8a3d1SWolfgang Grandegger reg = <0x26000 0x1000>; 26102b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 26202b8a3d1SWolfgang Grandegger interrupts = <31 2 32 2 33 2>; 26302b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 264b31a1d8bSAndy Fleming tbi-handle = <&tbi2>; 26502b8a3d1SWolfgang Grandegger phy-handle = <&phy3>; 26602b8a3d1SWolfgang Grandegger }; 26702b8a3d1SWolfgang Grandegger 26802b8a3d1SWolfgang Grandegger enet3: ethernet@27000 { 26902b8a3d1SWolfgang Grandegger cell-index = <3>; 27002b8a3d1SWolfgang Grandegger device_type = "network"; 27102b8a3d1SWolfgang Grandegger model = "eTSEC"; 27202b8a3d1SWolfgang Grandegger compatible = "gianfar"; 27302b8a3d1SWolfgang Grandegger reg = <0x27000 0x1000>; 27402b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 27502b8a3d1SWolfgang Grandegger interrupts = <37 2 38 2 39 2>; 27602b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 277b31a1d8bSAndy Fleming tbi-handle = <&tbi3>; 27802b8a3d1SWolfgang Grandegger phy-handle = <&phy4>; 27902b8a3d1SWolfgang Grandegger }; 28002b8a3d1SWolfgang Grandegger 28102b8a3d1SWolfgang Grandegger serial0: serial@4500 { 28202b8a3d1SWolfgang Grandegger cell-index = <0>; 28302b8a3d1SWolfgang Grandegger device_type = "serial"; 28402b8a3d1SWolfgang Grandegger compatible = "ns16550"; 28502b8a3d1SWolfgang Grandegger reg = <0x4500 0x100>; // reg base, size 28602b8a3d1SWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 28702b8a3d1SWolfgang Grandegger current-speed = <115200>; 28802b8a3d1SWolfgang Grandegger interrupts = <42 2>; 28902b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 29002b8a3d1SWolfgang Grandegger }; 29102b8a3d1SWolfgang Grandegger 29202b8a3d1SWolfgang Grandegger serial1: serial@4600 { 29302b8a3d1SWolfgang Grandegger cell-index = <1>; 29402b8a3d1SWolfgang Grandegger device_type = "serial"; 29502b8a3d1SWolfgang Grandegger compatible = "ns16550"; 29602b8a3d1SWolfgang Grandegger reg = <0x4600 0x100>; // reg base, size 29702b8a3d1SWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 29802b8a3d1SWolfgang Grandegger current-speed = <115200>; 29902b8a3d1SWolfgang Grandegger interrupts = <42 2>; 30002b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 30102b8a3d1SWolfgang Grandegger }; 30202b8a3d1SWolfgang Grandegger 30302b8a3d1SWolfgang Grandegger global-utilities@e0000 { // global utilities reg 30402b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-guts"; 30502b8a3d1SWolfgang Grandegger reg = <0xe0000 0x1000>; 30602b8a3d1SWolfgang Grandegger fsl,has-rstcr; 30702b8a3d1SWolfgang Grandegger }; 30802b8a3d1SWolfgang Grandegger 30902b8a3d1SWolfgang Grandegger mpic: pic@40000 { 31002b8a3d1SWolfgang Grandegger interrupt-controller; 31102b8a3d1SWolfgang Grandegger #address-cells = <0>; 31202b8a3d1SWolfgang Grandegger #interrupt-cells = <2>; 31302b8a3d1SWolfgang Grandegger reg = <0x40000 0x40000>; 31402b8a3d1SWolfgang Grandegger compatible = "chrp,open-pic"; 31502b8a3d1SWolfgang Grandegger device_type = "open-pic"; 31602b8a3d1SWolfgang Grandegger }; 31702b8a3d1SWolfgang Grandegger }; 31802b8a3d1SWolfgang Grandegger 31902b8a3d1SWolfgang Grandegger localbus@a0005000 { 32002b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 32102b8a3d1SWolfgang Grandegger "simple-bus"; 32202b8a3d1SWolfgang Grandegger #address-cells = <2>; 32302b8a3d1SWolfgang Grandegger #size-cells = <1>; 32402b8a3d1SWolfgang Grandegger reg = <0xa0005000 0x100>; // BRx, ORx, etc. 32502b8a3d1SWolfgang Grandegger 32602b8a3d1SWolfgang Grandegger ranges = < 32702b8a3d1SWolfgang Grandegger 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 32802b8a3d1SWolfgang Grandegger 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 32902b8a3d1SWolfgang Grandegger 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527) 33002b8a3d1SWolfgang Grandegger 3 0x0 0xa3010000 0x00008000 // NAND FLASH 33102b8a3d1SWolfgang Grandegger 33202b8a3d1SWolfgang Grandegger >; 33302b8a3d1SWolfgang Grandegger 33402b8a3d1SWolfgang Grandegger flash@1,0 { 33502b8a3d1SWolfgang Grandegger #address-cells = <1>; 33602b8a3d1SWolfgang Grandegger #size-cells = <1>; 33702b8a3d1SWolfgang Grandegger compatible = "cfi-flash"; 33802b8a3d1SWolfgang Grandegger reg = <1 0x0 0x8000000>; 33902b8a3d1SWolfgang Grandegger bank-width = <4>; 34002b8a3d1SWolfgang Grandegger device-width = <1>; 34102b8a3d1SWolfgang Grandegger 34202b8a3d1SWolfgang Grandegger partition@0 { 34302b8a3d1SWolfgang Grandegger label = "kernel"; 34402b8a3d1SWolfgang Grandegger reg = <0x00000000 0x00200000>; 34502b8a3d1SWolfgang Grandegger }; 34602b8a3d1SWolfgang Grandegger partition@200000 { 34702b8a3d1SWolfgang Grandegger label = "root"; 34802b8a3d1SWolfgang Grandegger reg = <0x00200000 0x00300000>; 34902b8a3d1SWolfgang Grandegger }; 35002b8a3d1SWolfgang Grandegger partition@500000 { 35102b8a3d1SWolfgang Grandegger label = "user"; 35202b8a3d1SWolfgang Grandegger reg = <0x00500000 0x07a00000>; 35302b8a3d1SWolfgang Grandegger }; 35402b8a3d1SWolfgang Grandegger partition@7f00000 { 35502b8a3d1SWolfgang Grandegger label = "env1"; 35602b8a3d1SWolfgang Grandegger reg = <0x07f00000 0x00040000>; 35702b8a3d1SWolfgang Grandegger }; 35802b8a3d1SWolfgang Grandegger partition@7f40000 { 35902b8a3d1SWolfgang Grandegger label = "env2"; 36002b8a3d1SWolfgang Grandegger reg = <0x07f40000 0x00040000>; 36102b8a3d1SWolfgang Grandegger }; 36202b8a3d1SWolfgang Grandegger partition@7f80000 { 36302b8a3d1SWolfgang Grandegger label = "u-boot"; 36402b8a3d1SWolfgang Grandegger reg = <0x07f80000 0x00080000>; 36502b8a3d1SWolfgang Grandegger read-only; 36602b8a3d1SWolfgang Grandegger }; 36702b8a3d1SWolfgang Grandegger }; 36802b8a3d1SWolfgang Grandegger 36902b8a3d1SWolfgang Grandegger /* Note: CAN support needs be enabled in U-Boot */ 37002b8a3d1SWolfgang Grandegger can0@2,0 { 37102b8a3d1SWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 37202b8a3d1SWolfgang Grandegger reg = <2 0x0 0x100>; 3737a385241SWolfgang Grandegger interrupts = <4 1>; 37402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 37502b8a3d1SWolfgang Grandegger }; 37602b8a3d1SWolfgang Grandegger 37702b8a3d1SWolfgang Grandegger can1@2,100 { 37802b8a3d1SWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 37902b8a3d1SWolfgang Grandegger reg = <2 0x100 0x100>; 3807a385241SWolfgang Grandegger interrupts = <4 1>; 38102b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 38202b8a3d1SWolfgang Grandegger }; 38302b8a3d1SWolfgang Grandegger 38402b8a3d1SWolfgang Grandegger /* Note: NAND support needs to be enabled in U-Boot */ 38502b8a3d1SWolfgang Grandegger upm@3,0 { 38602b8a3d1SWolfgang Grandegger #address-cells = <0>; 38702b8a3d1SWolfgang Grandegger #size-cells = <0>; 38802b8a3d1SWolfgang Grandegger compatible = "fsl,upm-nand"; 38902b8a3d1SWolfgang Grandegger reg = <3 0x0 0x800>; 39002b8a3d1SWolfgang Grandegger fsl,upm-addr-offset = <0x10>; 39102b8a3d1SWolfgang Grandegger fsl,upm-cmd-offset = <0x08>; 39202b8a3d1SWolfgang Grandegger chip-delay = <25>; // in micro-seconds 39302b8a3d1SWolfgang Grandegger 39402b8a3d1SWolfgang Grandegger nand@0 { 39502b8a3d1SWolfgang Grandegger #address-cells = <1>; 39602b8a3d1SWolfgang Grandegger #size-cells = <1>; 39702b8a3d1SWolfgang Grandegger 39802b8a3d1SWolfgang Grandegger partition@0 { 39902b8a3d1SWolfgang Grandegger label = "fs"; 40002b8a3d1SWolfgang Grandegger reg = <0x00000000 0x01000000>; 40102b8a3d1SWolfgang Grandegger }; 40202b8a3d1SWolfgang Grandegger }; 40302b8a3d1SWolfgang Grandegger }; 40402b8a3d1SWolfgang Grandegger }; 40502b8a3d1SWolfgang Grandegger 40602b8a3d1SWolfgang Grandegger pci0: pci@a0008000 { 40702b8a3d1SWolfgang Grandegger cell-index = <0>; 40802b8a3d1SWolfgang Grandegger #interrupt-cells = <1>; 40902b8a3d1SWolfgang Grandegger #size-cells = <2>; 41002b8a3d1SWolfgang Grandegger #address-cells = <3>; 41102b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 41202b8a3d1SWolfgang Grandegger device_type = "pci"; 41302b8a3d1SWolfgang Grandegger reg = <0xa0008000 0x1000>; 41402b8a3d1SWolfgang Grandegger clock-frequency = <33333333>; 41502b8a3d1SWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 41602b8a3d1SWolfgang Grandegger interrupt-map = < 41702b8a3d1SWolfgang Grandegger /* IDSEL 28 */ 41802b8a3d1SWolfgang Grandegger 0xe000 0 0 1 &mpic 2 1 41902b8a3d1SWolfgang Grandegger 0xe000 0 0 2 &mpic 3 1>; 42002b8a3d1SWolfgang Grandegger 42102b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 42202b8a3d1SWolfgang Grandegger interrupts = <24 2>; 42302b8a3d1SWolfgang Grandegger bus-range = <0 0>; 42402b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 42502b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>; 42602b8a3d1SWolfgang Grandegger }; 42702b8a3d1SWolfgang Grandegger 42802b8a3d1SWolfgang Grandegger pci1: pcie@a000a000 { 42902b8a3d1SWolfgang Grandegger cell-index = <2>; 43002b8a3d1SWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 43102b8a3d1SWolfgang Grandegger interrupt-map = < 43202b8a3d1SWolfgang Grandegger /* IDSEL 0x0 (PEX) */ 43302b8a3d1SWolfgang Grandegger 0x00000 0 0 1 &mpic 0 1 43402b8a3d1SWolfgang Grandegger 0x00000 0 0 2 &mpic 1 1 43502b8a3d1SWolfgang Grandegger 0x00000 0 0 3 &mpic 2 1 43602b8a3d1SWolfgang Grandegger 0x00000 0 0 4 &mpic 3 1>; 43702b8a3d1SWolfgang Grandegger 43802b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 43902b8a3d1SWolfgang Grandegger interrupts = <26 2>; 44002b8a3d1SWolfgang Grandegger bus-range = <0 0xff>; 44102b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000 44202b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>; 44302b8a3d1SWolfgang Grandegger clock-frequency = <33333333>; 44402b8a3d1SWolfgang Grandegger #interrupt-cells = <1>; 44502b8a3d1SWolfgang Grandegger #size-cells = <2>; 44602b8a3d1SWolfgang Grandegger #address-cells = <3>; 44702b8a3d1SWolfgang Grandegger reg = <0xa000a000 0x1000>; 44802b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-pcie"; 44902b8a3d1SWolfgang Grandegger device_type = "pci"; 45002b8a3d1SWolfgang Grandegger pcie@0 { 45102b8a3d1SWolfgang Grandegger reg = <0 0 0 0 0>; 45202b8a3d1SWolfgang Grandegger #size-cells = <2>; 45302b8a3d1SWolfgang Grandegger #address-cells = <3>; 45402b8a3d1SWolfgang Grandegger device_type = "pci"; 45502b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0xb0000000 0x02000000 0 45602b8a3d1SWolfgang Grandegger 0xb0000000 0 0x10000000 45702b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0x01000000 0 45802b8a3d1SWolfgang Grandegger 0x00000000 0 0x08000000>; 45902b8a3d1SWolfgang Grandegger }; 46002b8a3d1SWolfgang Grandegger }; 46102b8a3d1SWolfgang Grandegger}; 462