102b8a3d1SWolfgang Grandegger/* 202b8a3d1SWolfgang Grandegger * TQM8548 Device Tree Source 302b8a3d1SWolfgang Grandegger * 402b8a3d1SWolfgang Grandegger * Copyright 2006 Freescale Semiconductor Inc. 502b8a3d1SWolfgang Grandegger * Copyright 2008 Wolfgang Grandegger <wg@denx.de> 602b8a3d1SWolfgang Grandegger * 702b8a3d1SWolfgang Grandegger * This program is free software; you can redistribute it and/or modify it 802b8a3d1SWolfgang Grandegger * under the terms of the GNU General Public License as published by the 902b8a3d1SWolfgang Grandegger * Free Software Foundation; either version 2 of the License, or (at your 1002b8a3d1SWolfgang Grandegger * option) any later version. 1102b8a3d1SWolfgang Grandegger */ 1202b8a3d1SWolfgang Grandegger 1302b8a3d1SWolfgang Grandegger/dts-v1/; 1402b8a3d1SWolfgang Grandegger 1502b8a3d1SWolfgang Grandegger/ { 1602b8a3d1SWolfgang Grandegger model = "tqc,tqm8548"; 1702b8a3d1SWolfgang Grandegger compatible = "tqc,tqm8548"; 1802b8a3d1SWolfgang Grandegger #address-cells = <1>; 1902b8a3d1SWolfgang Grandegger #size-cells = <1>; 2002b8a3d1SWolfgang Grandegger 2102b8a3d1SWolfgang Grandegger aliases { 2202b8a3d1SWolfgang Grandegger ethernet0 = &enet0; 2302b8a3d1SWolfgang Grandegger ethernet1 = &enet1; 2402b8a3d1SWolfgang Grandegger ethernet2 = &enet2; 2502b8a3d1SWolfgang Grandegger ethernet3 = &enet3; 2602b8a3d1SWolfgang Grandegger 2702b8a3d1SWolfgang Grandegger serial0 = &serial0; 2802b8a3d1SWolfgang Grandegger serial1 = &serial1; 2902b8a3d1SWolfgang Grandegger pci0 = &pci0; 3002b8a3d1SWolfgang Grandegger pci1 = &pci1; 3102b8a3d1SWolfgang Grandegger }; 3202b8a3d1SWolfgang Grandegger 3302b8a3d1SWolfgang Grandegger cpus { 3402b8a3d1SWolfgang Grandegger #address-cells = <1>; 3502b8a3d1SWolfgang Grandegger #size-cells = <0>; 3602b8a3d1SWolfgang Grandegger 3702b8a3d1SWolfgang Grandegger PowerPC,8548@0 { 3802b8a3d1SWolfgang Grandegger device_type = "cpu"; 3902b8a3d1SWolfgang Grandegger reg = <0>; 4002b8a3d1SWolfgang Grandegger d-cache-line-size = <32>; // 32 bytes 4102b8a3d1SWolfgang Grandegger i-cache-line-size = <32>; // 32 bytes 4202b8a3d1SWolfgang Grandegger d-cache-size = <0x8000>; // L1, 32K 4302b8a3d1SWolfgang Grandegger i-cache-size = <0x8000>; // L1, 32K 4402b8a3d1SWolfgang Grandegger next-level-cache = <&L2>; 4502b8a3d1SWolfgang Grandegger }; 4602b8a3d1SWolfgang Grandegger }; 4702b8a3d1SWolfgang Grandegger 4802b8a3d1SWolfgang Grandegger memory { 4902b8a3d1SWolfgang Grandegger device_type = "memory"; 5002b8a3d1SWolfgang Grandegger reg = <0x00000000 0x00000000>; // Filled in by U-Boot 5102b8a3d1SWolfgang Grandegger }; 5202b8a3d1SWolfgang Grandegger 5302b8a3d1SWolfgang Grandegger soc8548@a0000000 { 5402b8a3d1SWolfgang Grandegger #address-cells = <1>; 5502b8a3d1SWolfgang Grandegger #size-cells = <1>; 5602b8a3d1SWolfgang Grandegger device_type = "soc"; 5702b8a3d1SWolfgang Grandegger ranges = <0x0 0xa0000000 0x100000>; 5802b8a3d1SWolfgang Grandegger reg = <0xa0000000 0x1000>; // CCSRBAR 5902b8a3d1SWolfgang Grandegger bus-frequency = <0>; 6002b8a3d1SWolfgang Grandegger 6102b8a3d1SWolfgang Grandegger memory-controller@2000 { 6202b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-memory-controller"; 6302b8a3d1SWolfgang Grandegger reg = <0x2000 0x1000>; 6402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 6502b8a3d1SWolfgang Grandegger interrupts = <18 2>; 6602b8a3d1SWolfgang Grandegger }; 6702b8a3d1SWolfgang Grandegger 6802b8a3d1SWolfgang Grandegger L2: l2-cache-controller@20000 { 6902b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-l2-cache-controller"; 7002b8a3d1SWolfgang Grandegger reg = <0x20000 0x1000>; 7102b8a3d1SWolfgang Grandegger cache-line-size = <32>; // 32 bytes 7202b8a3d1SWolfgang Grandegger cache-size = <0x80000>; // L2, 512K 7302b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 7402b8a3d1SWolfgang Grandegger interrupts = <16 2>; 7502b8a3d1SWolfgang Grandegger }; 7602b8a3d1SWolfgang Grandegger 7702b8a3d1SWolfgang Grandegger i2c@3000 { 7802b8a3d1SWolfgang Grandegger #address-cells = <1>; 7902b8a3d1SWolfgang Grandegger #size-cells = <0>; 8002b8a3d1SWolfgang Grandegger cell-index = <0>; 8102b8a3d1SWolfgang Grandegger compatible = "fsl-i2c"; 8202b8a3d1SWolfgang Grandegger reg = <0x3000 0x100>; 8302b8a3d1SWolfgang Grandegger interrupts = <43 2>; 8402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 8502b8a3d1SWolfgang Grandegger dfsrr; 8602b8a3d1SWolfgang Grandegger }; 8702b8a3d1SWolfgang Grandegger 8802b8a3d1SWolfgang Grandegger i2c@3100 { 8902b8a3d1SWolfgang Grandegger #address-cells = <1>; 9002b8a3d1SWolfgang Grandegger #size-cells = <0>; 9102b8a3d1SWolfgang Grandegger cell-index = <1>; 9202b8a3d1SWolfgang Grandegger compatible = "fsl-i2c"; 9302b8a3d1SWolfgang Grandegger reg = <0x3100 0x100>; 9402b8a3d1SWolfgang Grandegger interrupts = <43 2>; 9502b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 9602b8a3d1SWolfgang Grandegger dfsrr; 9702b8a3d1SWolfgang Grandegger }; 9802b8a3d1SWolfgang Grandegger 9902b8a3d1SWolfgang Grandegger mdio@24520 { 10002b8a3d1SWolfgang Grandegger #address-cells = <1>; 10102b8a3d1SWolfgang Grandegger #size-cells = <0>; 10202b8a3d1SWolfgang Grandegger compatible = "fsl,gianfar-mdio"; 10302b8a3d1SWolfgang Grandegger reg = <0x24520 0x20>; 10402b8a3d1SWolfgang Grandegger 10502b8a3d1SWolfgang Grandegger phy1: ethernet-phy@0 { 10602b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 10702b8a3d1SWolfgang Grandegger interrupts = <8 1>; 10802b8a3d1SWolfgang Grandegger reg = <1>; 10902b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 11002b8a3d1SWolfgang Grandegger }; 11102b8a3d1SWolfgang Grandegger phy2: ethernet-phy@1 { 11202b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 11302b8a3d1SWolfgang Grandegger interrupts = <8 1>; 11402b8a3d1SWolfgang Grandegger reg = <2>; 11502b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 11602b8a3d1SWolfgang Grandegger }; 11702b8a3d1SWolfgang Grandegger phy3: ethernet-phy@3 { 11802b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 11902b8a3d1SWolfgang Grandegger interrupts = <8 1>; 12002b8a3d1SWolfgang Grandegger reg = <3>; 12102b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 12202b8a3d1SWolfgang Grandegger }; 12302b8a3d1SWolfgang Grandegger phy4: ethernet-phy@4 { 12402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 12502b8a3d1SWolfgang Grandegger interrupts = <8 1>; 12602b8a3d1SWolfgang Grandegger reg = <4>; 12702b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 12802b8a3d1SWolfgang Grandegger }; 12902b8a3d1SWolfgang Grandegger phy5: ethernet-phy@5 { 13002b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 13102b8a3d1SWolfgang Grandegger interrupts = <8 1>; 13202b8a3d1SWolfgang Grandegger reg = <5>; 13302b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 13402b8a3d1SWolfgang Grandegger }; 13502b8a3d1SWolfgang Grandegger }; 13602b8a3d1SWolfgang Grandegger 13702b8a3d1SWolfgang Grandegger enet0: ethernet@24000 { 13802b8a3d1SWolfgang Grandegger cell-index = <0>; 13902b8a3d1SWolfgang Grandegger device_type = "network"; 14002b8a3d1SWolfgang Grandegger model = "eTSEC"; 14102b8a3d1SWolfgang Grandegger compatible = "gianfar"; 14202b8a3d1SWolfgang Grandegger reg = <0x24000 0x1000>; 14302b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 14402b8a3d1SWolfgang Grandegger interrupts = <29 2 30 2 34 2>; 14502b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 14602b8a3d1SWolfgang Grandegger phy-handle = <&phy2>; 14702b8a3d1SWolfgang Grandegger }; 14802b8a3d1SWolfgang Grandegger 14902b8a3d1SWolfgang Grandegger enet1: ethernet@25000 { 15002b8a3d1SWolfgang Grandegger cell-index = <1>; 15102b8a3d1SWolfgang Grandegger device_type = "network"; 15202b8a3d1SWolfgang Grandegger model = "eTSEC"; 15302b8a3d1SWolfgang Grandegger compatible = "gianfar"; 15402b8a3d1SWolfgang Grandegger reg = <0x25000 0x1000>; 15502b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 15602b8a3d1SWolfgang Grandegger interrupts = <35 2 36 2 40 2>; 15702b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 15802b8a3d1SWolfgang Grandegger phy-handle = <&phy1>; 15902b8a3d1SWolfgang Grandegger }; 16002b8a3d1SWolfgang Grandegger 16102b8a3d1SWolfgang Grandegger enet2: ethernet@26000 { 16202b8a3d1SWolfgang Grandegger cell-index = <2>; 16302b8a3d1SWolfgang Grandegger device_type = "network"; 16402b8a3d1SWolfgang Grandegger model = "eTSEC"; 16502b8a3d1SWolfgang Grandegger compatible = "gianfar"; 16602b8a3d1SWolfgang Grandegger reg = <0x26000 0x1000>; 16702b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 16802b8a3d1SWolfgang Grandegger interrupts = <31 2 32 2 33 2>; 16902b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 17002b8a3d1SWolfgang Grandegger phy-handle = <&phy3>; 17102b8a3d1SWolfgang Grandegger }; 17202b8a3d1SWolfgang Grandegger 17302b8a3d1SWolfgang Grandegger enet3: ethernet@27000 { 17402b8a3d1SWolfgang Grandegger cell-index = <3>; 17502b8a3d1SWolfgang Grandegger device_type = "network"; 17602b8a3d1SWolfgang Grandegger model = "eTSEC"; 17702b8a3d1SWolfgang Grandegger compatible = "gianfar"; 17802b8a3d1SWolfgang Grandegger reg = <0x27000 0x1000>; 17902b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 18002b8a3d1SWolfgang Grandegger interrupts = <37 2 38 2 39 2>; 18102b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 18202b8a3d1SWolfgang Grandegger phy-handle = <&phy4>; 18302b8a3d1SWolfgang Grandegger }; 18402b8a3d1SWolfgang Grandegger 18502b8a3d1SWolfgang Grandegger serial0: serial@4500 { 18602b8a3d1SWolfgang Grandegger cell-index = <0>; 18702b8a3d1SWolfgang Grandegger device_type = "serial"; 18802b8a3d1SWolfgang Grandegger compatible = "ns16550"; 18902b8a3d1SWolfgang Grandegger reg = <0x4500 0x100>; // reg base, size 19002b8a3d1SWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 19102b8a3d1SWolfgang Grandegger current-speed = <115200>; 19202b8a3d1SWolfgang Grandegger interrupts = <42 2>; 19302b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 19402b8a3d1SWolfgang Grandegger }; 19502b8a3d1SWolfgang Grandegger 19602b8a3d1SWolfgang Grandegger serial1: serial@4600 { 19702b8a3d1SWolfgang Grandegger cell-index = <1>; 19802b8a3d1SWolfgang Grandegger device_type = "serial"; 19902b8a3d1SWolfgang Grandegger compatible = "ns16550"; 20002b8a3d1SWolfgang Grandegger reg = <0x4600 0x100>; // reg base, size 20102b8a3d1SWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 20202b8a3d1SWolfgang Grandegger current-speed = <115200>; 20302b8a3d1SWolfgang Grandegger interrupts = <42 2>; 20402b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 20502b8a3d1SWolfgang Grandegger }; 20602b8a3d1SWolfgang Grandegger 20702b8a3d1SWolfgang Grandegger global-utilities@e0000 { // global utilities reg 20802b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-guts"; 20902b8a3d1SWolfgang Grandegger reg = <0xe0000 0x1000>; 21002b8a3d1SWolfgang Grandegger fsl,has-rstcr; 21102b8a3d1SWolfgang Grandegger }; 21202b8a3d1SWolfgang Grandegger 21302b8a3d1SWolfgang Grandegger mpic: pic@40000 { 21402b8a3d1SWolfgang Grandegger interrupt-controller; 21502b8a3d1SWolfgang Grandegger #address-cells = <0>; 21602b8a3d1SWolfgang Grandegger #interrupt-cells = <2>; 21702b8a3d1SWolfgang Grandegger reg = <0x40000 0x40000>; 21802b8a3d1SWolfgang Grandegger compatible = "chrp,open-pic"; 21902b8a3d1SWolfgang Grandegger device_type = "open-pic"; 22002b8a3d1SWolfgang Grandegger }; 22102b8a3d1SWolfgang Grandegger }; 22202b8a3d1SWolfgang Grandegger 22302b8a3d1SWolfgang Grandegger localbus@a0005000 { 22402b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 22502b8a3d1SWolfgang Grandegger "simple-bus"; 22602b8a3d1SWolfgang Grandegger #address-cells = <2>; 22702b8a3d1SWolfgang Grandegger #size-cells = <1>; 22802b8a3d1SWolfgang Grandegger reg = <0xa0005000 0x100>; // BRx, ORx, etc. 22902b8a3d1SWolfgang Grandegger 23002b8a3d1SWolfgang Grandegger ranges = < 23102b8a3d1SWolfgang Grandegger 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 23202b8a3d1SWolfgang Grandegger 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 23302b8a3d1SWolfgang Grandegger 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527) 23402b8a3d1SWolfgang Grandegger 3 0x0 0xa3010000 0x00008000 // NAND FLASH 23502b8a3d1SWolfgang Grandegger 23602b8a3d1SWolfgang Grandegger >; 23702b8a3d1SWolfgang Grandegger 23802b8a3d1SWolfgang Grandegger flash@1,0 { 23902b8a3d1SWolfgang Grandegger #address-cells = <1>; 24002b8a3d1SWolfgang Grandegger #size-cells = <1>; 24102b8a3d1SWolfgang Grandegger compatible = "cfi-flash"; 24202b8a3d1SWolfgang Grandegger reg = <1 0x0 0x8000000>; 24302b8a3d1SWolfgang Grandegger bank-width = <4>; 24402b8a3d1SWolfgang Grandegger device-width = <1>; 24502b8a3d1SWolfgang Grandegger 24602b8a3d1SWolfgang Grandegger partition@0 { 24702b8a3d1SWolfgang Grandegger label = "kernel"; 24802b8a3d1SWolfgang Grandegger reg = <0x00000000 0x00200000>; 24902b8a3d1SWolfgang Grandegger }; 25002b8a3d1SWolfgang Grandegger partition@200000 { 25102b8a3d1SWolfgang Grandegger label = "root"; 25202b8a3d1SWolfgang Grandegger reg = <0x00200000 0x00300000>; 25302b8a3d1SWolfgang Grandegger }; 25402b8a3d1SWolfgang Grandegger partition@500000 { 25502b8a3d1SWolfgang Grandegger label = "user"; 25602b8a3d1SWolfgang Grandegger reg = <0x00500000 0x07a00000>; 25702b8a3d1SWolfgang Grandegger }; 25802b8a3d1SWolfgang Grandegger partition@7f00000 { 25902b8a3d1SWolfgang Grandegger label = "env1"; 26002b8a3d1SWolfgang Grandegger reg = <0x07f00000 0x00040000>; 26102b8a3d1SWolfgang Grandegger }; 26202b8a3d1SWolfgang Grandegger partition@7f40000 { 26302b8a3d1SWolfgang Grandegger label = "env2"; 26402b8a3d1SWolfgang Grandegger reg = <0x07f40000 0x00040000>; 26502b8a3d1SWolfgang Grandegger }; 26602b8a3d1SWolfgang Grandegger partition@7f80000 { 26702b8a3d1SWolfgang Grandegger label = "u-boot"; 26802b8a3d1SWolfgang Grandegger reg = <0x07f80000 0x00080000>; 26902b8a3d1SWolfgang Grandegger read-only; 27002b8a3d1SWolfgang Grandegger }; 27102b8a3d1SWolfgang Grandegger }; 27202b8a3d1SWolfgang Grandegger 27302b8a3d1SWolfgang Grandegger /* Note: CAN support needs be enabled in U-Boot */ 27402b8a3d1SWolfgang Grandegger can0@2,0 { 27502b8a3d1SWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 27602b8a3d1SWolfgang Grandegger reg = <2 0x0 0x100>; 27702b8a3d1SWolfgang Grandegger interrupts = <4 0>; 27802b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 27902b8a3d1SWolfgang Grandegger }; 28002b8a3d1SWolfgang Grandegger 28102b8a3d1SWolfgang Grandegger can1@2,100 { 28202b8a3d1SWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 28302b8a3d1SWolfgang Grandegger reg = <2 0x100 0x100>; 28402b8a3d1SWolfgang Grandegger interrupts = <4 0>; 28502b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 28602b8a3d1SWolfgang Grandegger }; 28702b8a3d1SWolfgang Grandegger 28802b8a3d1SWolfgang Grandegger /* Note: NAND support needs to be enabled in U-Boot */ 28902b8a3d1SWolfgang Grandegger upm@3,0 { 29002b8a3d1SWolfgang Grandegger #address-cells = <0>; 29102b8a3d1SWolfgang Grandegger #size-cells = <0>; 29202b8a3d1SWolfgang Grandegger compatible = "fsl,upm-nand"; 29302b8a3d1SWolfgang Grandegger reg = <3 0x0 0x800>; 29402b8a3d1SWolfgang Grandegger fsl,upm-addr-offset = <0x10>; 29502b8a3d1SWolfgang Grandegger fsl,upm-cmd-offset = <0x08>; 29602b8a3d1SWolfgang Grandegger chip-delay = <25>; // in micro-seconds 29702b8a3d1SWolfgang Grandegger 29802b8a3d1SWolfgang Grandegger nand@0 { 29902b8a3d1SWolfgang Grandegger #address-cells = <1>; 30002b8a3d1SWolfgang Grandegger #size-cells = <1>; 30102b8a3d1SWolfgang Grandegger 30202b8a3d1SWolfgang Grandegger partition@0 { 30302b8a3d1SWolfgang Grandegger label = "fs"; 30402b8a3d1SWolfgang Grandegger reg = <0x00000000 0x01000000>; 30502b8a3d1SWolfgang Grandegger }; 30602b8a3d1SWolfgang Grandegger }; 30702b8a3d1SWolfgang Grandegger }; 30802b8a3d1SWolfgang Grandegger }; 30902b8a3d1SWolfgang Grandegger 31002b8a3d1SWolfgang Grandegger pci0: pci@a0008000 { 31102b8a3d1SWolfgang Grandegger cell-index = <0>; 31202b8a3d1SWolfgang Grandegger #interrupt-cells = <1>; 31302b8a3d1SWolfgang Grandegger #size-cells = <2>; 31402b8a3d1SWolfgang Grandegger #address-cells = <3>; 31502b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 31602b8a3d1SWolfgang Grandegger device_type = "pci"; 31702b8a3d1SWolfgang Grandegger reg = <0xa0008000 0x1000>; 31802b8a3d1SWolfgang Grandegger clock-frequency = <33333333>; 31902b8a3d1SWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 32002b8a3d1SWolfgang Grandegger interrupt-map = < 32102b8a3d1SWolfgang Grandegger /* IDSEL 28 */ 32202b8a3d1SWolfgang Grandegger 0xe000 0 0 1 &mpic 2 1 32302b8a3d1SWolfgang Grandegger 0xe000 0 0 2 &mpic 3 1>; 32402b8a3d1SWolfgang Grandegger 32502b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 32602b8a3d1SWolfgang Grandegger interrupts = <24 2>; 32702b8a3d1SWolfgang Grandegger bus-range = <0 0>; 32802b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 32902b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>; 33002b8a3d1SWolfgang Grandegger }; 33102b8a3d1SWolfgang Grandegger 33202b8a3d1SWolfgang Grandegger pci1: pcie@a000a000 { 33302b8a3d1SWolfgang Grandegger cell-index = <2>; 33402b8a3d1SWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 33502b8a3d1SWolfgang Grandegger interrupt-map = < 33602b8a3d1SWolfgang Grandegger /* IDSEL 0x0 (PEX) */ 33702b8a3d1SWolfgang Grandegger 0x00000 0 0 1 &mpic 0 1 33802b8a3d1SWolfgang Grandegger 0x00000 0 0 2 &mpic 1 1 33902b8a3d1SWolfgang Grandegger 0x00000 0 0 3 &mpic 2 1 34002b8a3d1SWolfgang Grandegger 0x00000 0 0 4 &mpic 3 1>; 34102b8a3d1SWolfgang Grandegger 34202b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 34302b8a3d1SWolfgang Grandegger interrupts = <26 2>; 34402b8a3d1SWolfgang Grandegger bus-range = <0 0xff>; 34502b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000 34602b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>; 34702b8a3d1SWolfgang Grandegger clock-frequency = <33333333>; 34802b8a3d1SWolfgang Grandegger #interrupt-cells = <1>; 34902b8a3d1SWolfgang Grandegger #size-cells = <2>; 35002b8a3d1SWolfgang Grandegger #address-cells = <3>; 35102b8a3d1SWolfgang Grandegger reg = <0xa000a000 0x1000>; 35202b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-pcie"; 35302b8a3d1SWolfgang Grandegger device_type = "pci"; 35402b8a3d1SWolfgang Grandegger pcie@0 { 35502b8a3d1SWolfgang Grandegger reg = <0 0 0 0 0>; 35602b8a3d1SWolfgang Grandegger #size-cells = <2>; 35702b8a3d1SWolfgang Grandegger #address-cells = <3>; 35802b8a3d1SWolfgang Grandegger device_type = "pci"; 35902b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0xb0000000 0x02000000 0 36002b8a3d1SWolfgang Grandegger 0xb0000000 0 0x10000000 36102b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0x01000000 0 36202b8a3d1SWolfgang Grandegger 0x00000000 0 0x08000000>; 36302b8a3d1SWolfgang Grandegger }; 36402b8a3d1SWolfgang Grandegger }; 36502b8a3d1SWolfgang Grandegger}; 366