1/* 2 * TQM 8541 Device Tree Source 3 * 4 * Copyright 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "tqc,tqm8541"; 16 compatible = "tqc,tqm8541"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8541@0 { 33 device_type = "cpu"; 34 reg = <0>; 35 d-cache-line-size = <32>; 36 i-cache-line-size = <32>; 37 d-cache-size = <32768>; 38 i-cache-size = <32768>; 39 timebase-frequency = <0>; 40 bus-frequency = <0>; 41 clock-frequency = <0>; 42 next-level-cache = <&L2>; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0x00000000 0x10000000>; 49 }; 50 51 soc@e0000000 { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 device_type = "soc"; 55 ranges = <0x0 0xe0000000 0x100000>; 56 reg = <0xe0000000 0x200>; 57 bus-frequency = <0>; 58 compatible = "fsl,mpc8541-immr", "simple-bus"; 59 60 memory-controller@2000 { 61 compatible = "fsl,8540-memory-controller"; 62 reg = <0x2000 0x1000>; 63 interrupt-parent = <&mpic>; 64 interrupts = <18 2>; 65 }; 66 67 L2: l2-cache-controller@20000 { 68 compatible = "fsl,8540-l2-cache-controller"; 69 reg = <0x20000 0x1000>; 70 cache-line-size = <32>; 71 cache-size = <0x40000>; // L2, 256K 72 interrupt-parent = <&mpic>; 73 interrupts = <16 2>; 74 }; 75 76 i2c@3000 { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 cell-index = <0>; 80 compatible = "fsl-i2c"; 81 reg = <0x3000 0x100>; 82 interrupts = <43 2>; 83 interrupt-parent = <&mpic>; 84 dfsrr; 85 86 rtc@68 { 87 compatible = "dallas,ds1337"; 88 reg = <0x68>; 89 }; 90 }; 91 92 dma@21300 { 93 #address-cells = <1>; 94 #size-cells = <1>; 95 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; 96 reg = <0x21300 0x4>; 97 ranges = <0x0 0x21100 0x200>; 98 cell-index = <0>; 99 dma-channel@0 { 100 compatible = "fsl,mpc8541-dma-channel", 101 "fsl,eloplus-dma-channel"; 102 reg = <0x0 0x80>; 103 cell-index = <0>; 104 interrupt-parent = <&mpic>; 105 interrupts = <20 2>; 106 }; 107 dma-channel@80 { 108 compatible = "fsl,mpc8541-dma-channel", 109 "fsl,eloplus-dma-channel"; 110 reg = <0x80 0x80>; 111 cell-index = <1>; 112 interrupt-parent = <&mpic>; 113 interrupts = <21 2>; 114 }; 115 dma-channel@100 { 116 compatible = "fsl,mpc8541-dma-channel", 117 "fsl,eloplus-dma-channel"; 118 reg = <0x100 0x80>; 119 cell-index = <2>; 120 interrupt-parent = <&mpic>; 121 interrupts = <22 2>; 122 }; 123 dma-channel@180 { 124 compatible = "fsl,mpc8541-dma-channel", 125 "fsl,eloplus-dma-channel"; 126 reg = <0x180 0x80>; 127 cell-index = <3>; 128 interrupt-parent = <&mpic>; 129 interrupts = <23 2>; 130 }; 131 }; 132 133 mdio@24520 { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 compatible = "fsl,gianfar-mdio"; 137 reg = <0x24520 0x20>; 138 139 phy1: ethernet-phy@1 { 140 interrupt-parent = <&mpic>; 141 interrupts = <8 1>; 142 reg = <1>; 143 device_type = "ethernet-phy"; 144 }; 145 phy2: ethernet-phy@2 { 146 interrupt-parent = <&mpic>; 147 interrupts = <8 1>; 148 reg = <2>; 149 device_type = "ethernet-phy"; 150 }; 151 phy3: ethernet-phy@3 { 152 interrupt-parent = <&mpic>; 153 interrupts = <8 1>; 154 reg = <3>; 155 device_type = "ethernet-phy"; 156 }; 157 }; 158 159 enet0: ethernet@24000 { 160 cell-index = <0>; 161 device_type = "network"; 162 model = "TSEC"; 163 compatible = "gianfar"; 164 reg = <0x24000 0x1000>; 165 local-mac-address = [ 00 00 00 00 00 00 ]; 166 interrupts = <29 2 30 2 34 2>; 167 interrupt-parent = <&mpic>; 168 phy-handle = <&phy2>; 169 }; 170 171 enet1: ethernet@25000 { 172 cell-index = <1>; 173 device_type = "network"; 174 model = "TSEC"; 175 compatible = "gianfar"; 176 reg = <0x25000 0x1000>; 177 local-mac-address = [ 00 00 00 00 00 00 ]; 178 interrupts = <35 2 36 2 40 2>; 179 interrupt-parent = <&mpic>; 180 phy-handle = <&phy1>; 181 }; 182 183 serial0: serial@4500 { 184 cell-index = <0>; 185 device_type = "serial"; 186 compatible = "ns16550"; 187 reg = <0x4500 0x100>; // reg base, size 188 clock-frequency = <0>; // should we fill in in uboot? 189 interrupts = <42 2>; 190 interrupt-parent = <&mpic>; 191 }; 192 193 serial1: serial@4600 { 194 cell-index = <1>; 195 device_type = "serial"; 196 compatible = "ns16550"; 197 reg = <0x4600 0x100>; // reg base, size 198 clock-frequency = <0>; // should we fill in in uboot? 199 interrupts = <42 2>; 200 interrupt-parent = <&mpic>; 201 }; 202 203 mpic: pic@40000 { 204 interrupt-controller; 205 #address-cells = <0>; 206 #interrupt-cells = <2>; 207 reg = <0x40000 0x40000>; 208 device_type = "open-pic"; 209 compatible = "chrp,open-pic"; 210 }; 211 212 cpm@919c0 { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus"; 216 reg = <0x919c0 0x30>; 217 ranges; 218 219 muram@80000 { 220 #address-cells = <1>; 221 #size-cells = <1>; 222 ranges = <0 0x80000 0x10000>; 223 224 data@0 { 225 compatible = "fsl,cpm-muram-data"; 226 reg = <0 0x2000 0x9000 0x1000>; 227 }; 228 }; 229 230 brg@919f0 { 231 compatible = "fsl,mpc8541-brg", 232 "fsl,cpm2-brg", 233 "fsl,cpm-brg"; 234 reg = <0x919f0 0x10 0x915f0 0x10>; 235 clock-frequency = <0>; 236 }; 237 238 cpmpic: pic@90c00 { 239 interrupt-controller; 240 #address-cells = <0>; 241 #interrupt-cells = <2>; 242 interrupts = <46 2>; 243 interrupt-parent = <&mpic>; 244 reg = <0x90c00 0x80>; 245 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 246 }; 247 }; 248 }; 249 250 pci0: pci@e0008000 { 251 cell-index = <0>; 252 #interrupt-cells = <1>; 253 #size-cells = <2>; 254 #address-cells = <3>; 255 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 256 device_type = "pci"; 257 reg = <0xe0008000 0x1000>; 258 clock-frequency = <66666666>; 259 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 260 interrupt-map = < 261 /* IDSEL 28 */ 262 0xe000 0 0 1 &mpic 2 1 263 0xe000 0 0 2 &mpic 3 1>; 264 265 interrupt-parent = <&mpic>; 266 interrupts = <24 2>; 267 bus-range = <0 0>; 268 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 269 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 270 }; 271}; 272