1/* 2 * TQM 8541 Device Tree Source 3 * 4 * Copyright 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "tqc,tqm8541"; 16 compatible = "tqc,tqm8541"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8541@0 { 33 device_type = "cpu"; 34 reg = <0>; 35 d-cache-line-size = <32>; 36 i-cache-line-size = <32>; 37 d-cache-size = <32768>; 38 i-cache-size = <32768>; 39 timebase-frequency = <0>; 40 bus-frequency = <0>; 41 clock-frequency = <0>; 42 next-level-cache = <&L2>; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0x00000000 0x10000000>; 49 }; 50 51 soc@e0000000 { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 device_type = "soc"; 55 ranges = <0x0 0xe0000000 0x100000>; 56 reg = <0xe0000000 0x200>; 57 bus-frequency = <0>; 58 compatible = "fsl,mpc8541-immr", "simple-bus"; 59 60 memory-controller@2000 { 61 compatible = "fsl,8540-memory-controller"; 62 reg = <0x2000 0x1000>; 63 interrupt-parent = <&mpic>; 64 interrupts = <18 2>; 65 }; 66 67 L2: l2-cache-controller@20000 { 68 compatible = "fsl,8540-l2-cache-controller"; 69 reg = <0x20000 0x1000>; 70 cache-line-size = <32>; 71 cache-size = <0x40000>; // L2, 256K 72 interrupt-parent = <&mpic>; 73 interrupts = <16 2>; 74 }; 75 76 i2c@3000 { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 cell-index = <0>; 80 compatible = "fsl-i2c"; 81 reg = <0x3000 0x100>; 82 interrupts = <43 2>; 83 interrupt-parent = <&mpic>; 84 dfsrr; 85 86 dtt@50 { 87 compatible = "national,lm75"; 88 reg = <0x50>; 89 }; 90 91 rtc@68 { 92 compatible = "dallas,ds1337"; 93 reg = <0x68>; 94 }; 95 }; 96 97 dma@21300 { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; 101 reg = <0x21300 0x4>; 102 ranges = <0x0 0x21100 0x200>; 103 cell-index = <0>; 104 dma-channel@0 { 105 compatible = "fsl,mpc8541-dma-channel", 106 "fsl,eloplus-dma-channel"; 107 reg = <0x0 0x80>; 108 cell-index = <0>; 109 interrupt-parent = <&mpic>; 110 interrupts = <20 2>; 111 }; 112 dma-channel@80 { 113 compatible = "fsl,mpc8541-dma-channel", 114 "fsl,eloplus-dma-channel"; 115 reg = <0x80 0x80>; 116 cell-index = <1>; 117 interrupt-parent = <&mpic>; 118 interrupts = <21 2>; 119 }; 120 dma-channel@100 { 121 compatible = "fsl,mpc8541-dma-channel", 122 "fsl,eloplus-dma-channel"; 123 reg = <0x100 0x80>; 124 cell-index = <2>; 125 interrupt-parent = <&mpic>; 126 interrupts = <22 2>; 127 }; 128 dma-channel@180 { 129 compatible = "fsl,mpc8541-dma-channel", 130 "fsl,eloplus-dma-channel"; 131 reg = <0x180 0x80>; 132 cell-index = <3>; 133 interrupt-parent = <&mpic>; 134 interrupts = <23 2>; 135 }; 136 }; 137 138 enet0: ethernet@24000 { 139 #address-cells = <1>; 140 #size-cells = <1>; 141 cell-index = <0>; 142 device_type = "network"; 143 model = "TSEC"; 144 compatible = "gianfar"; 145 reg = <0x24000 0x1000>; 146 ranges = <0x0 0x24000 0x1000>; 147 local-mac-address = [ 00 00 00 00 00 00 ]; 148 interrupts = <29 2 30 2 34 2>; 149 interrupt-parent = <&mpic>; 150 tbi-handle = <&tbi0>; 151 phy-handle = <&phy2>; 152 153 mdio@520 { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 compatible = "fsl,gianfar-mdio"; 157 reg = <0x520 0x20>; 158 159 phy1: ethernet-phy@1 { 160 interrupt-parent = <&mpic>; 161 interrupts = <8 1>; 162 reg = <1>; 163 device_type = "ethernet-phy"; 164 }; 165 phy2: ethernet-phy@2 { 166 interrupt-parent = <&mpic>; 167 interrupts = <8 1>; 168 reg = <2>; 169 device_type = "ethernet-phy"; 170 }; 171 phy3: ethernet-phy@3 { 172 interrupt-parent = <&mpic>; 173 interrupts = <8 1>; 174 reg = <3>; 175 device_type = "ethernet-phy"; 176 }; 177 tbi0: tbi-phy@11 { 178 reg = <0x11>; 179 device_type = "tbi-phy"; 180 }; 181 }; 182 }; 183 184 enet1: ethernet@25000 { 185 #address-cells = <1>; 186 #size-cells = <1>; 187 cell-index = <1>; 188 device_type = "network"; 189 model = "TSEC"; 190 compatible = "gianfar"; 191 reg = <0x25000 0x1000>; 192 ranges = <0x0 0x25000 0x1000>; 193 local-mac-address = [ 00 00 00 00 00 00 ]; 194 interrupts = <35 2 36 2 40 2>; 195 interrupt-parent = <&mpic>; 196 tbi-handle = <&tbi1>; 197 phy-handle = <&phy1>; 198 199 mdio@520 { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 compatible = "fsl,gianfar-tbi"; 203 reg = <0x520 0x20>; 204 205 tbi1: tbi-phy@11 { 206 reg = <0x11>; 207 device_type = "tbi-phy"; 208 }; 209 }; 210 }; 211 212 serial0: serial@4500 { 213 cell-index = <0>; 214 device_type = "serial"; 215 compatible = "ns16550"; 216 reg = <0x4500 0x100>; // reg base, size 217 clock-frequency = <0>; // should we fill in in uboot? 218 interrupts = <42 2>; 219 interrupt-parent = <&mpic>; 220 }; 221 222 serial1: serial@4600 { 223 cell-index = <1>; 224 device_type = "serial"; 225 compatible = "ns16550"; 226 reg = <0x4600 0x100>; // reg base, size 227 clock-frequency = <0>; // should we fill in in uboot? 228 interrupts = <42 2>; 229 interrupt-parent = <&mpic>; 230 }; 231 232 crypto@30000 { 233 compatible = "fsl,sec2.0"; 234 reg = <0x30000 0x10000>; 235 interrupts = <45 2>; 236 interrupt-parent = <&mpic>; 237 fsl,num-channels = <4>; 238 fsl,channel-fifo-len = <24>; 239 fsl,exec-units-mask = <0x7e>; 240 fsl,descriptor-types-mask = <0x01010ebf>; 241 }; 242 243 mpic: pic@40000 { 244 interrupt-controller; 245 #address-cells = <0>; 246 #interrupt-cells = <2>; 247 reg = <0x40000 0x40000>; 248 device_type = "open-pic"; 249 compatible = "chrp,open-pic"; 250 }; 251 252 cpm@919c0 { 253 #address-cells = <1>; 254 #size-cells = <1>; 255 compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus"; 256 reg = <0x919c0 0x30>; 257 ranges; 258 259 muram@80000 { 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0 0x80000 0x10000>; 263 264 data@0 { 265 compatible = "fsl,cpm-muram-data"; 266 reg = <0 0x2000 0x9000 0x1000>; 267 }; 268 }; 269 270 brg@919f0 { 271 compatible = "fsl,mpc8541-brg", 272 "fsl,cpm2-brg", 273 "fsl,cpm-brg"; 274 reg = <0x919f0 0x10 0x915f0 0x10>; 275 clock-frequency = <0>; 276 }; 277 278 cpmpic: pic@90c00 { 279 interrupt-controller; 280 #address-cells = <0>; 281 #interrupt-cells = <2>; 282 interrupts = <46 2>; 283 interrupt-parent = <&mpic>; 284 reg = <0x90c00 0x80>; 285 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 286 }; 287 }; 288 }; 289 290 pci0: pci@e0008000 { 291 cell-index = <0>; 292 #interrupt-cells = <1>; 293 #size-cells = <2>; 294 #address-cells = <3>; 295 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 296 device_type = "pci"; 297 reg = <0xe0008000 0x1000>; 298 clock-frequency = <66666666>; 299 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 300 interrupt-map = < 301 /* IDSEL 28 */ 302 0xe000 0 0 1 &mpic 2 1 303 0xe000 0 0 2 &mpic 3 1>; 304 305 interrupt-parent = <&mpic>; 306 interrupts = <24 2>; 307 bus-range = <0 0>; 308 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 309 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 310 }; 311}; 312