1/*
2 * TQM 8541 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "tqc,tqm8541";
16	compatible = "tqc,tqm8541";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8541@0 {
33			device_type = "cpu";
34			reg = <0>;
35			d-cache-line-size = <32>;
36			i-cache-line-size = <32>;
37			d-cache-size = <32768>;
38			i-cache-size = <32768>;
39			timebase-frequency = <0>;
40			bus-frequency = <0>;
41			clock-frequency = <0>;
42			next-level-cache = <&L2>;
43		};
44	};
45
46	memory {
47		device_type = "memory";
48		reg = <0x00000000 0x10000000>;
49	};
50
51	soc@e0000000 {
52		#address-cells = <1>;
53		#size-cells = <1>;
54		device_type = "soc";
55		ranges = <0x0 0xe0000000 0x100000>;
56		bus-frequency = <0>;
57		compatible = "fsl,mpc8541-immr", "simple-bus";
58
59		ecm-law@0 {
60			compatible = "fsl,ecm-law";
61			reg = <0x0 0x1000>;
62			fsl,num-laws = <8>;
63		};
64
65		ecm@1000 {
66			compatible = "fsl,mpc8541-ecm", "fsl,ecm";
67			reg = <0x1000 0x1000>;
68			interrupts = <17 2>;
69			interrupt-parent = <&mpic>;
70		};
71
72		memory-controller@2000 {
73			compatible = "fsl,mpc8540-memory-controller";
74			reg = <0x2000 0x1000>;
75			interrupt-parent = <&mpic>;
76			interrupts = <18 2>;
77		};
78
79		L2: l2-cache-controller@20000 {
80			compatible = "fsl,mpc8540-l2-cache-controller";
81			reg = <0x20000 0x1000>;
82			cache-line-size = <32>;
83			cache-size = <0x40000>;	// L2, 256K
84			interrupt-parent = <&mpic>;
85			interrupts = <16 2>;
86		};
87
88		i2c@3000 {
89			#address-cells = <1>;
90			#size-cells = <0>;
91			cell-index = <0>;
92			compatible = "fsl-i2c";
93			reg = <0x3000 0x100>;
94			interrupts = <43 2>;
95			interrupt-parent = <&mpic>;
96			dfsrr;
97
98			dtt@48 {
99				compatible = "national,lm75";
100				reg = <0x48>;
101			};
102
103			rtc@68 {
104				compatible = "dallas,ds1337";
105				reg = <0x68>;
106			};
107		};
108
109		dma@21300 {
110			#address-cells = <1>;
111			#size-cells = <1>;
112			compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
113			reg = <0x21300 0x4>;
114			ranges = <0x0 0x21100 0x200>;
115			cell-index = <0>;
116			dma-channel@0 {
117				compatible = "fsl,mpc8541-dma-channel",
118						"fsl,eloplus-dma-channel";
119				reg = <0x0 0x80>;
120				cell-index = <0>;
121				interrupt-parent = <&mpic>;
122				interrupts = <20 2>;
123			};
124			dma-channel@80 {
125				compatible = "fsl,mpc8541-dma-channel",
126						"fsl,eloplus-dma-channel";
127				reg = <0x80 0x80>;
128				cell-index = <1>;
129				interrupt-parent = <&mpic>;
130				interrupts = <21 2>;
131			};
132			dma-channel@100 {
133				compatible = "fsl,mpc8541-dma-channel",
134						"fsl,eloplus-dma-channel";
135				reg = <0x100 0x80>;
136				cell-index = <2>;
137				interrupt-parent = <&mpic>;
138				interrupts = <22 2>;
139			};
140			dma-channel@180 {
141				compatible = "fsl,mpc8541-dma-channel",
142						"fsl,eloplus-dma-channel";
143				reg = <0x180 0x80>;
144				cell-index = <3>;
145				interrupt-parent = <&mpic>;
146				interrupts = <23 2>;
147			};
148		};
149
150		enet0: ethernet@24000 {
151			#address-cells = <1>;
152			#size-cells = <1>;
153			cell-index = <0>;
154			device_type = "network";
155			model = "TSEC";
156			compatible = "gianfar";
157			reg = <0x24000 0x1000>;
158			ranges = <0x0 0x24000 0x1000>;
159			local-mac-address = [ 00 00 00 00 00 00 ];
160			interrupts = <29 2 30 2 34 2>;
161			interrupt-parent = <&mpic>;
162			tbi-handle = <&tbi0>;
163			phy-handle = <&phy2>;
164
165			mdio@520 {
166				#address-cells = <1>;
167				#size-cells = <0>;
168				compatible = "fsl,gianfar-mdio";
169				reg = <0x520 0x20>;
170
171				phy1: ethernet-phy@1 {
172					interrupt-parent = <&mpic>;
173					interrupts = <8 1>;
174					reg = <1>;
175				};
176				phy2: ethernet-phy@2 {
177					interrupt-parent = <&mpic>;
178					interrupts = <8 1>;
179					reg = <2>;
180				};
181				phy3: ethernet-phy@3 {
182					interrupt-parent = <&mpic>;
183					interrupts = <8 1>;
184					reg = <3>;
185				};
186				tbi0: tbi-phy@11 {
187					reg = <0x11>;
188					device_type = "tbi-phy";
189				};
190			};
191		};
192
193		enet1: ethernet@25000 {
194			#address-cells = <1>;
195			#size-cells = <1>;
196			cell-index = <1>;
197			device_type = "network";
198			model = "TSEC";
199			compatible = "gianfar";
200			reg = <0x25000 0x1000>;
201			ranges = <0x0 0x25000 0x1000>;
202			local-mac-address = [ 00 00 00 00 00 00 ];
203			interrupts = <35 2 36 2 40 2>;
204			interrupt-parent = <&mpic>;
205			tbi-handle = <&tbi1>;
206			phy-handle = <&phy1>;
207
208			mdio@520 {
209				#address-cells = <1>;
210				#size-cells = <0>;
211				compatible = "fsl,gianfar-tbi";
212				reg = <0x520 0x20>;
213
214				tbi1: tbi-phy@11 {
215					reg = <0x11>;
216					device_type = "tbi-phy";
217				};
218			};
219		};
220
221		serial0: serial@4500 {
222			cell-index = <0>;
223			device_type = "serial";
224			compatible = "fsl,ns16550", "ns16550";
225			reg = <0x4500 0x100>; 	// reg base, size
226			clock-frequency = <0>; 	// should we fill in in uboot?
227			interrupts = <42 2>;
228			interrupt-parent = <&mpic>;
229		};
230
231		serial1: serial@4600 {
232			cell-index = <1>;
233			device_type = "serial";
234			compatible = "fsl,ns16550", "ns16550";
235			reg = <0x4600 0x100>;	// reg base, size
236			clock-frequency = <0>; 	// should we fill in in uboot?
237			interrupts = <42 2>;
238			interrupt-parent = <&mpic>;
239		};
240
241		crypto@30000 {
242			compatible = "fsl,sec2.0";
243			reg = <0x30000 0x10000>;
244			interrupts = <45 2>;
245			interrupt-parent = <&mpic>;
246			fsl,num-channels = <4>;
247			fsl,channel-fifo-len = <24>;
248			fsl,exec-units-mask = <0x7e>;
249			fsl,descriptor-types-mask = <0x01010ebf>;
250		};
251
252		mpic: pic@40000 {
253			interrupt-controller;
254			#address-cells = <0>;
255			#interrupt-cells = <2>;
256			reg = <0x40000 0x40000>;
257			device_type = "open-pic";
258			compatible = "chrp,open-pic";
259		};
260
261		cpm@919c0 {
262			#address-cells = <1>;
263			#size-cells = <1>;
264			compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus";
265			reg = <0x919c0 0x30>;
266			ranges;
267
268			muram@80000 {
269				#address-cells = <1>;
270				#size-cells = <1>;
271				ranges = <0 0x80000 0x10000>;
272
273				data@0 {
274					compatible = "fsl,cpm-muram-data";
275					reg = <0 0x2000 0x9000 0x1000>;
276				};
277			};
278
279			brg@919f0 {
280				compatible = "fsl,mpc8541-brg",
281				             "fsl,cpm2-brg",
282				             "fsl,cpm-brg";
283				reg = <0x919f0 0x10 0x915f0 0x10>;
284				clock-frequency = <0>;
285			};
286
287			cpmpic: pic@90c00 {
288				interrupt-controller;
289				#address-cells = <0>;
290				#interrupt-cells = <2>;
291				interrupts = <46 2>;
292				interrupt-parent = <&mpic>;
293				reg = <0x90c00 0x80>;
294				compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
295			};
296		};
297	};
298
299	pci0: pci@e0008000 {
300		#interrupt-cells = <1>;
301		#size-cells = <2>;
302		#address-cells = <3>;
303		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
304		device_type = "pci";
305		reg = <0xe0008000 0x1000>;
306		clock-frequency = <66666666>;
307		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
308		interrupt-map = <
309				/* IDSEL 28 */
310				 0xe000 0 0 1 &mpic 2 1
311				 0xe000 0 0 2 &mpic 3 1
312				 0xe000 0 0 3 &mpic 6 1
313				 0xe000 0 0 4 &mpic 5 1
314
315				/* IDSEL 11 */
316				 0x5800 0 0 1 &mpic 6 1
317				 0x5800 0 0 2 &mpic 5 1
318				 >;
319
320		interrupt-parent = <&mpic>;
321		interrupts = <24 2>;
322		bus-range = <0 0>;
323		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
324			  0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
325	};
326};
327