10052bc5dSKumar Gala/* 20052bc5dSKumar Gala * TQM 8541 Device Tree Source 30052bc5dSKumar Gala * 40052bc5dSKumar Gala * Copyright 2008 Freescale Semiconductor Inc. 50052bc5dSKumar Gala * 60052bc5dSKumar Gala * This program is free software; you can redistribute it and/or modify it 70052bc5dSKumar Gala * under the terms of the GNU General Public License as published by the 80052bc5dSKumar Gala * Free Software Foundation; either version 2 of the License, or (at your 90052bc5dSKumar Gala * option) any later version. 100052bc5dSKumar Gala */ 110052bc5dSKumar Gala 120052bc5dSKumar Gala/dts-v1/; 130052bc5dSKumar Gala 140052bc5dSKumar Gala/ { 154fb035f6SWolfgang Grandegger model = "tqc,tqm8541"; 164fb035f6SWolfgang Grandegger compatible = "tqc,tqm8541"; 170052bc5dSKumar Gala #address-cells = <1>; 180052bc5dSKumar Gala #size-cells = <1>; 190052bc5dSKumar Gala 200052bc5dSKumar Gala aliases { 210052bc5dSKumar Gala ethernet0 = &enet0; 220052bc5dSKumar Gala ethernet1 = &enet1; 230052bc5dSKumar Gala serial0 = &serial0; 240052bc5dSKumar Gala serial1 = &serial1; 250052bc5dSKumar Gala pci0 = &pci0; 260052bc5dSKumar Gala }; 270052bc5dSKumar Gala 280052bc5dSKumar Gala cpus { 290052bc5dSKumar Gala #address-cells = <1>; 300052bc5dSKumar Gala #size-cells = <0>; 310052bc5dSKumar Gala 320052bc5dSKumar Gala PowerPC,8541@0 { 330052bc5dSKumar Gala device_type = "cpu"; 340052bc5dSKumar Gala reg = <0>; 350052bc5dSKumar Gala d-cache-line-size = <32>; 360052bc5dSKumar Gala i-cache-line-size = <32>; 370052bc5dSKumar Gala d-cache-size = <32768>; 380052bc5dSKumar Gala i-cache-size = <32768>; 390052bc5dSKumar Gala timebase-frequency = <0>; 400052bc5dSKumar Gala bus-frequency = <0>; 410052bc5dSKumar Gala clock-frequency = <0>; 42c054065bSKumar Gala next-level-cache = <&L2>; 430052bc5dSKumar Gala }; 440052bc5dSKumar Gala }; 450052bc5dSKumar Gala 460052bc5dSKumar Gala memory { 470052bc5dSKumar Gala device_type = "memory"; 480052bc5dSKumar Gala reg = <0x00000000 0x10000000>; 490052bc5dSKumar Gala }; 500052bc5dSKumar Gala 51f67be814SKumar Gala soc@e0000000 { 520052bc5dSKumar Gala #address-cells = <1>; 530052bc5dSKumar Gala #size-cells = <1>; 540052bc5dSKumar Gala device_type = "soc"; 550052bc5dSKumar Gala ranges = <0x0 0xe0000000 0x100000>; 560052bc5dSKumar Gala bus-frequency = <0>; 570052bc5dSKumar Gala compatible = "fsl,mpc8541-immr", "simple-bus"; 580052bc5dSKumar Gala 59e1a22897SKumar Gala ecm-law@0 { 60e1a22897SKumar Gala compatible = "fsl,ecm-law"; 61e1a22897SKumar Gala reg = <0x0 0x1000>; 62e1a22897SKumar Gala fsl,num-laws = <8>; 63e1a22897SKumar Gala }; 64e1a22897SKumar Gala 65e1a22897SKumar Gala ecm@1000 { 66e1a22897SKumar Gala compatible = "fsl,mpc8541-ecm", "fsl,ecm"; 67e1a22897SKumar Gala reg = <0x1000 0x1000>; 68e1a22897SKumar Gala interrupts = <17 2>; 69e1a22897SKumar Gala interrupt-parent = <&mpic>; 70e1a22897SKumar Gala }; 71e1a22897SKumar Gala 720052bc5dSKumar Gala memory-controller@2000 { 73fe671772SKumar Gala compatible = "fsl,mpc8540-memory-controller"; 740052bc5dSKumar Gala reg = <0x2000 0x1000>; 750052bc5dSKumar Gala interrupt-parent = <&mpic>; 760052bc5dSKumar Gala interrupts = <18 2>; 770052bc5dSKumar Gala }; 780052bc5dSKumar Gala 79c054065bSKumar Gala L2: l2-cache-controller@20000 { 80fe671772SKumar Gala compatible = "fsl,mpc8540-l2-cache-controller"; 810052bc5dSKumar Gala reg = <0x20000 0x1000>; 820052bc5dSKumar Gala cache-line-size = <32>; 830052bc5dSKumar Gala cache-size = <0x40000>; // L2, 256K 840052bc5dSKumar Gala interrupt-parent = <&mpic>; 850052bc5dSKumar Gala interrupts = <16 2>; 860052bc5dSKumar Gala }; 870052bc5dSKumar Gala 880052bc5dSKumar Gala i2c@3000 { 890052bc5dSKumar Gala #address-cells = <1>; 900052bc5dSKumar Gala #size-cells = <0>; 910052bc5dSKumar Gala cell-index = <0>; 920052bc5dSKumar Gala compatible = "fsl-i2c"; 930052bc5dSKumar Gala reg = <0x3000 0x100>; 940052bc5dSKumar Gala interrupts = <43 2>; 950052bc5dSKumar Gala interrupt-parent = <&mpic>; 960052bc5dSKumar Gala dfsrr; 970052bc5dSKumar Gala 986467cae3SWolfgang Grandegger dtt@48 { 990f73a449SWolfgang Grandegger compatible = "national,lm75"; 1006467cae3SWolfgang Grandegger reg = <0x48>; 1010f73a449SWolfgang Grandegger }; 1020f73a449SWolfgang Grandegger 1030052bc5dSKumar Gala rtc@68 { 1040052bc5dSKumar Gala compatible = "dallas,ds1337"; 1050052bc5dSKumar Gala reg = <0x68>; 1060052bc5dSKumar Gala }; 1070052bc5dSKumar Gala }; 1080052bc5dSKumar Gala 109dee80553SKumar Gala dma@21300 { 110dee80553SKumar Gala #address-cells = <1>; 111dee80553SKumar Gala #size-cells = <1>; 112dee80553SKumar Gala compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; 113dee80553SKumar Gala reg = <0x21300 0x4>; 114dee80553SKumar Gala ranges = <0x0 0x21100 0x200>; 115dee80553SKumar Gala cell-index = <0>; 116dee80553SKumar Gala dma-channel@0 { 117dee80553SKumar Gala compatible = "fsl,mpc8541-dma-channel", 118dee80553SKumar Gala "fsl,eloplus-dma-channel"; 119dee80553SKumar Gala reg = <0x0 0x80>; 120dee80553SKumar Gala cell-index = <0>; 121dee80553SKumar Gala interrupt-parent = <&mpic>; 122dee80553SKumar Gala interrupts = <20 2>; 123dee80553SKumar Gala }; 124dee80553SKumar Gala dma-channel@80 { 125dee80553SKumar Gala compatible = "fsl,mpc8541-dma-channel", 126dee80553SKumar Gala "fsl,eloplus-dma-channel"; 127dee80553SKumar Gala reg = <0x80 0x80>; 128dee80553SKumar Gala cell-index = <1>; 129dee80553SKumar Gala interrupt-parent = <&mpic>; 130dee80553SKumar Gala interrupts = <21 2>; 131dee80553SKumar Gala }; 132dee80553SKumar Gala dma-channel@100 { 133dee80553SKumar Gala compatible = "fsl,mpc8541-dma-channel", 134dee80553SKumar Gala "fsl,eloplus-dma-channel"; 135dee80553SKumar Gala reg = <0x100 0x80>; 136dee80553SKumar Gala cell-index = <2>; 137dee80553SKumar Gala interrupt-parent = <&mpic>; 138dee80553SKumar Gala interrupts = <22 2>; 139dee80553SKumar Gala }; 140dee80553SKumar Gala dma-channel@180 { 141dee80553SKumar Gala compatible = "fsl,mpc8541-dma-channel", 142dee80553SKumar Gala "fsl,eloplus-dma-channel"; 143dee80553SKumar Gala reg = <0x180 0x80>; 144dee80553SKumar Gala cell-index = <3>; 145dee80553SKumar Gala interrupt-parent = <&mpic>; 146dee80553SKumar Gala interrupts = <23 2>; 147dee80553SKumar Gala }; 148dee80553SKumar Gala }; 149dee80553SKumar Gala 15084ba4a58SAnton Vorontsov enet0: ethernet@24000 { 15184ba4a58SAnton Vorontsov #address-cells = <1>; 15284ba4a58SAnton Vorontsov #size-cells = <1>; 15384ba4a58SAnton Vorontsov cell-index = <0>; 15484ba4a58SAnton Vorontsov device_type = "network"; 15584ba4a58SAnton Vorontsov model = "TSEC"; 15684ba4a58SAnton Vorontsov compatible = "gianfar"; 15784ba4a58SAnton Vorontsov reg = <0x24000 0x1000>; 15884ba4a58SAnton Vorontsov ranges = <0x0 0x24000 0x1000>; 15984ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 16084ba4a58SAnton Vorontsov interrupts = <29 2 30 2 34 2>; 16184ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 16284ba4a58SAnton Vorontsov tbi-handle = <&tbi0>; 16384ba4a58SAnton Vorontsov phy-handle = <&phy2>; 16484ba4a58SAnton Vorontsov 16584ba4a58SAnton Vorontsov mdio@520 { 1660052bc5dSKumar Gala #address-cells = <1>; 1670052bc5dSKumar Gala #size-cells = <0>; 1680052bc5dSKumar Gala compatible = "fsl,gianfar-mdio"; 16984ba4a58SAnton Vorontsov reg = <0x520 0x20>; 1700052bc5dSKumar Gala 1710052bc5dSKumar Gala phy1: ethernet-phy@1 { 1720052bc5dSKumar Gala interrupt-parent = <&mpic>; 1730052bc5dSKumar Gala interrupts = <8 1>; 1740052bc5dSKumar Gala reg = <1>; 1750052bc5dSKumar Gala device_type = "ethernet-phy"; 1760052bc5dSKumar Gala }; 1770052bc5dSKumar Gala phy2: ethernet-phy@2 { 1780052bc5dSKumar Gala interrupt-parent = <&mpic>; 1790052bc5dSKumar Gala interrupts = <8 1>; 1800052bc5dSKumar Gala reg = <2>; 1810052bc5dSKumar Gala device_type = "ethernet-phy"; 1820052bc5dSKumar Gala }; 1830052bc5dSKumar Gala phy3: ethernet-phy@3 { 1840052bc5dSKumar Gala interrupt-parent = <&mpic>; 1850052bc5dSKumar Gala interrupts = <8 1>; 1860052bc5dSKumar Gala reg = <3>; 1870052bc5dSKumar Gala device_type = "ethernet-phy"; 1880052bc5dSKumar Gala }; 189b31a1d8bSAndy Fleming tbi0: tbi-phy@11 { 190b31a1d8bSAndy Fleming reg = <0x11>; 191b31a1d8bSAndy Fleming device_type = "tbi-phy"; 192b31a1d8bSAndy Fleming }; 193b31a1d8bSAndy Fleming }; 19484ba4a58SAnton Vorontsov }; 195b31a1d8bSAndy Fleming 19684ba4a58SAnton Vorontsov enet1: ethernet@25000 { 19784ba4a58SAnton Vorontsov #address-cells = <1>; 19884ba4a58SAnton Vorontsov #size-cells = <1>; 19984ba4a58SAnton Vorontsov cell-index = <1>; 20084ba4a58SAnton Vorontsov device_type = "network"; 20184ba4a58SAnton Vorontsov model = "TSEC"; 20284ba4a58SAnton Vorontsov compatible = "gianfar"; 20384ba4a58SAnton Vorontsov reg = <0x25000 0x1000>; 20484ba4a58SAnton Vorontsov ranges = <0x0 0x25000 0x1000>; 20584ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 20684ba4a58SAnton Vorontsov interrupts = <35 2 36 2 40 2>; 20784ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 20884ba4a58SAnton Vorontsov tbi-handle = <&tbi1>; 20984ba4a58SAnton Vorontsov phy-handle = <&phy1>; 21084ba4a58SAnton Vorontsov 21184ba4a58SAnton Vorontsov mdio@520 { 212b31a1d8bSAndy Fleming #address-cells = <1>; 213b31a1d8bSAndy Fleming #size-cells = <0>; 214b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 21584ba4a58SAnton Vorontsov reg = <0x520 0x20>; 216b31a1d8bSAndy Fleming 217b31a1d8bSAndy Fleming tbi1: tbi-phy@11 { 218b31a1d8bSAndy Fleming reg = <0x11>; 219b31a1d8bSAndy Fleming device_type = "tbi-phy"; 220b31a1d8bSAndy Fleming }; 2210052bc5dSKumar Gala }; 2220052bc5dSKumar Gala }; 2230052bc5dSKumar Gala 2240052bc5dSKumar Gala serial0: serial@4500 { 2250052bc5dSKumar Gala cell-index = <0>; 2260052bc5dSKumar Gala device_type = "serial"; 227f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 2280052bc5dSKumar Gala reg = <0x4500 0x100>; // reg base, size 2290052bc5dSKumar Gala clock-frequency = <0>; // should we fill in in uboot? 2300052bc5dSKumar Gala interrupts = <42 2>; 2310052bc5dSKumar Gala interrupt-parent = <&mpic>; 2320052bc5dSKumar Gala }; 2330052bc5dSKumar Gala 2340052bc5dSKumar Gala serial1: serial@4600 { 2350052bc5dSKumar Gala cell-index = <1>; 2360052bc5dSKumar Gala device_type = "serial"; 237f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 2380052bc5dSKumar Gala reg = <0x4600 0x100>; // reg base, size 2390052bc5dSKumar Gala clock-frequency = <0>; // should we fill in in uboot? 2400052bc5dSKumar Gala interrupts = <42 2>; 2410052bc5dSKumar Gala interrupt-parent = <&mpic>; 2420052bc5dSKumar Gala }; 2430052bc5dSKumar Gala 2443fd44736SKim Phillips crypto@30000 { 2453fd44736SKim Phillips compatible = "fsl,sec2.0"; 2463fd44736SKim Phillips reg = <0x30000 0x10000>; 2473fd44736SKim Phillips interrupts = <45 2>; 2483fd44736SKim Phillips interrupt-parent = <&mpic>; 2493fd44736SKim Phillips fsl,num-channels = <4>; 2503fd44736SKim Phillips fsl,channel-fifo-len = <24>; 2513fd44736SKim Phillips fsl,exec-units-mask = <0x7e>; 2523fd44736SKim Phillips fsl,descriptor-types-mask = <0x01010ebf>; 2533fd44736SKim Phillips }; 2543fd44736SKim Phillips 2550052bc5dSKumar Gala mpic: pic@40000 { 2560052bc5dSKumar Gala interrupt-controller; 2570052bc5dSKumar Gala #address-cells = <0>; 2580052bc5dSKumar Gala #interrupt-cells = <2>; 2590052bc5dSKumar Gala reg = <0x40000 0x40000>; 2600052bc5dSKumar Gala device_type = "open-pic"; 261acd4b715SKumar Gala compatible = "chrp,open-pic"; 2620052bc5dSKumar Gala }; 2630052bc5dSKumar Gala 2640052bc5dSKumar Gala cpm@919c0 { 2650052bc5dSKumar Gala #address-cells = <1>; 2660052bc5dSKumar Gala #size-cells = <1>; 2670052bc5dSKumar Gala compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus"; 2680052bc5dSKumar Gala reg = <0x919c0 0x30>; 2690052bc5dSKumar Gala ranges; 2700052bc5dSKumar Gala 2710052bc5dSKumar Gala muram@80000 { 2720052bc5dSKumar Gala #address-cells = <1>; 2730052bc5dSKumar Gala #size-cells = <1>; 2740052bc5dSKumar Gala ranges = <0 0x80000 0x10000>; 2750052bc5dSKumar Gala 2760052bc5dSKumar Gala data@0 { 2770052bc5dSKumar Gala compatible = "fsl,cpm-muram-data"; 2780052bc5dSKumar Gala reg = <0 0x2000 0x9000 0x1000>; 2790052bc5dSKumar Gala }; 2800052bc5dSKumar Gala }; 2810052bc5dSKumar Gala 2820052bc5dSKumar Gala brg@919f0 { 2830052bc5dSKumar Gala compatible = "fsl,mpc8541-brg", 2840052bc5dSKumar Gala "fsl,cpm2-brg", 2850052bc5dSKumar Gala "fsl,cpm-brg"; 2860052bc5dSKumar Gala reg = <0x919f0 0x10 0x915f0 0x10>; 2870052bc5dSKumar Gala clock-frequency = <0>; 2880052bc5dSKumar Gala }; 2890052bc5dSKumar Gala 2900052bc5dSKumar Gala cpmpic: pic@90c00 { 2910052bc5dSKumar Gala interrupt-controller; 2920052bc5dSKumar Gala #address-cells = <0>; 2930052bc5dSKumar Gala #interrupt-cells = <2>; 2940052bc5dSKumar Gala interrupts = <46 2>; 2950052bc5dSKumar Gala interrupt-parent = <&mpic>; 2960052bc5dSKumar Gala reg = <0x90c00 0x80>; 2970052bc5dSKumar Gala compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 2980052bc5dSKumar Gala }; 2990052bc5dSKumar Gala }; 3000052bc5dSKumar Gala }; 3010052bc5dSKumar Gala 3020052bc5dSKumar Gala pci0: pci@e0008000 { 3030052bc5dSKumar Gala #interrupt-cells = <1>; 3040052bc5dSKumar Gala #size-cells = <2>; 3050052bc5dSKumar Gala #address-cells = <3>; 3060052bc5dSKumar Gala compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 3070052bc5dSKumar Gala device_type = "pci"; 3080052bc5dSKumar Gala reg = <0xe0008000 0x1000>; 3090052bc5dSKumar Gala clock-frequency = <66666666>; 3100052bc5dSKumar Gala interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 3110052bc5dSKumar Gala interrupt-map = < 3120052bc5dSKumar Gala /* IDSEL 28 */ 3130052bc5dSKumar Gala 0xe000 0 0 1 &mpic 2 1 31407c63839SDmitry Eremin-Solenikov 0xe000 0 0 2 &mpic 3 1 31507c63839SDmitry Eremin-Solenikov 0xe000 0 0 3 &mpic 6 1 31607c63839SDmitry Eremin-Solenikov 0xe000 0 0 4 &mpic 5 1 31707c63839SDmitry Eremin-Solenikov 31807c63839SDmitry Eremin-Solenikov /* IDSEL 11 */ 31907c63839SDmitry Eremin-Solenikov 0x5800 0 0 1 &mpic 6 1 32007c63839SDmitry Eremin-Solenikov 0x5800 0 0 2 &mpic 5 1 32107c63839SDmitry Eremin-Solenikov >; 3220052bc5dSKumar Gala 3230052bc5dSKumar Gala interrupt-parent = <&mpic>; 3240052bc5dSKumar Gala interrupts = <24 2>; 3250052bc5dSKumar Gala bus-range = <0 0>; 3260052bc5dSKumar Gala ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 3270052bc5dSKumar Gala 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 3280052bc5dSKumar Gala }; 3290052bc5dSKumar Gala}; 330