12874c5fdSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-or-later 20052bc5dSKumar Gala/* 30052bc5dSKumar Gala * TQM 8541 Device Tree Source 40052bc5dSKumar Gala * 50052bc5dSKumar Gala * Copyright 2008 Freescale Semiconductor Inc. 60052bc5dSKumar Gala */ 70052bc5dSKumar Gala 80052bc5dSKumar Gala/dts-v1/; 90052bc5dSKumar Gala 100052bc5dSKumar Gala/ { 114fb035f6SWolfgang Grandegger model = "tqc,tqm8541"; 124fb035f6SWolfgang Grandegger compatible = "tqc,tqm8541"; 130052bc5dSKumar Gala #address-cells = <1>; 140052bc5dSKumar Gala #size-cells = <1>; 150052bc5dSKumar Gala 160052bc5dSKumar Gala aliases { 170052bc5dSKumar Gala ethernet0 = &enet0; 180052bc5dSKumar Gala ethernet1 = &enet1; 190052bc5dSKumar Gala serial0 = &serial0; 200052bc5dSKumar Gala serial1 = &serial1; 210052bc5dSKumar Gala pci0 = &pci0; 220052bc5dSKumar Gala }; 230052bc5dSKumar Gala 240052bc5dSKumar Gala cpus { 250052bc5dSKumar Gala #address-cells = <1>; 260052bc5dSKumar Gala #size-cells = <0>; 270052bc5dSKumar Gala 280052bc5dSKumar Gala PowerPC,8541@0 { 290052bc5dSKumar Gala device_type = "cpu"; 300052bc5dSKumar Gala reg = <0>; 310052bc5dSKumar Gala d-cache-line-size = <32>; 320052bc5dSKumar Gala i-cache-line-size = <32>; 330052bc5dSKumar Gala d-cache-size = <32768>; 340052bc5dSKumar Gala i-cache-size = <32768>; 350052bc5dSKumar Gala timebase-frequency = <0>; 360052bc5dSKumar Gala bus-frequency = <0>; 370052bc5dSKumar Gala clock-frequency = <0>; 38c054065bSKumar Gala next-level-cache = <&L2>; 390052bc5dSKumar Gala }; 400052bc5dSKumar Gala }; 410052bc5dSKumar Gala 420052bc5dSKumar Gala memory { 430052bc5dSKumar Gala device_type = "memory"; 440052bc5dSKumar Gala reg = <0x00000000 0x10000000>; 450052bc5dSKumar Gala }; 460052bc5dSKumar Gala 47f67be814SKumar Gala soc@e0000000 { 480052bc5dSKumar Gala #address-cells = <1>; 490052bc5dSKumar Gala #size-cells = <1>; 500052bc5dSKumar Gala device_type = "soc"; 510052bc5dSKumar Gala ranges = <0x0 0xe0000000 0x100000>; 520052bc5dSKumar Gala bus-frequency = <0>; 530052bc5dSKumar Gala compatible = "fsl,mpc8541-immr", "simple-bus"; 540052bc5dSKumar Gala 55e1a22897SKumar Gala ecm-law@0 { 56e1a22897SKumar Gala compatible = "fsl,ecm-law"; 57e1a22897SKumar Gala reg = <0x0 0x1000>; 58e1a22897SKumar Gala fsl,num-laws = <8>; 59e1a22897SKumar Gala }; 60e1a22897SKumar Gala 61e1a22897SKumar Gala ecm@1000 { 62e1a22897SKumar Gala compatible = "fsl,mpc8541-ecm", "fsl,ecm"; 63e1a22897SKumar Gala reg = <0x1000 0x1000>; 64e1a22897SKumar Gala interrupts = <17 2>; 65e1a22897SKumar Gala interrupt-parent = <&mpic>; 66e1a22897SKumar Gala }; 67e1a22897SKumar Gala 680052bc5dSKumar Gala memory-controller@2000 { 69fe671772SKumar Gala compatible = "fsl,mpc8540-memory-controller"; 700052bc5dSKumar Gala reg = <0x2000 0x1000>; 710052bc5dSKumar Gala interrupt-parent = <&mpic>; 720052bc5dSKumar Gala interrupts = <18 2>; 730052bc5dSKumar Gala }; 740052bc5dSKumar Gala 75c054065bSKumar Gala L2: l2-cache-controller@20000 { 76fe671772SKumar Gala compatible = "fsl,mpc8540-l2-cache-controller"; 770052bc5dSKumar Gala reg = <0x20000 0x1000>; 780052bc5dSKumar Gala cache-line-size = <32>; 790052bc5dSKumar Gala cache-size = <0x40000>; // L2, 256K 800052bc5dSKumar Gala interrupt-parent = <&mpic>; 810052bc5dSKumar Gala interrupts = <16 2>; 820052bc5dSKumar Gala }; 830052bc5dSKumar Gala 840052bc5dSKumar Gala i2c@3000 { 850052bc5dSKumar Gala #address-cells = <1>; 860052bc5dSKumar Gala #size-cells = <0>; 870052bc5dSKumar Gala cell-index = <0>; 880052bc5dSKumar Gala compatible = "fsl-i2c"; 890052bc5dSKumar Gala reg = <0x3000 0x100>; 900052bc5dSKumar Gala interrupts = <43 2>; 910052bc5dSKumar Gala interrupt-parent = <&mpic>; 920052bc5dSKumar Gala dfsrr; 930052bc5dSKumar Gala 946467cae3SWolfgang Grandegger dtt@48 { 950f73a449SWolfgang Grandegger compatible = "national,lm75"; 966467cae3SWolfgang Grandegger reg = <0x48>; 970f73a449SWolfgang Grandegger }; 980f73a449SWolfgang Grandegger 990052bc5dSKumar Gala rtc@68 { 1000052bc5dSKumar Gala compatible = "dallas,ds1337"; 1010052bc5dSKumar Gala reg = <0x68>; 1020052bc5dSKumar Gala }; 1030052bc5dSKumar Gala }; 1040052bc5dSKumar Gala 105dee80553SKumar Gala dma@21300 { 106dee80553SKumar Gala #address-cells = <1>; 107dee80553SKumar Gala #size-cells = <1>; 108dee80553SKumar Gala compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; 109dee80553SKumar Gala reg = <0x21300 0x4>; 110dee80553SKumar Gala ranges = <0x0 0x21100 0x200>; 111dee80553SKumar Gala cell-index = <0>; 112dee80553SKumar Gala dma-channel@0 { 113dee80553SKumar Gala compatible = "fsl,mpc8541-dma-channel", 114dee80553SKumar Gala "fsl,eloplus-dma-channel"; 115dee80553SKumar Gala reg = <0x0 0x80>; 116dee80553SKumar Gala cell-index = <0>; 117dee80553SKumar Gala interrupt-parent = <&mpic>; 118dee80553SKumar Gala interrupts = <20 2>; 119dee80553SKumar Gala }; 120dee80553SKumar Gala dma-channel@80 { 121dee80553SKumar Gala compatible = "fsl,mpc8541-dma-channel", 122dee80553SKumar Gala "fsl,eloplus-dma-channel"; 123dee80553SKumar Gala reg = <0x80 0x80>; 124dee80553SKumar Gala cell-index = <1>; 125dee80553SKumar Gala interrupt-parent = <&mpic>; 126dee80553SKumar Gala interrupts = <21 2>; 127dee80553SKumar Gala }; 128dee80553SKumar Gala dma-channel@100 { 129dee80553SKumar Gala compatible = "fsl,mpc8541-dma-channel", 130dee80553SKumar Gala "fsl,eloplus-dma-channel"; 131dee80553SKumar Gala reg = <0x100 0x80>; 132dee80553SKumar Gala cell-index = <2>; 133dee80553SKumar Gala interrupt-parent = <&mpic>; 134dee80553SKumar Gala interrupts = <22 2>; 135dee80553SKumar Gala }; 136dee80553SKumar Gala dma-channel@180 { 137dee80553SKumar Gala compatible = "fsl,mpc8541-dma-channel", 138dee80553SKumar Gala "fsl,eloplus-dma-channel"; 139dee80553SKumar Gala reg = <0x180 0x80>; 140dee80553SKumar Gala cell-index = <3>; 141dee80553SKumar Gala interrupt-parent = <&mpic>; 142dee80553SKumar Gala interrupts = <23 2>; 143dee80553SKumar Gala }; 144dee80553SKumar Gala }; 145dee80553SKumar Gala 14684ba4a58SAnton Vorontsov enet0: ethernet@24000 { 14784ba4a58SAnton Vorontsov #address-cells = <1>; 14884ba4a58SAnton Vorontsov #size-cells = <1>; 14984ba4a58SAnton Vorontsov cell-index = <0>; 15084ba4a58SAnton Vorontsov device_type = "network"; 15184ba4a58SAnton Vorontsov model = "TSEC"; 15284ba4a58SAnton Vorontsov compatible = "gianfar"; 15384ba4a58SAnton Vorontsov reg = <0x24000 0x1000>; 15484ba4a58SAnton Vorontsov ranges = <0x0 0x24000 0x1000>; 15584ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 15684ba4a58SAnton Vorontsov interrupts = <29 2 30 2 34 2>; 15784ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 15884ba4a58SAnton Vorontsov tbi-handle = <&tbi0>; 15984ba4a58SAnton Vorontsov phy-handle = <&phy2>; 16084ba4a58SAnton Vorontsov 16184ba4a58SAnton Vorontsov mdio@520 { 1620052bc5dSKumar Gala #address-cells = <1>; 1630052bc5dSKumar Gala #size-cells = <0>; 1640052bc5dSKumar Gala compatible = "fsl,gianfar-mdio"; 16584ba4a58SAnton Vorontsov reg = <0x520 0x20>; 1660052bc5dSKumar Gala 1670052bc5dSKumar Gala phy1: ethernet-phy@1 { 1680052bc5dSKumar Gala interrupt-parent = <&mpic>; 1690052bc5dSKumar Gala interrupts = <8 1>; 1700052bc5dSKumar Gala reg = <1>; 1710052bc5dSKumar Gala }; 1720052bc5dSKumar Gala phy2: ethernet-phy@2 { 1730052bc5dSKumar Gala interrupt-parent = <&mpic>; 1740052bc5dSKumar Gala interrupts = <8 1>; 1750052bc5dSKumar Gala reg = <2>; 1760052bc5dSKumar Gala }; 1770052bc5dSKumar Gala phy3: ethernet-phy@3 { 1780052bc5dSKumar Gala interrupt-parent = <&mpic>; 1790052bc5dSKumar Gala interrupts = <8 1>; 1800052bc5dSKumar Gala reg = <3>; 1810052bc5dSKumar Gala }; 182b31a1d8bSAndy Fleming tbi0: tbi-phy@11 { 183b31a1d8bSAndy Fleming reg = <0x11>; 184b31a1d8bSAndy Fleming device_type = "tbi-phy"; 185b31a1d8bSAndy Fleming }; 186b31a1d8bSAndy Fleming }; 18784ba4a58SAnton Vorontsov }; 188b31a1d8bSAndy Fleming 18984ba4a58SAnton Vorontsov enet1: ethernet@25000 { 19084ba4a58SAnton Vorontsov #address-cells = <1>; 19184ba4a58SAnton Vorontsov #size-cells = <1>; 19284ba4a58SAnton Vorontsov cell-index = <1>; 19384ba4a58SAnton Vorontsov device_type = "network"; 19484ba4a58SAnton Vorontsov model = "TSEC"; 19584ba4a58SAnton Vorontsov compatible = "gianfar"; 19684ba4a58SAnton Vorontsov reg = <0x25000 0x1000>; 19784ba4a58SAnton Vorontsov ranges = <0x0 0x25000 0x1000>; 19884ba4a58SAnton Vorontsov local-mac-address = [ 00 00 00 00 00 00 ]; 19984ba4a58SAnton Vorontsov interrupts = <35 2 36 2 40 2>; 20084ba4a58SAnton Vorontsov interrupt-parent = <&mpic>; 20184ba4a58SAnton Vorontsov tbi-handle = <&tbi1>; 20284ba4a58SAnton Vorontsov phy-handle = <&phy1>; 20384ba4a58SAnton Vorontsov 20484ba4a58SAnton Vorontsov mdio@520 { 205b31a1d8bSAndy Fleming #address-cells = <1>; 206b31a1d8bSAndy Fleming #size-cells = <0>; 207b31a1d8bSAndy Fleming compatible = "fsl,gianfar-tbi"; 20884ba4a58SAnton Vorontsov reg = <0x520 0x20>; 209b31a1d8bSAndy Fleming 210b31a1d8bSAndy Fleming tbi1: tbi-phy@11 { 211b31a1d8bSAndy Fleming reg = <0x11>; 212b31a1d8bSAndy Fleming device_type = "tbi-phy"; 213b31a1d8bSAndy Fleming }; 2140052bc5dSKumar Gala }; 2150052bc5dSKumar Gala }; 2160052bc5dSKumar Gala 2170052bc5dSKumar Gala serial0: serial@4500 { 2180052bc5dSKumar Gala cell-index = <0>; 2190052bc5dSKumar Gala device_type = "serial"; 220f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 2210052bc5dSKumar Gala reg = <0x4500 0x100>; // reg base, size 2220052bc5dSKumar Gala clock-frequency = <0>; // should we fill in in uboot? 2230052bc5dSKumar Gala interrupts = <42 2>; 2240052bc5dSKumar Gala interrupt-parent = <&mpic>; 2250052bc5dSKumar Gala }; 2260052bc5dSKumar Gala 2270052bc5dSKumar Gala serial1: serial@4600 { 2280052bc5dSKumar Gala cell-index = <1>; 2290052bc5dSKumar Gala device_type = "serial"; 230f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 2310052bc5dSKumar Gala reg = <0x4600 0x100>; // reg base, size 2320052bc5dSKumar Gala clock-frequency = <0>; // should we fill in in uboot? 2330052bc5dSKumar Gala interrupts = <42 2>; 2340052bc5dSKumar Gala interrupt-parent = <&mpic>; 2350052bc5dSKumar Gala }; 2360052bc5dSKumar Gala 2373fd44736SKim Phillips crypto@30000 { 2383fd44736SKim Phillips compatible = "fsl,sec2.0"; 2393fd44736SKim Phillips reg = <0x30000 0x10000>; 2403fd44736SKim Phillips interrupts = <45 2>; 2413fd44736SKim Phillips interrupt-parent = <&mpic>; 2423fd44736SKim Phillips fsl,num-channels = <4>; 2433fd44736SKim Phillips fsl,channel-fifo-len = <24>; 2443fd44736SKim Phillips fsl,exec-units-mask = <0x7e>; 2453fd44736SKim Phillips fsl,descriptor-types-mask = <0x01010ebf>; 2463fd44736SKim Phillips }; 2473fd44736SKim Phillips 2480052bc5dSKumar Gala mpic: pic@40000 { 2490052bc5dSKumar Gala interrupt-controller; 2500052bc5dSKumar Gala #address-cells = <0>; 2510052bc5dSKumar Gala #interrupt-cells = <2>; 2520052bc5dSKumar Gala reg = <0x40000 0x40000>; 2530052bc5dSKumar Gala device_type = "open-pic"; 254acd4b715SKumar Gala compatible = "chrp,open-pic"; 2550052bc5dSKumar Gala }; 2560052bc5dSKumar Gala 2570052bc5dSKumar Gala cpm@919c0 { 2580052bc5dSKumar Gala #address-cells = <1>; 2590052bc5dSKumar Gala #size-cells = <1>; 2600052bc5dSKumar Gala compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus"; 2610052bc5dSKumar Gala reg = <0x919c0 0x30>; 2620052bc5dSKumar Gala ranges; 2630052bc5dSKumar Gala 2640052bc5dSKumar Gala muram@80000 { 2650052bc5dSKumar Gala #address-cells = <1>; 2660052bc5dSKumar Gala #size-cells = <1>; 2670052bc5dSKumar Gala ranges = <0 0x80000 0x10000>; 2680052bc5dSKumar Gala 2690052bc5dSKumar Gala data@0 { 2700052bc5dSKumar Gala compatible = "fsl,cpm-muram-data"; 2710052bc5dSKumar Gala reg = <0 0x2000 0x9000 0x1000>; 2720052bc5dSKumar Gala }; 2730052bc5dSKumar Gala }; 2740052bc5dSKumar Gala 2750052bc5dSKumar Gala brg@919f0 { 2760052bc5dSKumar Gala compatible = "fsl,mpc8541-brg", 2770052bc5dSKumar Gala "fsl,cpm2-brg", 2780052bc5dSKumar Gala "fsl,cpm-brg"; 2790052bc5dSKumar Gala reg = <0x919f0 0x10 0x915f0 0x10>; 2800052bc5dSKumar Gala clock-frequency = <0>; 2810052bc5dSKumar Gala }; 2820052bc5dSKumar Gala 2830052bc5dSKumar Gala cpmpic: pic@90c00 { 2840052bc5dSKumar Gala interrupt-controller; 2850052bc5dSKumar Gala #address-cells = <0>; 2860052bc5dSKumar Gala #interrupt-cells = <2>; 2870052bc5dSKumar Gala interrupts = <46 2>; 2880052bc5dSKumar Gala interrupt-parent = <&mpic>; 2890052bc5dSKumar Gala reg = <0x90c00 0x80>; 2900052bc5dSKumar Gala compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 2910052bc5dSKumar Gala }; 2920052bc5dSKumar Gala }; 2930052bc5dSKumar Gala }; 2940052bc5dSKumar Gala 2950052bc5dSKumar Gala pci0: pci@e0008000 { 2960052bc5dSKumar Gala #interrupt-cells = <1>; 2970052bc5dSKumar Gala #size-cells = <2>; 2980052bc5dSKumar Gala #address-cells = <3>; 2990052bc5dSKumar Gala compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 3000052bc5dSKumar Gala device_type = "pci"; 3010052bc5dSKumar Gala reg = <0xe0008000 0x1000>; 3020052bc5dSKumar Gala clock-frequency = <66666666>; 3030052bc5dSKumar Gala interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 3040052bc5dSKumar Gala interrupt-map = < 3050052bc5dSKumar Gala /* IDSEL 28 */ 3060052bc5dSKumar Gala 0xe000 0 0 1 &mpic 2 1 30707c63839SDmitry Eremin-Solenikov 0xe000 0 0 2 &mpic 3 1 30807c63839SDmitry Eremin-Solenikov 0xe000 0 0 3 &mpic 6 1 30907c63839SDmitry Eremin-Solenikov 0xe000 0 0 4 &mpic 5 1 31007c63839SDmitry Eremin-Solenikov 31107c63839SDmitry Eremin-Solenikov /* IDSEL 11 */ 31207c63839SDmitry Eremin-Solenikov 0x5800 0 0 1 &mpic 6 1 31307c63839SDmitry Eremin-Solenikov 0x5800 0 0 2 &mpic 5 1 31407c63839SDmitry Eremin-Solenikov >; 3150052bc5dSKumar Gala 3160052bc5dSKumar Gala interrupt-parent = <&mpic>; 3170052bc5dSKumar Gala interrupts = <24 2>; 3180052bc5dSKumar Gala bus-range = <0 0>; 3190052bc5dSKumar Gala ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 3200052bc5dSKumar Gala 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 3210052bc5dSKumar Gala }; 3220052bc5dSKumar Gala}; 323