1/* 2 * TQM 8540 Device Tree Source 3 * 4 * Copyright 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "tqc,tqm8540"; 16 compatible = "tqc,tqm8540"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 ethernet2 = &enet2; 24 serial0 = &serial0; 25 serial1 = &serial1; 26 pci0 = &pci0; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8540@0 { 34 device_type = "cpu"; 35 reg = <0>; 36 d-cache-line-size = <32>; 37 i-cache-line-size = <32>; 38 d-cache-size = <32768>; 39 i-cache-size = <32768>; 40 timebase-frequency = <0>; 41 bus-frequency = <0>; 42 clock-frequency = <0>; 43 next-level-cache = <&L2>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x00000000 0x10000000>; 50 }; 51 52 soc@e0000000 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 device_type = "soc"; 56 ranges = <0x0 0xe0000000 0x100000>; 57 reg = <0xe0000000 0x200>; 58 bus-frequency = <0>; 59 compatible = "fsl,mpc8540-immr", "simple-bus"; 60 61 ecm-law@0 { 62 compatible = "fsl,ecm-law"; 63 reg = <0x0 0x1000>; 64 fsl,num-laws = <8>; 65 }; 66 67 ecm@1000 { 68 compatible = "fsl,mpc8540-ecm", "fsl,ecm"; 69 reg = <0x1000 0x1000>; 70 interrupts = <17 2>; 71 interrupt-parent = <&mpic>; 72 }; 73 74 memory-controller@2000 { 75 compatible = "fsl,mpc8540-memory-controller"; 76 reg = <0x2000 0x1000>; 77 interrupt-parent = <&mpic>; 78 interrupts = <18 2>; 79 }; 80 81 L2: l2-cache-controller@20000 { 82 compatible = "fsl,mpc8540-l2-cache-controller"; 83 reg = <0x20000 0x1000>; 84 cache-line-size = <32>; 85 cache-size = <0x40000>; // L2, 256K 86 interrupt-parent = <&mpic>; 87 interrupts = <16 2>; 88 }; 89 90 i2c@3000 { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 cell-index = <0>; 94 compatible = "fsl-i2c"; 95 reg = <0x3000 0x100>; 96 interrupts = <43 2>; 97 interrupt-parent = <&mpic>; 98 dfsrr; 99 100 dtt@48 { 101 compatible = "national,lm75"; 102 reg = <0x48>; 103 }; 104 105 rtc@68 { 106 compatible = "dallas,ds1337"; 107 reg = <0x68>; 108 }; 109 }; 110 111 dma@21300 { 112 #address-cells = <1>; 113 #size-cells = <1>; 114 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 115 reg = <0x21300 0x4>; 116 ranges = <0x0 0x21100 0x200>; 117 cell-index = <0>; 118 dma-channel@0 { 119 compatible = "fsl,mpc8540-dma-channel", 120 "fsl,eloplus-dma-channel"; 121 reg = <0x0 0x80>; 122 cell-index = <0>; 123 interrupt-parent = <&mpic>; 124 interrupts = <20 2>; 125 }; 126 dma-channel@80 { 127 compatible = "fsl,mpc8540-dma-channel", 128 "fsl,eloplus-dma-channel"; 129 reg = <0x80 0x80>; 130 cell-index = <1>; 131 interrupt-parent = <&mpic>; 132 interrupts = <21 2>; 133 }; 134 dma-channel@100 { 135 compatible = "fsl,mpc8540-dma-channel", 136 "fsl,eloplus-dma-channel"; 137 reg = <0x100 0x80>; 138 cell-index = <2>; 139 interrupt-parent = <&mpic>; 140 interrupts = <22 2>; 141 }; 142 dma-channel@180 { 143 compatible = "fsl,mpc8540-dma-channel", 144 "fsl,eloplus-dma-channel"; 145 reg = <0x180 0x80>; 146 cell-index = <3>; 147 interrupt-parent = <&mpic>; 148 interrupts = <23 2>; 149 }; 150 }; 151 152 enet0: ethernet@24000 { 153 #address-cells = <1>; 154 #size-cells = <1>; 155 cell-index = <0>; 156 device_type = "network"; 157 model = "TSEC"; 158 compatible = "gianfar"; 159 reg = <0x24000 0x1000>; 160 ranges = <0x0 0x24000 0x1000>; 161 local-mac-address = [ 00 00 00 00 00 00 ]; 162 interrupts = <29 2 30 2 34 2>; 163 interrupt-parent = <&mpic>; 164 phy-handle = <&phy2>; 165 166 mdio@520 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 compatible = "fsl,gianfar-mdio"; 170 reg = <0x520 0x20>; 171 172 phy1: ethernet-phy@1 { 173 interrupt-parent = <&mpic>; 174 interrupts = <8 1>; 175 reg = <1>; 176 device_type = "ethernet-phy"; 177 }; 178 phy2: ethernet-phy@2 { 179 interrupt-parent = <&mpic>; 180 interrupts = <8 1>; 181 reg = <2>; 182 device_type = "ethernet-phy"; 183 }; 184 phy3: ethernet-phy@3 { 185 interrupt-parent = <&mpic>; 186 interrupts = <8 1>; 187 reg = <3>; 188 device_type = "ethernet-phy"; 189 }; 190 tbi0: tbi-phy@11 { 191 reg = <0x11>; 192 device_type = "tbi-phy"; 193 }; 194 }; 195 }; 196 197 enet1: ethernet@25000 { 198 #address-cells = <1>; 199 #size-cells = <1>; 200 cell-index = <1>; 201 device_type = "network"; 202 model = "TSEC"; 203 compatible = "gianfar"; 204 reg = <0x25000 0x1000>; 205 ranges = <0x0 0x25000 0x1000>; 206 local-mac-address = [ 00 00 00 00 00 00 ]; 207 interrupts = <35 2 36 2 40 2>; 208 interrupt-parent = <&mpic>; 209 phy-handle = <&phy1>; 210 211 mdio@520 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 compatible = "fsl,gianfar-tbi"; 215 reg = <0x520 0x20>; 216 217 tbi1: tbi-phy@11 { 218 reg = <0x11>; 219 device_type = "tbi-phy"; 220 }; 221 }; 222 }; 223 224 enet2: ethernet@26000 { 225 #address-cells = <1>; 226 #size-cells = <1>; 227 cell-index = <2>; 228 device_type = "network"; 229 model = "FEC"; 230 compatible = "gianfar"; 231 reg = <0x26000 0x1000>; 232 ranges = <0x0 0x26000 0x1000>; 233 local-mac-address = [ 00 00 00 00 00 00 ]; 234 interrupts = <41 2>; 235 interrupt-parent = <&mpic>; 236 phy-handle = <&phy3>; 237 238 mdio@520 { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 compatible = "fsl,gianfar-tbi"; 242 reg = <0x520 0x20>; 243 244 tbi2: tbi-phy@11 { 245 reg = <0x11>; 246 device_type = "tbi-phy"; 247 }; 248 }; 249 }; 250 251 serial0: serial@4500 { 252 cell-index = <0>; 253 device_type = "serial"; 254 compatible = "ns16550"; 255 reg = <0x4500 0x100>; // reg base, size 256 clock-frequency = <0>; // should we fill in in uboot? 257 interrupts = <42 2>; 258 interrupt-parent = <&mpic>; 259 }; 260 261 serial1: serial@4600 { 262 cell-index = <1>; 263 device_type = "serial"; 264 compatible = "ns16550"; 265 reg = <0x4600 0x100>; // reg base, size 266 clock-frequency = <0>; // should we fill in in uboot? 267 interrupts = <42 2>; 268 interrupt-parent = <&mpic>; 269 }; 270 271 mpic: pic@40000 { 272 interrupt-controller; 273 #address-cells = <0>; 274 #interrupt-cells = <2>; 275 reg = <0x40000 0x40000>; 276 device_type = "open-pic"; 277 compatible = "chrp,open-pic"; 278 }; 279 }; 280 281 pci0: pci@e0008000 { 282 #interrupt-cells = <1>; 283 #size-cells = <2>; 284 #address-cells = <3>; 285 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 286 device_type = "pci"; 287 reg = <0xe0008000 0x1000>; 288 clock-frequency = <66666666>; 289 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 290 interrupt-map = < 291 /* IDSEL 28 */ 292 0xe000 0 0 1 &mpic 2 1 293 0xe000 0 0 2 &mpic 3 1>; 294 295 interrupt-parent = <&mpic>; 296 interrupts = <24 2>; 297 bus-range = <0 0>; 298 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 299 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 300 }; 301}; 302