1/*
2 * TQM5200 board Device Tree Source
3 *
4 * Copyright (C) 2007 Semihalf
5 * Marian Balakowicz <m8@semihalf.com>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/*
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
18
19/ {
20	model = "tqc,tqm5200";
21	compatible = "tqc,tqm5200";
22	#address-cells = <1>;
23	#size-cells = <1>;
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		PowerPC,5200@0 {
30			device_type = "cpu";
31			reg = <0>;
32			d-cache-line-size = <20>;
33			i-cache-line-size = <20>;
34			d-cache-size = <4000>;		// L1, 16K
35			i-cache-size = <4000>;		// L1, 16K
36			timebase-frequency = <0>;	// from bootloader
37			bus-frequency = <0>;		// from bootloader
38			clock-frequency = <0>;		// from bootloader
39		};
40	};
41
42	memory {
43		device_type = "memory";
44		reg = <00000000 04000000>;	// 64MB
45	};
46
47	soc5200@f0000000 {
48		model = "fsl,mpc5200";
49		compatible = "fsl,mpc5200";
50		revision = "";			// from bootloader
51		device_type = "soc";
52		ranges = <0 f0000000 0000c000>;
53		reg = <f0000000 00000100>;
54		bus-frequency = <0>;		// from bootloader
55		system-frequency = <0>;		// from bootloader
56
57		cdm@200 {
58			compatible = "mpc5200-cdm";
59			reg = <200 38>;
60		};
61
62		mpc5200_pic: pic@500 {
63			// 5200 interrupts are encoded into two levels;
64			interrupt-controller;
65			#interrupt-cells = <3>;
66			compatible = "mpc5200-pic";
67			reg = <500 80>;
68		};
69
70		gpt@600 {	// General Purpose Timer
71			compatible = "fsl,mpc5200-gpt";
72			reg = <600 10>;
73			interrupts = <1 9 0>;
74			interrupt-parent = <&mpc5200_pic>;
75			fsl,has-wdt;
76		};
77
78		gpio@b00 {
79			compatible = "mpc5200-gpio";
80			reg = <b00 40>;
81			interrupts = <1 7 0>;
82			interrupt-parent = <&mpc5200_pic>;
83		};
84
85		usb@1000 {
86			compatible = "mpc5200-ohci","ohci-be";
87			reg = <1000 ff>;
88			interrupts = <2 6 0>;
89			interrupt-parent = <&mpc5200_pic>;
90		};
91
92		dma-controller@1200 {
93			compatible = "mpc5200-bestcomm";
94			reg = <1200 80>;
95			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
96			              3 4 0  3 5 0  3 6 0  3 7 0
97			              3 8 0  3 9 0  3 a 0  3 b 0
98			              3 c 0  3 d 0  3 e 0  3 f 0>;
99			interrupt-parent = <&mpc5200_pic>;
100		};
101
102		xlb@1f00 {
103			compatible = "mpc5200-xlb";
104			reg = <1f00 100>;
105		};
106
107		serial@2000 {		// PSC1
108			device_type = "serial";
109			compatible = "mpc5200-psc-uart";
110			port-number = <0>;  // Logical port assignment
111			reg = <2000 100>;
112			interrupts = <2 1 0>;
113			interrupt-parent = <&mpc5200_pic>;
114		};
115
116		serial@2200 {		// PSC2
117			device_type = "serial";
118			compatible = "mpc5200-psc-uart";
119			port-number = <1>;  // Logical port assignment
120			reg = <2200 100>;
121			interrupts = <2 2 0>;
122			interrupt-parent = <&mpc5200_pic>;
123		};
124
125		serial@2400 {		// PSC3
126			device_type = "serial";
127			compatible = "mpc5200-psc-uart";
128			port-number = <2>;  // Logical port assignment
129			reg = <2400 100>;
130			interrupts = <2 3 0>;
131			interrupt-parent = <&mpc5200_pic>;
132		};
133
134		ethernet@3000 {
135			device_type = "network";
136			compatible = "mpc5200-fec";
137			reg = <3000 800>;
138			local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */
139			interrupts = <2 5 0>;
140			interrupt-parent = <&mpc5200_pic>;
141		};
142
143		ata@3a00 {
144			compatible = "mpc5200-ata";
145			reg = <3a00 100>;
146			interrupts = <2 7 0>;
147			interrupt-parent = <&mpc5200_pic>;
148		};
149
150		i2c@3d40 {
151			compatible = "mpc5200-i2c","fsl-i2c";
152			reg = <3d40 40>;
153			interrupts = <2 10 0>;
154			interrupt-parent = <&mpc5200_pic>;
155			fsl5200-clocking;
156		};
157
158		sram@8000 {
159			compatible = "mpc5200-sram";
160			reg = <8000 4000>;
161		};
162	};
163
164	pci@f0000d00 {
165		#interrupt-cells = <1>;
166		#size-cells = <2>;
167		#address-cells = <3>;
168		device_type = "pci";
169		compatible = "fsl,mpc5200-pci";
170		reg = <f0000d00 100>;
171		interrupt-map-mask = <f800 0 0 7>;
172		interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
173				 c000 0 0 2 &mpc5200_pic 0 0 3
174				 c000 0 0 3 &mpc5200_pic 0 0 3
175				 c000 0 0 4 &mpc5200_pic 0 0 3>;
176		clock-frequency = <0>; // From boot loader
177		interrupts = <2 8 0 2 9 0 2 a 0>;
178		interrupt-parent = <&mpc5200_pic>;
179		bus-range = <0 0>;
180		ranges = <42000000 0 80000000 80000000 0 10000000
181			  02000000 0 90000000 90000000 0 10000000
182			  01000000 0 00000000 a0000000 0 01000000>;
183	};
184};
185