16c712090SMadhulika Madishetty/*
26c712090SMadhulika Madishetty * Device Tree Source for AMCC Redwood(460SX)
36c712090SMadhulika Madishetty *
46c712090SMadhulika Madishetty * Copyright 2008 AMCC <tmarri@amcc.com>
56c712090SMadhulika Madishetty *
66c712090SMadhulika Madishetty * This file is licensed under the terms of the GNU General Public
76c712090SMadhulika Madishetty * License version 2.  This program is licensed "as is" without
86c712090SMadhulika Madishetty * any warranty of any kind, whether express or implied.
96c712090SMadhulika Madishetty */
106c712090SMadhulika Madishetty
116c712090SMadhulika Madishetty/dts-v1/;
126c712090SMadhulika Madishetty
136c712090SMadhulika Madishetty/ {
146c712090SMadhulika Madishetty	#address-cells = <2>;
156c712090SMadhulika Madishetty	#size-cells = <1>;
166c712090SMadhulika Madishetty	model = "amcc,redwood";
176c712090SMadhulika Madishetty	compatible = "amcc,redwood";
186c712090SMadhulika Madishetty	dcr-parent = <&{/cpus/cpu@0}>;
196c712090SMadhulika Madishetty
206c712090SMadhulika Madishetty	aliases {
216c712090SMadhulika Madishetty		ethernet0 = &EMAC0;
226c712090SMadhulika Madishetty		serial0 = &UART0;
236c712090SMadhulika Madishetty	};
246c712090SMadhulika Madishetty
256c712090SMadhulika Madishetty	cpus {
266c712090SMadhulika Madishetty		#address-cells = <1>;
276c712090SMadhulika Madishetty		#size-cells = <0>;
286c712090SMadhulika Madishetty
296c712090SMadhulika Madishetty		cpu@0 {
306c712090SMadhulika Madishetty			device_type = "cpu";
316c712090SMadhulika Madishetty			model = "PowerPC,460SX";
326c712090SMadhulika Madishetty			reg = <0x00000000>;
336c712090SMadhulika Madishetty			clock-frequency = <0>; /* Filled in by U-Boot */
346c712090SMadhulika Madishetty			timebase-frequency = <0>; /* Filled in by U-Boot */
356c712090SMadhulika Madishetty			i-cache-line-size = <32>;
366c712090SMadhulika Madishetty			d-cache-line-size = <32>;
376c712090SMadhulika Madishetty			i-cache-size = <32768>;
386c712090SMadhulika Madishetty			d-cache-size = <32768>;
396c712090SMadhulika Madishetty			dcr-controller;
406c712090SMadhulika Madishetty			dcr-access-method = "native";
416c712090SMadhulika Madishetty		};
426c712090SMadhulika Madishetty	};
436c712090SMadhulika Madishetty
446c712090SMadhulika Madishetty	memory {
456c712090SMadhulika Madishetty		device_type = "memory";
466c712090SMadhulika Madishetty		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
476c712090SMadhulika Madishetty	};
486c712090SMadhulika Madishetty
496c712090SMadhulika Madishetty	UIC0: interrupt-controller0 {
506c712090SMadhulika Madishetty		compatible = "ibm,uic-460sx","ibm,uic";
516c712090SMadhulika Madishetty		interrupt-controller;
526c712090SMadhulika Madishetty		cell-index = <0>;
536c712090SMadhulika Madishetty		dcr-reg = <0x0c0 0x009>;
546c712090SMadhulika Madishetty		#address-cells = <0>;
556c712090SMadhulika Madishetty		#size-cells = <0>;
566c712090SMadhulika Madishetty		#interrupt-cells = <2>;
576c712090SMadhulika Madishetty	};
586c712090SMadhulika Madishetty
596c712090SMadhulika Madishetty	UIC1: interrupt-controller1 {
606c712090SMadhulika Madishetty		compatible = "ibm,uic-460sx","ibm,uic";
616c712090SMadhulika Madishetty		interrupt-controller;
626c712090SMadhulika Madishetty		cell-index = <1>;
636c712090SMadhulika Madishetty		dcr-reg = <0x0d0 0x009>;
646c712090SMadhulika Madishetty		#address-cells = <0>;
656c712090SMadhulika Madishetty		#size-cells = <0>;
666c712090SMadhulika Madishetty		#interrupt-cells = <2>;
676c712090SMadhulika Madishetty		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
686c712090SMadhulika Madishetty		interrupt-parent = <&UIC0>;
696c712090SMadhulika Madishetty	};
706c712090SMadhulika Madishetty
716c712090SMadhulika Madishetty	UIC2: interrupt-controller2 {
726c712090SMadhulika Madishetty		compatible = "ibm,uic-460sx","ibm,uic";
736c712090SMadhulika Madishetty		interrupt-controller;
746c712090SMadhulika Madishetty		cell-index = <2>;
756c712090SMadhulika Madishetty		dcr-reg = <0x0e0 0x009>;
766c712090SMadhulika Madishetty		#address-cells = <0>;
776c712090SMadhulika Madishetty		#size-cells = <0>;
786c712090SMadhulika Madishetty		#interrupt-cells = <2>;
796c712090SMadhulika Madishetty		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
806c712090SMadhulika Madishetty		interrupt-parent = <&UIC0>;
816c712090SMadhulika Madishetty	};
826c712090SMadhulika Madishetty
836c712090SMadhulika Madishetty	UIC3: interrupt-controller3 {
846c712090SMadhulika Madishetty		compatible = "ibm,uic-460sx","ibm,uic";
856c712090SMadhulika Madishetty		interrupt-controller;
866c712090SMadhulika Madishetty		cell-index = <3>;
876c712090SMadhulika Madishetty		dcr-reg = <0x0f0 0x009>;
886c712090SMadhulika Madishetty		#address-cells = <0>;
896c712090SMadhulika Madishetty		#size-cells = <0>;
906c712090SMadhulika Madishetty		#interrupt-cells = <2>;
916c712090SMadhulika Madishetty		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
926c712090SMadhulika Madishetty		interrupt-parent = <&UIC0>;
936c712090SMadhulika Madishetty	};
946c712090SMadhulika Madishetty
956c712090SMadhulika Madishetty	SDR0: sdr {
966c712090SMadhulika Madishetty		compatible = "ibm,sdr-460sx";
976c712090SMadhulika Madishetty		dcr-reg = <0x00e 0x002>;
986c712090SMadhulika Madishetty	};
996c712090SMadhulika Madishetty
1006c712090SMadhulika Madishetty	CPR0: cpr {
1016c712090SMadhulika Madishetty		compatible = "ibm,cpr-460sx";
1026c712090SMadhulika Madishetty		dcr-reg = <0x00c 0x002>;
1036c712090SMadhulika Madishetty	};
1046c712090SMadhulika Madishetty
1056c712090SMadhulika Madishetty	plb {
1066c712090SMadhulika Madishetty		compatible = "ibm,plb-460sx", "ibm,plb4";
1076c712090SMadhulika Madishetty		#address-cells = <2>;
1086c712090SMadhulika Madishetty		#size-cells = <1>;
1096c712090SMadhulika Madishetty		ranges;
1106c712090SMadhulika Madishetty		clock-frequency = <0>; /* Filled in by U-Boot */
1116c712090SMadhulika Madishetty
1126c712090SMadhulika Madishetty		SDRAM0: sdram {
1136c712090SMadhulika Madishetty			compatible = "ibm,sdram-460sx", "ibm,sdram-405gp";
1146c712090SMadhulika Madishetty			dcr-reg = <0x010 0x002>;
1156c712090SMadhulika Madishetty		};
1166c712090SMadhulika Madishetty
1176c712090SMadhulika Madishetty		MAL0: mcmal {
1186c712090SMadhulika Madishetty			compatible = "ibm,mcmal-460sx", "ibm,mcmal2";
1196c712090SMadhulika Madishetty			dcr-reg = <0x180 0x62>;
1206c712090SMadhulika Madishetty			num-tx-chans = <4>;
1216c712090SMadhulika Madishetty			num-rx-chans = <32>;
1226c712090SMadhulika Madishetty			#address-cells = <1>;
1236c712090SMadhulika Madishetty			#size-cells = <1>;
1246c712090SMadhulika Madishetty			interrupt-parent = <&UIC1>;
1256c712090SMadhulika Madishetty			interrupts = <	/*TXEOB*/ 0x6 0x4
1266c712090SMadhulika Madishetty					/*RXEOB*/ 0x7 0x4
1276c712090SMadhulika Madishetty					/*SERR*/  0x1 0x4
1286c712090SMadhulika Madishetty					/*TXDE*/  0x2 0x4
1296c712090SMadhulika Madishetty					/*RXDE*/  0x3 0x4
1306c712090SMadhulika Madishetty					/*COAL TX0*/ 0x18 0x2
1316c712090SMadhulika Madishetty					/*COAL TX1*/ 0x19 0x2
1326c712090SMadhulika Madishetty					/*COAL TX2*/ 0x1a 0x2
1336c712090SMadhulika Madishetty					/*COAL TX3*/ 0x1b 0x2
1346c712090SMadhulika Madishetty					/*COAL RX0*/ 0x1c 0x2
1356c712090SMadhulika Madishetty					/*COAL RX1*/ 0x1d 0x2
1366c712090SMadhulika Madishetty					/*COAL RX2*/ 0x1e 0x2
1376c712090SMadhulika Madishetty					/*COAL RX3*/ 0x1f 0x2>;
1386c712090SMadhulika Madishetty		};
1396c712090SMadhulika Madishetty
1406c712090SMadhulika Madishetty		POB0: opb {
1416c712090SMadhulika Madishetty			compatible = "ibm,opb-460sx", "ibm,opb";
1426c712090SMadhulika Madishetty			#address-cells = <1>;
1436c712090SMadhulika Madishetty			#size-cells = <1>;
1446c712090SMadhulika Madishetty			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
1456c712090SMadhulika Madishetty			clock-frequency = <0>; /* Filled in by U-Boot */
1466c712090SMadhulika Madishetty
1476c712090SMadhulika Madishetty			EBC0: ebc {
1486c712090SMadhulika Madishetty				compatible = "ibm,ebc-460sx", "ibm,ebc";
1496c712090SMadhulika Madishetty				dcr-reg = <0x012 0x002>;
1506c712090SMadhulika Madishetty				#address-cells = <2>;
1516c712090SMadhulika Madishetty				#size-cells = <1>;
1526c712090SMadhulika Madishetty				clock-frequency = <0>; /* Filled in by U-Boot */
1536c712090SMadhulika Madishetty				/* ranges property is supplied by U-Boot */
1546c712090SMadhulika Madishetty				interrupts = <0x6 0x4>;
1556c712090SMadhulika Madishetty				interrupt-parent = <&UIC1>;
1566c712090SMadhulika Madishetty
1576c712090SMadhulika Madishetty				nor_flash@0,0 {
1586c712090SMadhulika Madishetty					compatible = "amd,s29gl512n", "cfi-flash";
1596c712090SMadhulika Madishetty					bank-width = <2>;
1606c712090SMadhulika Madishetty					reg = <0x0000000 0x00000000 0x04000000>;
1616c712090SMadhulika Madishetty					#address-cells = <1>;
1626c712090SMadhulika Madishetty					#size-cells = <1>;
1636c712090SMadhulika Madishetty					partition@0 {
1646c712090SMadhulika Madishetty						label = "kernel";
1656c712090SMadhulika Madishetty						reg = <0x00000000 0x001e0000>;
1666c712090SMadhulika Madishetty					};
1676c712090SMadhulika Madishetty					partition@1e0000 {
1686c712090SMadhulika Madishetty						label = "dtb";
1696c712090SMadhulika Madishetty						reg = <0x001e0000 0x00020000>;
1706c712090SMadhulika Madishetty					};
1716c712090SMadhulika Madishetty					partition@200000 {
1726c712090SMadhulika Madishetty						label = "ramdisk";
1736c712090SMadhulika Madishetty						reg = <0x00200000 0x01400000>;
1746c712090SMadhulika Madishetty					};
1756c712090SMadhulika Madishetty					partition@1600000 {
1766c712090SMadhulika Madishetty						label = "jffs2";
1776c712090SMadhulika Madishetty						reg = <0x01600000 0x00400000>;
1786c712090SMadhulika Madishetty					};
1796c712090SMadhulika Madishetty					partition@1a00000 {
1806c712090SMadhulika Madishetty						label = "user";
1816c712090SMadhulika Madishetty						reg = <0x01a00000 0x02560000>;
1826c712090SMadhulika Madishetty					};
1836c712090SMadhulika Madishetty					partition@3f60000 {
1846c712090SMadhulika Madishetty						label = "env";
1856c712090SMadhulika Madishetty						reg = <0x03f60000 0x00040000>;
1866c712090SMadhulika Madishetty					};
1876c712090SMadhulika Madishetty					partition@3fa0000 {
1886c712090SMadhulika Madishetty						label = "u-boot";
1896c712090SMadhulika Madishetty						reg = <0x03fa0000 0x00060000>;
1906c712090SMadhulika Madishetty					};
1916c712090SMadhulika Madishetty				};
1926c712090SMadhulika Madishetty			};
1936c712090SMadhulika Madishetty
1946c712090SMadhulika Madishetty			UART0: serial@ef600200 {
1956c712090SMadhulika Madishetty				device_type = "serial";
1966c712090SMadhulika Madishetty				compatible = "ns16550";
1976c712090SMadhulika Madishetty				reg = <0xef600200 0x00000008>;
1986c712090SMadhulika Madishetty				virtual-reg = <0xef600200>;
1996c712090SMadhulika Madishetty				clock-frequency = <0>; /* Filled in by U-Boot */
2006c712090SMadhulika Madishetty				current-speed = <0>; /* Filled in by U-Boot */
2016c712090SMadhulika Madishetty				interrupt-parent = <&UIC0>;
2026c712090SMadhulika Madishetty				interrupts = <0x0 0x4>;
2036c712090SMadhulika Madishetty			};
2046c712090SMadhulika Madishetty
2056c712090SMadhulika Madishetty			RGMII0: emac-rgmii@ef600900 {
2066c712090SMadhulika Madishetty				compatible = "ibm,rgmii-460sx", "ibm,rgmii";
2076c712090SMadhulika Madishetty				reg = <0xef600900 0x00000008>;
2086c712090SMadhulika Madishetty			};
2096c712090SMadhulika Madishetty
2106c712090SMadhulika Madishetty			EMAC0: ethernet@ef600a00 {
2116c712090SMadhulika Madishetty				device_type = "network";
2126c712090SMadhulika Madishetty				compatible = "ibm,emac-460sx", "ibm,emac4";
2136c712090SMadhulika Madishetty				interrupt-parent = <&EMAC0>;
2146c712090SMadhulika Madishetty				interrupts = <0x0 0x1>;
2156c712090SMadhulika Madishetty				#interrupt-cells = <1>;
2166c712090SMadhulika Madishetty				#address-cells = <0>;
2176c712090SMadhulika Madishetty				#size-cells = <0>;
2186c712090SMadhulika Madishetty				interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
2196c712090SMadhulika Madishetty						 /*Wake*/   0x1 &UIC2 0x1d 0x4>;
2206c712090SMadhulika Madishetty				reg = <0xef600a00 0x00000070>;
2216c712090SMadhulika Madishetty				local-mac-address = [000000000000]; /* Filled in by U-Boot */
2226c712090SMadhulika Madishetty				mal-device = <&MAL0>;
2236c712090SMadhulika Madishetty				mal-tx-channel = <0>;
2246c712090SMadhulika Madishetty				mal-rx-channel = <0>;
2256c712090SMadhulika Madishetty				cell-index = <0>;
2266c712090SMadhulika Madishetty				max-frame-size = <9000>;
2276c712090SMadhulika Madishetty				rx-fifo-size = <4096>;
2286c712090SMadhulika Madishetty				tx-fifo-size = <2048>;
229835ad8e7SDave Mitchell				rx-fifo-size-gige = <16384>;
2306c712090SMadhulika Madishetty				phy-mode = "rgmii";
2316c712090SMadhulika Madishetty				phy-map = <0x00000000>;
2326c712090SMadhulika Madishetty				rgmii-device = <&RGMII0>;
2336c712090SMadhulika Madishetty				rgmii-channel = <0>;
2346c712090SMadhulika Madishetty				has-inverted-stacr-oc;
2356c712090SMadhulika Madishetty				has-new-stacr-staopc;
2366c712090SMadhulika Madishetty			};
237e2efc09eSTirumala Marri		};
23886bc917dSMichael Ellerman		PCIE0: pcie@d00000000 {
239e2efc09eSTirumala Marri			device_type = "pci";
240e2efc09eSTirumala Marri			#interrupt-cells = <1>;
241e2efc09eSTirumala Marri			#size-cells = <2>;
242e2efc09eSTirumala Marri			#address-cells = <3>;
243e2efc09eSTirumala Marri			compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
244e2efc09eSTirumala Marri			primary;
245e2efc09eSTirumala Marri			port = <0x0>; /* port number */
246e2efc09eSTirumala Marri			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
247e2efc09eSTirumala Marri			       0x0000000c 0x10000000 0x00001000>;	/* Registers */
248e2efc09eSTirumala Marri			dcr-reg = <0x100 0x020>;
249e2efc09eSTirumala Marri			sdr-base = <0x300>;
2506c712090SMadhulika Madishetty
251e2efc09eSTirumala Marri			/* Outbound ranges, one memory and one IO,
252e2efc09eSTirumala Marri			 * later cannot be changed
253e2efc09eSTirumala Marri			 */
254e2efc09eSTirumala Marri			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
255e2efc09eSTirumala Marri				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
256e2efc09eSTirumala Marri
257e2efc09eSTirumala Marri			/* Inbound 2GB range starting at 0 */
258e2efc09eSTirumala Marri			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
259e2efc09eSTirumala Marri
260e2efc09eSTirumala Marri			/* This drives busses 10 to 0x1f */
261e2efc09eSTirumala Marri			bus-range = <0x10 0x1f>;
262e2efc09eSTirumala Marri
263e2efc09eSTirumala Marri			/* Legacy interrupts (note the weird polarity, the bridge seems
264e2efc09eSTirumala Marri			 * to invert PCIe legacy interrupts).
265e2efc09eSTirumala Marri			 * We are de-swizzling here because the numbers are actually for
266e2efc09eSTirumala Marri			 * port of the root complex virtual P2P bridge. But I want
267e2efc09eSTirumala Marri			 * to avoid putting a node for it in the tree, so the numbers
268e2efc09eSTirumala Marri			 * below are basically de-swizzled numbers.
269e2efc09eSTirumala Marri			 * The real slot is on idsel 0, so the swizzling is 1:1
270e2efc09eSTirumala Marri			 */
271e2efc09eSTirumala Marri			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
272e2efc09eSTirumala Marri			interrupt-map = <
273e2efc09eSTirumala Marri				0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
274e2efc09eSTirumala Marri				0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
275e2efc09eSTirumala Marri				0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
276e2efc09eSTirumala Marri				0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
277e2efc09eSTirumala Marri		};
278e2efc09eSTirumala Marri
27986bc917dSMichael Ellerman		PCIE1: pcie@d20000000 {
280e2efc09eSTirumala Marri			device_type = "pci";
281e2efc09eSTirumala Marri			#interrupt-cells = <1>;
282e2efc09eSTirumala Marri			#size-cells = <2>;
283e2efc09eSTirumala Marri			#address-cells = <3>;
284e2efc09eSTirumala Marri			compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
285e2efc09eSTirumala Marri			primary;
286e2efc09eSTirumala Marri			port = <0x1>; /* port number */
287e2efc09eSTirumala Marri			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
288e2efc09eSTirumala Marri			       0x0000000c 0x10001000 0x00001000>;	/* Registers */
289e2efc09eSTirumala Marri			dcr-reg = <0x120 0x020>;
290e2efc09eSTirumala Marri			sdr-base = <0x340>;
291e2efc09eSTirumala Marri
292e2efc09eSTirumala Marri			/* Outbound ranges, one memory and one IO,
293e2efc09eSTirumala Marri			 * later cannot be changed
294e2efc09eSTirumala Marri			 */
295e2efc09eSTirumala Marri			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
296e2efc09eSTirumala Marri				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
297e2efc09eSTirumala Marri
298e2efc09eSTirumala Marri			/* Inbound 2GB range starting at 0 */
299e2efc09eSTirumala Marri			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
300e2efc09eSTirumala Marri
301e2efc09eSTirumala Marri			/* This drives busses 10 to 0x1f */
302e2efc09eSTirumala Marri			bus-range = <0x20 0x2f>;
303e2efc09eSTirumala Marri
304e2efc09eSTirumala Marri			/* Legacy interrupts (note the weird polarity, the bridge seems
305e2efc09eSTirumala Marri			 * to invert PCIe legacy interrupts).
306e2efc09eSTirumala Marri			 * We are de-swizzling here because the numbers are actually for
307e2efc09eSTirumala Marri			 * port of the root complex virtual P2P bridge. But I want
308e2efc09eSTirumala Marri			 * to avoid putting a node for it in the tree, so the numbers
309e2efc09eSTirumala Marri			 * below are basically de-swizzled numbers.
310e2efc09eSTirumala Marri			 * The real slot is on idsel 0, so the swizzling is 1:1
311e2efc09eSTirumala Marri			 */
312e2efc09eSTirumala Marri			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
313e2efc09eSTirumala Marri			interrupt-map = <
314e2efc09eSTirumala Marri				0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
315e2efc09eSTirumala Marri				0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
316e2efc09eSTirumala Marri				0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
317e2efc09eSTirumala Marri				0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
318e2efc09eSTirumala Marri		};
319e2efc09eSTirumala Marri
32086bc917dSMichael Ellerman		PCIE2: pcie@d40000000 {
321e2efc09eSTirumala Marri			device_type = "pci";
322e2efc09eSTirumala Marri			#interrupt-cells = <1>;
323e2efc09eSTirumala Marri			#size-cells = <2>;
324e2efc09eSTirumala Marri			#address-cells = <3>;
325e2efc09eSTirumala Marri			compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
326e2efc09eSTirumala Marri			primary;
327e2efc09eSTirumala Marri			port = <0x2>; /* port number */
328e2efc09eSTirumala Marri			reg = <0x0000000d 0x40000000 0x20000000	/* Config space access */
329e2efc09eSTirumala Marri			       0x0000000c 0x10002000 0x00001000>;	/* Registers */
330e2efc09eSTirumala Marri			dcr-reg = <0x140 0x020>;
331e2efc09eSTirumala Marri			sdr-base = <0x370>;
332e2efc09eSTirumala Marri
333e2efc09eSTirumala Marri			/* Outbound ranges, one memory and one IO,
334e2efc09eSTirumala Marri			 * later cannot be changed
335e2efc09eSTirumala Marri			 */
336e2efc09eSTirumala Marri			ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
337e2efc09eSTirumala Marri				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
338e2efc09eSTirumala Marri
339e2efc09eSTirumala Marri			/* Inbound 2GB range starting at 0 */
340e2efc09eSTirumala Marri			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
341e2efc09eSTirumala Marri
342e2efc09eSTirumala Marri			/* This drives busses 10 to 0x1f */
343e2efc09eSTirumala Marri			bus-range = <0x30 0x3f>;
344e2efc09eSTirumala Marri
345e2efc09eSTirumala Marri			/* Legacy interrupts (note the weird polarity, the bridge seems
346e2efc09eSTirumala Marri			 * to invert PCIe legacy interrupts).
347e2efc09eSTirumala Marri			 * We are de-swizzling here because the numbers are actually for
348e2efc09eSTirumala Marri			 * port of the root complex virtual P2P bridge. But I want
349e2efc09eSTirumala Marri			 * to avoid putting a node for it in the tree, so the numbers
350e2efc09eSTirumala Marri			 * below are basically de-swizzled numbers.
351e2efc09eSTirumala Marri			 * The real slot is on idsel 0, so the swizzling is 1:1
352e2efc09eSTirumala Marri			 */
353e2efc09eSTirumala Marri			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
354e2efc09eSTirumala Marri			interrupt-map = <
355e2efc09eSTirumala Marri				0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
356e2efc09eSTirumala Marri				0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
357e2efc09eSTirumala Marri				0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
358e2efc09eSTirumala Marri				0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
3596c712090SMadhulika Madishetty		};
3606c712090SMadhulika Madishetty
3613fb79338SRupjyoti Sarmah	};
3623fb79338SRupjyoti Sarmah
3633fb79338SRupjyoti Sarmah
3646c712090SMadhulika Madishetty	chosen {
36578e5dfeaSRob Herring		stdout-path = "/plb/opb/serial@ef600200";
3666c712090SMadhulika Madishetty	};
3676c712090SMadhulika Madishetty
3686c712090SMadhulika Madishetty};
369