110b9dc6fSWolfram Sang/* 210b9dc6fSWolfram Sang * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source 310b9dc6fSWolfram Sang * 410b9dc6fSWolfram Sang * Copyright (C) 2006-2009 Pengutronix 510b9dc6fSWolfram Sang * Sascha Hauer <s.hauer@pengutronix.de> 610b9dc6fSWolfram Sang * Juergen Beisert <j.beisert@pengutronix.de> 710b9dc6fSWolfram Sang * Wolfram Sang <w.sang@pengutronix.de> 810b9dc6fSWolfram Sang * 910b9dc6fSWolfram Sang * This program is free software; you can redistribute it and/or modify it 1010b9dc6fSWolfram Sang * under the terms of the GNU General Public License as published by the 1110b9dc6fSWolfram Sang * Free Software Foundation; either version 2 of the License, or (at your 1210b9dc6fSWolfram Sang * option) any later version. 1310b9dc6fSWolfram Sang */ 1410b9dc6fSWolfram Sang 15c8bf6b52SJohn Bonesio/include/ "mpc5200b.dtsi" 1610b9dc6fSWolfram Sang 1710b9dc6fSWolfram Sang/ { 1810b9dc6fSWolfram Sang model = "phytec,pcm032"; 1910b9dc6fSWolfram Sang compatible = "phytec,pcm032"; 2010b9dc6fSWolfram Sang 2110b9dc6fSWolfram Sang memory { 2210b9dc6fSWolfram Sang reg = <0x00000000 0x08000000>; // 128MB 2310b9dc6fSWolfram Sang }; 2410b9dc6fSWolfram Sang 2510b9dc6fSWolfram Sang soc5200@f0000000 { 2610b9dc6fSWolfram Sang timer@600 { // General Purpose Timer 2710b9dc6fSWolfram Sang fsl,has-wdt; 2810b9dc6fSWolfram Sang }; 2910b9dc6fSWolfram Sang 3010b9dc6fSWolfram Sang gpt2: timer@620 { // General Purpose Timer in GPIO mode 3110b9dc6fSWolfram Sang gpio-controller; 3210b9dc6fSWolfram Sang #gpio-cells = <2>; 3310b9dc6fSWolfram Sang }; 3410b9dc6fSWolfram Sang 3510b9dc6fSWolfram Sang gpt3: timer@630 { // General Purpose Timer in GPIO mode 3610b9dc6fSWolfram Sang gpio-controller; 3710b9dc6fSWolfram Sang #gpio-cells = <2>; 3810b9dc6fSWolfram Sang }; 3910b9dc6fSWolfram Sang 4010b9dc6fSWolfram Sang gpt4: timer@640 { // General Purpose Timer in GPIO mode 4110b9dc6fSWolfram Sang gpio-controller; 4210b9dc6fSWolfram Sang #gpio-cells = <2>; 4310b9dc6fSWolfram Sang }; 4410b9dc6fSWolfram Sang 4510b9dc6fSWolfram Sang gpt5: timer@650 { // General Purpose Timer in GPIO mode 4610b9dc6fSWolfram Sang gpio-controller; 4710b9dc6fSWolfram Sang #gpio-cells = <2>; 4810b9dc6fSWolfram Sang }; 4910b9dc6fSWolfram Sang 5010b9dc6fSWolfram Sang gpt6: timer@660 { // General Purpose Timer in GPIO mode 5110b9dc6fSWolfram Sang compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 5210b9dc6fSWolfram Sang reg = <0x660 0x10>; 5310b9dc6fSWolfram Sang interrupts = <1 15 0>; 5410b9dc6fSWolfram Sang gpio-controller; 5510b9dc6fSWolfram Sang #gpio-cells = <2>; 5610b9dc6fSWolfram Sang }; 5710b9dc6fSWolfram Sang 5810b9dc6fSWolfram Sang gpt7: timer@670 { // General Purpose Timer in GPIO mode 5910b9dc6fSWolfram Sang gpio-controller; 6010b9dc6fSWolfram Sang #gpio-cells = <2>; 6110b9dc6fSWolfram Sang }; 6210b9dc6fSWolfram Sang 63abf1e27fSJohn Bonesio psc@2000 { /* PSC1 is ac97 */ 6410b9dc6fSWolfram Sang compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 6510b9dc6fSWolfram Sang cell-index = <0>; 6610b9dc6fSWolfram Sang }; 6710b9dc6fSWolfram Sang 6810b9dc6fSWolfram Sang /* PSC2 port is used by CAN1/2 */ 69c8bf6b52SJohn Bonesio psc@2200 { 70c8bf6b52SJohn Bonesio status = "disabled"; 71c8bf6b52SJohn Bonesio }; 7210b9dc6fSWolfram Sang 73abf1e27fSJohn Bonesio psc@2400 { /* PSC3 in UART mode */ 7410b9dc6fSWolfram Sang compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 7510b9dc6fSWolfram Sang }; 7610b9dc6fSWolfram Sang 7710b9dc6fSWolfram Sang /* PSC4 is ??? */ 78c8bf6b52SJohn Bonesio psc@2600 { 79c8bf6b52SJohn Bonesio status = "disabled"; 80c8bf6b52SJohn Bonesio }; 8110b9dc6fSWolfram Sang 8210b9dc6fSWolfram Sang /* PSC5 is ??? */ 83c8bf6b52SJohn Bonesio psc@2800 { 84c8bf6b52SJohn Bonesio status = "disabled"; 85c8bf6b52SJohn Bonesio }; 8610b9dc6fSWolfram Sang 87abf1e27fSJohn Bonesio psc@2c00 { /* PSC6 in UART mode */ 8810b9dc6fSWolfram Sang compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 8910b9dc6fSWolfram Sang }; 9010b9dc6fSWolfram Sang 9110b9dc6fSWolfram Sang ethernet@3000 { 9210b9dc6fSWolfram Sang phy-handle = <&phy0>; 9310b9dc6fSWolfram Sang }; 9410b9dc6fSWolfram Sang 9510b9dc6fSWolfram Sang mdio@3000 { 9610b9dc6fSWolfram Sang phy0: ethernet-phy@0 { 9710b9dc6fSWolfram Sang reg = <0>; 9810b9dc6fSWolfram Sang }; 9910b9dc6fSWolfram Sang }; 10010b9dc6fSWolfram Sang 10110b9dc6fSWolfram Sang i2c@3d40 { 10210b9dc6fSWolfram Sang rtc@51 { 10310b9dc6fSWolfram Sang compatible = "nxp,pcf8563"; 10410b9dc6fSWolfram Sang reg = <0x51>; 10510b9dc6fSWolfram Sang }; 10610b9dc6fSWolfram Sang eeprom@52 { 10755271024SWolfram Sang compatible = "catalyst,24c32"; 10810b9dc6fSWolfram Sang reg = <0x52>; 10955271024SWolfram Sang pagesize = <32>; 11010b9dc6fSWolfram Sang }; 11110b9dc6fSWolfram Sang }; 11210b9dc6fSWolfram Sang }; 11310b9dc6fSWolfram Sang 11410b9dc6fSWolfram Sang pci@f0000d00 { 11510b9dc6fSWolfram Sang interrupt-map-mask = <0xf800 0 0 7>; 11610b9dc6fSWolfram Sang interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 11710b9dc6fSWolfram Sang 0xc000 0 0 2 &mpc5200_pic 1 1 3 11810b9dc6fSWolfram Sang 0xc000 0 0 3 &mpc5200_pic 1 2 3 11910b9dc6fSWolfram Sang 0xc000 0 0 4 &mpc5200_pic 1 3 3 12010b9dc6fSWolfram Sang 12110b9dc6fSWolfram Sang 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot 12210b9dc6fSWolfram Sang 0xc800 0 0 2 &mpc5200_pic 1 2 3 12310b9dc6fSWolfram Sang 0xc800 0 0 3 &mpc5200_pic 1 3 3 12410b9dc6fSWolfram Sang 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 12510b9dc6fSWolfram Sang ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 12610b9dc6fSWolfram Sang 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 12710b9dc6fSWolfram Sang 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 12810b9dc6fSWolfram Sang }; 12910b9dc6fSWolfram Sang 13010b9dc6fSWolfram Sang localbus { 13110b9dc6fSWolfram Sang ranges = <0 0 0xfe000000 0x02000000 13210b9dc6fSWolfram Sang 1 0 0xfc000000 0x02000000 13310b9dc6fSWolfram Sang 2 0 0xfbe00000 0x00200000 13410b9dc6fSWolfram Sang 3 0 0xf9e00000 0x02000000 13510b9dc6fSWolfram Sang 4 0 0xf7e00000 0x02000000 13610b9dc6fSWolfram Sang 5 0 0xe6000000 0x02000000 13710b9dc6fSWolfram Sang 6 0 0xe8000000 0x02000000 13810b9dc6fSWolfram Sang 7 0 0xea000000 0x02000000>; 13910b9dc6fSWolfram Sang 14010b9dc6fSWolfram Sang flash@0,0 { 14110b9dc6fSWolfram Sang compatible = "cfi-flash"; 14210b9dc6fSWolfram Sang reg = <0 0 0x02000000>; 14310b9dc6fSWolfram Sang bank-width = <4>; 14410b9dc6fSWolfram Sang #size-cells = <1>; 14510b9dc6fSWolfram Sang #address-cells = <1>; 14610b9dc6fSWolfram Sang 14710b9dc6fSWolfram Sang partition@0 { 14810b9dc6fSWolfram Sang label = "ubootl"; 14910b9dc6fSWolfram Sang reg = <0x00000000 0x00040000>; 15010b9dc6fSWolfram Sang }; 15110b9dc6fSWolfram Sang partition@40000 { 15210b9dc6fSWolfram Sang label = "kernel"; 15310b9dc6fSWolfram Sang reg = <0x00040000 0x001c0000>; 15410b9dc6fSWolfram Sang }; 15510b9dc6fSWolfram Sang partition@200000 { 15610b9dc6fSWolfram Sang label = "jffs2"; 15710b9dc6fSWolfram Sang reg = <0x00200000 0x01d00000>; 15810b9dc6fSWolfram Sang }; 15910b9dc6fSWolfram Sang partition@1f00000 { 16010b9dc6fSWolfram Sang label = "uboot"; 16110b9dc6fSWolfram Sang reg = <0x01f00000 0x00040000>; 16210b9dc6fSWolfram Sang }; 16310b9dc6fSWolfram Sang partition@1f40000 { 16410b9dc6fSWolfram Sang label = "env"; 16510b9dc6fSWolfram Sang reg = <0x01f40000 0x00040000>; 16610b9dc6fSWolfram Sang }; 16710b9dc6fSWolfram Sang partition@1f80000 { 16810b9dc6fSWolfram Sang label = "oftree"; 16910b9dc6fSWolfram Sang reg = <0x01f80000 0x00040000>; 17010b9dc6fSWolfram Sang }; 17110b9dc6fSWolfram Sang partition@1fc0000 { 17210b9dc6fSWolfram Sang label = "space"; 17310b9dc6fSWolfram Sang reg = <0x01fc0000 0x00040000>; 17410b9dc6fSWolfram Sang }; 17510b9dc6fSWolfram Sang }; 17610b9dc6fSWolfram Sang 17710b9dc6fSWolfram Sang sram@2,0 { 17810b9dc6fSWolfram Sang compatible = "mtd-ram"; 17910b9dc6fSWolfram Sang reg = <2 0 0x00200000>; 18010b9dc6fSWolfram Sang bank-width = <2>; 18110b9dc6fSWolfram Sang }; 18210b9dc6fSWolfram Sang 18310b9dc6fSWolfram Sang /* 18410b9dc6fSWolfram Sang * example snippets for FPGA 18510b9dc6fSWolfram Sang * 18610b9dc6fSWolfram Sang * fpga@3,0 { 18710b9dc6fSWolfram Sang * compatible = "fpga_driver"; 18810b9dc6fSWolfram Sang * reg = <3 0 0x02000000>; 18910b9dc6fSWolfram Sang * bank-width = <4>; 19010b9dc6fSWolfram Sang * }; 19110b9dc6fSWolfram Sang * 19210b9dc6fSWolfram Sang * fpga@4,0 { 19310b9dc6fSWolfram Sang * compatible = "fpga_driver"; 19410b9dc6fSWolfram Sang * reg = <4 0 0x02000000>; 19510b9dc6fSWolfram Sang * bank-width = <4>; 19610b9dc6fSWolfram Sang * }; 19710b9dc6fSWolfram Sang */ 19810b9dc6fSWolfram Sang 19910b9dc6fSWolfram Sang /* 20010b9dc6fSWolfram Sang * example snippets for free chipselects 20110b9dc6fSWolfram Sang * 20210b9dc6fSWolfram Sang * device@5,0 { 20310b9dc6fSWolfram Sang * compatible = "custom_driver"; 20410b9dc6fSWolfram Sang * reg = <5 0 0x02000000>; 20510b9dc6fSWolfram Sang * }; 20610b9dc6fSWolfram Sang * 20710b9dc6fSWolfram Sang * device@6,0 { 20810b9dc6fSWolfram Sang * compatible = "custom_driver"; 20910b9dc6fSWolfram Sang * reg = <6 0 0x02000000>; 21010b9dc6fSWolfram Sang * }; 21110b9dc6fSWolfram Sang * 21210b9dc6fSWolfram Sang * device@7,0 { 21310b9dc6fSWolfram Sang * compatible = "custom_driver"; 21410b9dc6fSWolfram Sang * reg = <7 0 0x02000000>; 21510b9dc6fSWolfram Sang * }; 21610b9dc6fSWolfram Sang */ 21710b9dc6fSWolfram Sang }; 21810b9dc6fSWolfram Sang}; 219