1be201981SStephen Chivers/*
2be201981SStephen Chivers * Device Tree Source for Motorola/Emerson MVME5100.
3be201981SStephen Chivers *
4be201981SStephen Chivers * Copyright 2013 CSC Australia Pty. Ltd.
5be201981SStephen Chivers *
6be201981SStephen Chivers * This file is licensed under the terms of the GNU General Public
7be201981SStephen Chivers * License version 2.  This program is licensed "as is" without
8be201981SStephen Chivers * any warranty of any kind, whether express or implied.
9be201981SStephen Chivers */
10be201981SStephen Chivers
11be201981SStephen Chivers/dts-v1/;
12be201981SStephen Chivers
13be201981SStephen Chivers/ {
14be201981SStephen Chivers	model = "MVME5100";
15be201981SStephen Chivers	compatible = "MVME5100";
16be201981SStephen Chivers	#address-cells = <1>;
17be201981SStephen Chivers	#size-cells = <1>;
18be201981SStephen Chivers
19be201981SStephen Chivers	aliases {
20be201981SStephen Chivers		serial0 = &serial0;
21be201981SStephen Chivers		pci0 = &pci0;
22be201981SStephen Chivers	};
23be201981SStephen Chivers
24be201981SStephen Chivers	cpus {
25be201981SStephen Chivers		#address-cells = <1>;
26be201981SStephen Chivers		#size-cells = <0>;
27be201981SStephen Chivers
28be201981SStephen Chivers		PowerPC,7410 {
29be201981SStephen Chivers			device_type = "cpu";
30be201981SStephen Chivers			reg = <0x0>;
31be201981SStephen Chivers			/* Following required by dtc but not used */
32be201981SStephen Chivers			d-cache-line-size = <32>;
33be201981SStephen Chivers			i-cache-line-size = <32>;
34be201981SStephen Chivers			i-cache-size = <32768>;
35be201981SStephen Chivers			d-cache-size = <32768>;
36be201981SStephen Chivers			timebase-frequency = <25000000>;
37be201981SStephen Chivers			clock-frequency = <500000000>;
38be201981SStephen Chivers			bus-frequency = <100000000>;
39be201981SStephen Chivers		};
40be201981SStephen Chivers	};
41be201981SStephen Chivers
42be201981SStephen Chivers	memory {
43be201981SStephen Chivers		device_type = "memory";
44be201981SStephen Chivers		reg = <0x0 0x20000000>;
45be201981SStephen Chivers	};
46be201981SStephen Chivers
47be201981SStephen Chivers	hawk@fef80000 {
48be201981SStephen Chivers		#address-cells = <1>;
49be201981SStephen Chivers		#size-cells = <1>;
50be201981SStephen Chivers		compatible = "hawk-bridge", "simple-bus";
51be201981SStephen Chivers		ranges = <0x0 0xfef80000 0x10000>;
52be201981SStephen Chivers		reg = <0xfef80000 0x10000>;
53be201981SStephen Chivers
54be201981SStephen Chivers		serial0: serial@8000 {
55be201981SStephen Chivers			device_type = "serial";
56be201981SStephen Chivers			compatible = "ns16550";
57be201981SStephen Chivers			reg = <0x8000 0x80>;
58be201981SStephen Chivers			reg-shift = <4>;
59be201981SStephen Chivers			clock-frequency = <1843200>;
60be201981SStephen Chivers			current-speed = <9600>;
61be201981SStephen Chivers			interrupts = <1 1>; // IRQ1 Level Active Low.
62be201981SStephen Chivers			interrupt-parent = <&mpic>;
63be201981SStephen Chivers		};
64be201981SStephen Chivers
65be201981SStephen Chivers		serial1: serial@8200 {
66be201981SStephen Chivers			device_type = "serial";
67be201981SStephen Chivers			compatible = "ns16550";
68be201981SStephen Chivers			reg = <0x8200 0x80>;
69be201981SStephen Chivers			reg-shift = <4>;
70be201981SStephen Chivers			clock-frequency = <1843200>;
71be201981SStephen Chivers			current-speed = <9600>;
72be201981SStephen Chivers			interrupts = <1 1>; // IRQ1 Level Active Low.
73be201981SStephen Chivers			interrupt-parent = <&mpic>;
74be201981SStephen Chivers		};
75be201981SStephen Chivers
76be201981SStephen Chivers		mpic: interrupt-controller@f3f80000 {
77be201981SStephen Chivers			#interrupt-cells = <2>;
78be201981SStephen Chivers			#address-cells = <0>;
79be201981SStephen Chivers			device_type = "open-pic";
80be201981SStephen Chivers			compatible = "chrp,open-pic";
81be201981SStephen Chivers			interrupt-controller;
82be201981SStephen Chivers			reg = <0xf3f80000 0x40000>;
83be201981SStephen Chivers		};
84be201981SStephen Chivers	};
85be201981SStephen Chivers
86be201981SStephen Chivers	pci0: pci@feff0000 {
87be201981SStephen Chivers		#address-cells = <3>;
88be201981SStephen Chivers		#size-cells = <2>;
89be201981SStephen Chivers		#interrupt-cells = <1>;
90be201981SStephen Chivers		device_type = "pci";
91be201981SStephen Chivers		compatible = "hawk-pci";
92be201981SStephen Chivers		reg = <0xfec00000 0x400000>;
93be201981SStephen Chivers		8259-interrupt-acknowledge = <0xfeff0030>;
94be201981SStephen Chivers		ranges = <0x1000000 0x0        0x0 0xfe000000 0x0 0x800000
95be201981SStephen Chivers			  0x2000000 0x0 0x80000000 0x80000000 0x0 0x74000000>;
96be201981SStephen Chivers		bus-range = <0 255>;
97be201981SStephen Chivers		clock-frequency = <33333333>;
98be201981SStephen Chivers		interrupt-parent = <&mpic>;
99be201981SStephen Chivers		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
100be201981SStephen Chivers		interrupt-map = <
101be201981SStephen Chivers
102be201981SStephen Chivers			/*
103be201981SStephen Chivers			 * This definition (IDSEL 11) duplicates the
104be201981SStephen Chivers			 * interrupts definition in the i8259
105be201981SStephen Chivers			 * interrupt controller below.
106be201981SStephen Chivers			 *
107be201981SStephen Chivers			 * Do not change the interrupt sense/polarity from
108be201981SStephen Chivers			 * 0x2 to anything else, doing so will cause endless
109be201981SStephen Chivers			 * "spurious" i8259 interrupts to be fielded.
110be201981SStephen Chivers			 */
111be201981SStephen Chivers			// IDSEL 11 - iPMC712 PCI/ISA Bridge
112be201981SStephen Chivers			0x5800 0x0 0x0 0x1 &mpic 0x0 0x2
113be201981SStephen Chivers			0x5800 0x0 0x0 0x2 &mpic 0x0 0x2
114be201981SStephen Chivers			0x5800 0x0 0x0 0x3 &mpic 0x0 0x2
115be201981SStephen Chivers			0x5800 0x0 0x0 0x4 &mpic 0x0 0x2
116be201981SStephen Chivers
117be201981SStephen Chivers			/* IDSEL 12 - Not Used */
118be201981SStephen Chivers
119be201981SStephen Chivers			/* IDSEL 13 - Universe VME Bridge */
120be201981SStephen Chivers			0x6800 0x0 0x0 0x1 &mpic 0x5 0x1
121be201981SStephen Chivers			0x6800 0x0 0x0 0x2 &mpic 0x6 0x1
122be201981SStephen Chivers			0x6800 0x0 0x0 0x3 &mpic 0x7 0x1
123be201981SStephen Chivers			0x6800 0x0 0x0 0x4 &mpic 0x8 0x1
124be201981SStephen Chivers
125be201981SStephen Chivers			/* IDSEL 14 - ENET 1 */
126be201981SStephen Chivers			0x7000 0x0 0x0 0x1 &mpic 0x2 0x1
127be201981SStephen Chivers
128be201981SStephen Chivers			/* IDSEL 15 - Not Used */
129be201981SStephen Chivers
130be201981SStephen Chivers			/* IDSEL 16 - PMC Slot 1 */
131be201981SStephen Chivers			0x8000 0x0 0x0 0x1 &mpic 0x9 0x1
132be201981SStephen Chivers			0x8000 0x0 0x0 0x2 &mpic 0xa 0x1
133be201981SStephen Chivers			0x8000 0x0 0x0 0x3 &mpic 0xb 0x1
134be201981SStephen Chivers			0x8000 0x0 0x0 0x4 &mpic 0xc 0x1
135be201981SStephen Chivers
136be201981SStephen Chivers			/* IDSEL 17 - PMC Slot 2 */
137be201981SStephen Chivers			0x8800 0x0 0x0 0x1 &mpic 0xc 0x1
138be201981SStephen Chivers			0x8800 0x0 0x0 0x2 &mpic 0x9 0x1
139be201981SStephen Chivers			0x8800 0x0 0x0 0x3 &mpic 0xa 0x1
140be201981SStephen Chivers			0x8800 0x0 0x0 0x4 &mpic 0xb 0x1
141be201981SStephen Chivers
142be201981SStephen Chivers			/* IDSEL 18 - Not Used */
143be201981SStephen Chivers
144be201981SStephen Chivers			/* IDSEL 19 - ENET 2 */
145be201981SStephen Chivers			0x9800 0x0 0x0 0x1 &mpic 0xd 0x1
146be201981SStephen Chivers
147be201981SStephen Chivers			/* IDSEL 20 - PMCSPAN (PCI-X) */
148be201981SStephen Chivers			0xa000 0x0 0x0 0x1 &mpic 0x9 0x1
149be201981SStephen Chivers			0xa000 0x0 0x0 0x2 &mpic 0xa 0x1
150be201981SStephen Chivers			0xa000 0x0 0x0 0x3 &mpic 0xb 0x1
151be201981SStephen Chivers			0xa000 0x0 0x0 0x4 &mpic 0xc 0x1
152be201981SStephen Chivers
153be201981SStephen Chivers		>;
154be201981SStephen Chivers
155be201981SStephen Chivers		isa {
156be201981SStephen Chivers			#address-cells = <2>;
157be201981SStephen Chivers			#size-cells = <1>;
158be201981SStephen Chivers			#interrupt-cells = <2>;
159be201981SStephen Chivers			device_type = "isa";
160be201981SStephen Chivers			compatible = "isa";
161be201981SStephen Chivers			ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>;
162be201981SStephen Chivers			interrupt-parent = <&i8259>;
163be201981SStephen Chivers
164be201981SStephen Chivers			i8259: interrupt-controller@20 {
165be201981SStephen Chivers				#interrupt-cells = <2>;
166be201981SStephen Chivers				#address-cells = <0>;
167be201981SStephen Chivers				interrupts = <0 2>;
168be201981SStephen Chivers				device_type = "interrupt-controller";
169be201981SStephen Chivers				compatible = "chrp,iic";
170be201981SStephen Chivers				interrupt-controller;
171be201981SStephen Chivers				reg = <1 0x00000020 0x00000002
172be201981SStephen Chivers                                       1 0x000000a0 0x00000002
173be201981SStephen Chivers                                       1 0x000004d0 0x00000002>;
174be201981SStephen Chivers				interrupt-parent = <&mpic>;
175be201981SStephen Chivers			};
176be201981SStephen Chivers
177be201981SStephen Chivers		};
178be201981SStephen Chivers
179be201981SStephen Chivers	};
180be201981SStephen Chivers
181be201981SStephen Chivers	chosen {
18278e5dfeaSRob Herring		stdout-path = &serial0;
183be201981SStephen Chivers        };
184be201981SStephen Chivers
185be201981SStephen Chivers};
186