1/*
2 * MPC8379E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	compatible = "fsl,mpc8379rdb";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet0;
21		ethernet1 = &enet1;
22		serial0 = &serial0;
23		serial1 = &serial1;
24		pci0 = &pci0;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		PowerPC,8379@0 {
32			device_type = "cpu";
33			reg = <0x0>;
34			d-cache-line-size = <32>;
35			i-cache-line-size = <32>;
36			d-cache-size = <32768>;
37			i-cache-size = <32768>;
38			timebase-frequency = <0>;
39			bus-frequency = <0>;
40			clock-frequency = <0>;
41		};
42	};
43
44	memory {
45		device_type = "memory";
46		reg = <0x00000000 0x10000000>;	// 256MB at 0
47	};
48
49	localbus@e0005000 {
50		#address-cells = <2>;
51		#size-cells = <1>;
52		compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
53		reg = <0xe0005000 0x1000>;
54		interrupts = <77 0x8>;
55		interrupt-parent = <&ipic>;
56
57		// CS0 and CS1 are swapped when
58		// booting from nand, but the
59		// addresses are the same.
60		ranges = <0x0 0x0 0xfe000000 0x00800000
61		          0x1 0x0 0xe0600000 0x00008000
62		          0x2 0x0 0xf0000000 0x00020000
63		          0x3 0x0 0xfa000000 0x00008000>;
64
65		flash@0,0 {
66			#address-cells = <1>;
67			#size-cells = <1>;
68			compatible = "cfi-flash";
69			reg = <0x0 0x0 0x800000>;
70			bank-width = <2>;
71			device-width = <1>;
72		};
73
74		nand@1,0 {
75			#address-cells = <1>;
76			#size-cells = <1>;
77			compatible = "fsl,mpc8379-fcm-nand",
78			             "fsl,elbc-fcm-nand";
79			reg = <0x1 0x0 0x8000>;
80
81			u-boot@0 {
82				reg = <0x0 0x100000>;
83				read-only;
84			};
85
86			kernel@100000 {
87				reg = <0x100000 0x300000>;
88			};
89			fs@400000 {
90				reg = <0x400000 0x1c00000>;
91			};
92		};
93	};
94
95	immr@e0000000 {
96		#address-cells = <1>;
97		#size-cells = <1>;
98		device_type = "soc";
99		compatible = "simple-bus";
100		ranges = <0x0 0xe0000000 0x00100000>;
101		reg = <0xe0000000 0x00000200>;
102		bus-frequency = <0>;
103
104		wdt@200 {
105			device_type = "watchdog";
106			compatible = "mpc83xx_wdt";
107			reg = <0x200 0x100>;
108		};
109
110		i2c@3000 {
111			#address-cells = <1>;
112			#size-cells = <0>;
113			cell-index = <0>;
114			compatible = "fsl-i2c";
115			reg = <0x3000 0x100>;
116			interrupts = <14 0x8>;
117			interrupt-parent = <&ipic>;
118			dfsrr;
119
120			at24@50 {
121				compatible = "at24,24c256";
122				reg = <0x50>;
123			};
124
125			rtc@68 {
126				compatible = "dallas,ds1339";
127				reg = <0x68>;
128			};
129
130			mcu_pio: mcu@a {
131				#gpio-cells = <2>;
132				compatible = "fsl,mc9s08qg8-mpc8379erdb",
133					     "fsl,mcu-mpc8349emitx";
134				reg = <0x0a>;
135				gpio-controller;
136			};
137		};
138
139		i2c@3100 {
140			#address-cells = <1>;
141			#size-cells = <0>;
142			cell-index = <1>;
143			compatible = "fsl-i2c";
144			reg = <0x3100 0x100>;
145			interrupts = <15 0x8>;
146			interrupt-parent = <&ipic>;
147			dfsrr;
148		};
149
150		spi@7000 {
151			cell-index = <0>;
152			compatible = "fsl,spi";
153			reg = <0x7000 0x1000>;
154			interrupts = <16 0x8>;
155			interrupt-parent = <&ipic>;
156			mode = "cpu";
157		};
158
159		dma@82a8 {
160			#address-cells = <1>;
161			#size-cells = <1>;
162			compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
163			reg = <0x82a8 4>;
164			ranges = <0 0x8100 0x1a8>;
165			interrupt-parent = <&ipic>;
166			interrupts = <71 8>;
167			cell-index = <0>;
168			dma-channel@0 {
169				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
170				reg = <0 0x80>;
171				cell-index = <0>;
172				interrupt-parent = <&ipic>;
173				interrupts = <71 8>;
174			};
175			dma-channel@80 {
176				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
177				reg = <0x80 0x80>;
178				cell-index = <1>;
179				interrupt-parent = <&ipic>;
180				interrupts = <71 8>;
181			};
182			dma-channel@100 {
183				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
184				reg = <0x100 0x80>;
185				cell-index = <2>;
186				interrupt-parent = <&ipic>;
187				interrupts = <71 8>;
188			};
189			dma-channel@180 {
190				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
191				reg = <0x180 0x28>;
192				cell-index = <3>;
193				interrupt-parent = <&ipic>;
194				interrupts = <71 8>;
195			};
196		};
197
198		usb@23000 {
199			compatible = "fsl-usb2-dr";
200			reg = <0x23000 0x1000>;
201			#address-cells = <1>;
202			#size-cells = <0>;
203			interrupt-parent = <&ipic>;
204			interrupts = <38 0x8>;
205			phy_type = "ulpi";
206		};
207
208		mdio@24520 {
209			#address-cells = <1>;
210			#size-cells = <0>;
211			compatible = "fsl,gianfar-mdio";
212			reg = <0x24520 0x20>;
213			phy2: ethernet-phy@2 {
214				interrupt-parent = <&ipic>;
215				interrupts = <17 0x8>;
216				reg = <0x2>;
217				device_type = "ethernet-phy";
218			};
219			tbi0: tbi-phy@11 {
220				reg = <0x11>;
221				device_type = "tbi-phy";
222			};
223		};
224
225		mdio@25520 {
226			#address-cells = <1>;
227			#size-cells = <0>;
228			compatible = "fsl,gianfar-tbi";
229			reg = <0x25520 0x20>;
230
231			tbi1: tbi-phy@11 {
232				reg = <0x11>;
233				device_type = "tbi-phy";
234			};
235		};
236
237		enet0: ethernet@24000 {
238			cell-index = <0>;
239			device_type = "network";
240			model = "eTSEC";
241			compatible = "gianfar";
242			reg = <0x24000 0x1000>;
243			local-mac-address = [ 00 00 00 00 00 00 ];
244			interrupts = <32 0x8 33 0x8 34 0x8>;
245			phy-connection-type = "mii";
246			interrupt-parent = <&ipic>;
247			tbi-handle = <&tbi0>;
248			phy-handle = <&phy2>;
249		};
250
251		enet1: ethernet@25000 {
252			cell-index = <1>;
253			device_type = "network";
254			model = "eTSEC";
255			compatible = "gianfar";
256			reg = <0x25000 0x1000>;
257			local-mac-address = [ 00 00 00 00 00 00 ];
258			interrupts = <35 0x8 36 0x8 37 0x8>;
259			phy-connection-type = "mii";
260			interrupt-parent = <&ipic>;
261			fixed-link = <1 1 1000 0 0>;
262			tbi-handle = <&tbi1>;
263		};
264
265		serial0: serial@4500 {
266			cell-index = <0>;
267			device_type = "serial";
268			compatible = "ns16550";
269			reg = <0x4500 0x100>;
270			clock-frequency = <0>;
271			interrupts = <9 0x8>;
272			interrupt-parent = <&ipic>;
273		};
274
275		serial1: serial@4600 {
276			cell-index = <1>;
277			device_type = "serial";
278			compatible = "ns16550";
279			reg = <0x4600 0x100>;
280			clock-frequency = <0>;
281			interrupts = <10 0x8>;
282			interrupt-parent = <&ipic>;
283		};
284
285		crypto@30000 {
286			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
287				     "fsl,sec2.1", "fsl,sec2.0";
288			reg = <0x30000 0x10000>;
289			interrupts = <11 0x8>;
290			interrupt-parent = <&ipic>;
291			fsl,num-channels = <4>;
292			fsl,channel-fifo-len = <24>;
293			fsl,exec-units-mask = <0x9fe>;
294			fsl,descriptor-types-mask = <0x3ab0ebf>;
295		};
296
297		sata@18000 {
298			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
299			reg = <0x18000 0x1000>;
300			interrupts = <44 0x8>;
301			interrupt-parent = <&ipic>;
302		};
303
304		sata@19000 {
305			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
306			reg = <0x19000 0x1000>;
307			interrupts = <45 0x8>;
308			interrupt-parent = <&ipic>;
309		};
310
311		sata@1a000 {
312			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
313			reg = <0x1a000 0x1000>;
314			interrupts = <46 0x8>;
315			interrupt-parent = <&ipic>;
316		};
317
318		sata@1b000 {
319			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
320			reg = <0x1b000 0x1000>;
321			interrupts = <47 0x8>;
322			interrupt-parent = <&ipic>;
323		};
324
325		/* IPIC
326		 * interrupts cell = <intr #, sense>
327		 * sense values match linux IORESOURCE_IRQ_* defines:
328		 * sense == 8: Level, low assertion
329		 * sense == 2: Edge, high-to-low change
330		 */
331		ipic: interrupt-controller@700 {
332			compatible = "fsl,ipic";
333			interrupt-controller;
334			#address-cells = <0>;
335			#interrupt-cells = <2>;
336			reg = <0x700 0x100>;
337		};
338	};
339
340	pci0: pci@e0008500 {
341		interrupt-map-mask = <0xf800 0 0 7>;
342		interrupt-map = <
343				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
344
345				/* IDSEL AD14 IRQ6 inta */
346				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
347
348				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
349				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
350				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
351				 0x7800 0x0 0x0 0x4 &ipic 23 0x8
352
353				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
354				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
355				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
356				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
357		interrupt-parent = <&ipic>;
358		interrupts = <66 0x8>;
359		bus-range = <0x0 0x0>;
360		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
361		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
362		          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
363		clock-frequency = <66666666>;
364		#interrupt-cells = <1>;
365		#size-cells = <2>;
366		#address-cells = <3>;
367		reg = <0xe0008500 0x100		/* internal registers */
368		       0xe0008300 0x8>;		/* config space access registers */
369		compatible = "fsl,mpc8349-pci";
370		device_type = "pci";
371	};
372};
373