1/* 2 * MPC8379E RDB Device Tree Source 3 * 4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 compatible = "fsl,mpc8379rdb"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 ethernet0 = &enet0; 21 ethernet1 = &enet1; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8379@0 { 32 device_type = "cpu"; 33 reg = <0x0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <32768>; 37 i-cache-size = <32768>; 38 timebase-frequency = <0>; 39 bus-frequency = <0>; 40 clock-frequency = <0>; 41 }; 42 }; 43 44 memory { 45 device_type = "memory"; 46 reg = <0x00000000 0x10000000>; // 256MB at 0 47 }; 48 49 localbus@e0005000 { 50 #address-cells = <2>; 51 #size-cells = <1>; 52 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus"; 53 reg = <0xe0005000 0x1000>; 54 interrupts = <77 0x8>; 55 interrupt-parent = <&ipic>; 56 57 // CS0 and CS1 are swapped when 58 // booting from nand, but the 59 // addresses are the same. 60 ranges = <0x0 0x0 0xfe000000 0x00800000 61 0x1 0x0 0xe0600000 0x00008000 62 0x2 0x0 0xf0000000 0x00020000 63 0x3 0x0 0xfa000000 0x00008000>; 64 65 flash@0,0 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "cfi-flash"; 69 reg = <0x0 0x0 0x800000>; 70 bank-width = <2>; 71 device-width = <1>; 72 }; 73 74 nand@1,0 { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "fsl,mpc8379-fcm-nand", 78 "fsl,elbc-fcm-nand"; 79 reg = <0x1 0x0 0x8000>; 80 81 u-boot@0 { 82 reg = <0x0 0x100000>; 83 read-only; 84 }; 85 86 kernel@100000 { 87 reg = <0x100000 0x300000>; 88 }; 89 fs@400000 { 90 reg = <0x400000 0x1c00000>; 91 }; 92 }; 93 }; 94 95 immr@e0000000 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 device_type = "soc"; 99 compatible = "simple-bus"; 100 ranges = <0x0 0xe0000000 0x00100000>; 101 reg = <0xe0000000 0x00000200>; 102 bus-frequency = <0>; 103 104 wdt@200 { 105 device_type = "watchdog"; 106 compatible = "mpc83xx_wdt"; 107 reg = <0x200 0x100>; 108 }; 109 110 gpio1: gpio-controller@c00 { 111 #gpio-cells = <2>; 112 compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; 113 reg = <0xc00 0x100>; 114 interrupts = <74 0x8>; 115 interrupt-parent = <&ipic>; 116 gpio-controller; 117 }; 118 119 gpio2: gpio-controller@d00 { 120 #gpio-cells = <2>; 121 compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; 122 reg = <0xd00 0x100>; 123 interrupts = <75 0x8>; 124 interrupt-parent = <&ipic>; 125 gpio-controller; 126 }; 127 128 i2c@3000 { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 cell-index = <0>; 132 compatible = "fsl-i2c"; 133 reg = <0x3000 0x100>; 134 interrupts = <14 0x8>; 135 interrupt-parent = <&ipic>; 136 dfsrr; 137 138 dtt@48 { 139 compatible = "national,lm75"; 140 reg = <0x48>; 141 }; 142 143 at24@50 { 144 compatible = "at24,24c256"; 145 reg = <0x50>; 146 }; 147 148 rtc@68 { 149 compatible = "dallas,ds1339"; 150 reg = <0x68>; 151 }; 152 153 mcu_pio: mcu@a { 154 #gpio-cells = <2>; 155 compatible = "fsl,mc9s08qg8-mpc8379erdb", 156 "fsl,mcu-mpc8349emitx"; 157 reg = <0x0a>; 158 gpio-controller; 159 }; 160 }; 161 162 i2c@3100 { 163 #address-cells = <1>; 164 #size-cells = <0>; 165 cell-index = <1>; 166 compatible = "fsl-i2c"; 167 reg = <0x3100 0x100>; 168 interrupts = <15 0x8>; 169 interrupt-parent = <&ipic>; 170 dfsrr; 171 }; 172 173 spi@7000 { 174 cell-index = <0>; 175 compatible = "fsl,spi"; 176 reg = <0x7000 0x1000>; 177 interrupts = <16 0x8>; 178 interrupt-parent = <&ipic>; 179 mode = "cpu"; 180 }; 181 182 dma@82a8 { 183 #address-cells = <1>; 184 #size-cells = <1>; 185 compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; 186 reg = <0x82a8 4>; 187 ranges = <0 0x8100 0x1a8>; 188 interrupt-parent = <&ipic>; 189 interrupts = <71 8>; 190 cell-index = <0>; 191 dma-channel@0 { 192 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 193 reg = <0 0x80>; 194 cell-index = <0>; 195 interrupt-parent = <&ipic>; 196 interrupts = <71 8>; 197 }; 198 dma-channel@80 { 199 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 200 reg = <0x80 0x80>; 201 cell-index = <1>; 202 interrupt-parent = <&ipic>; 203 interrupts = <71 8>; 204 }; 205 dma-channel@100 { 206 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 207 reg = <0x100 0x80>; 208 cell-index = <2>; 209 interrupt-parent = <&ipic>; 210 interrupts = <71 8>; 211 }; 212 dma-channel@180 { 213 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 214 reg = <0x180 0x28>; 215 cell-index = <3>; 216 interrupt-parent = <&ipic>; 217 interrupts = <71 8>; 218 }; 219 }; 220 221 usb@23000 { 222 compatible = "fsl-usb2-dr"; 223 reg = <0x23000 0x1000>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 interrupt-parent = <&ipic>; 227 interrupts = <38 0x8>; 228 phy_type = "ulpi"; 229 }; 230 231 mdio@24520 { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 compatible = "fsl,gianfar-mdio"; 235 reg = <0x24520 0x20>; 236 phy2: ethernet-phy@2 { 237 interrupt-parent = <&ipic>; 238 interrupts = <17 0x8>; 239 reg = <0x2>; 240 device_type = "ethernet-phy"; 241 }; 242 tbi0: tbi-phy@11 { 243 reg = <0x11>; 244 device_type = "tbi-phy"; 245 }; 246 }; 247 248 mdio@25520 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "fsl,gianfar-tbi"; 252 reg = <0x25520 0x20>; 253 254 tbi1: tbi-phy@11 { 255 reg = <0x11>; 256 device_type = "tbi-phy"; 257 }; 258 }; 259 260 enet0: ethernet@24000 { 261 cell-index = <0>; 262 device_type = "network"; 263 model = "eTSEC"; 264 compatible = "gianfar"; 265 reg = <0x24000 0x1000>; 266 local-mac-address = [ 00 00 00 00 00 00 ]; 267 interrupts = <32 0x8 33 0x8 34 0x8>; 268 phy-connection-type = "mii"; 269 interrupt-parent = <&ipic>; 270 tbi-handle = <&tbi0>; 271 phy-handle = <&phy2>; 272 }; 273 274 enet1: ethernet@25000 { 275 cell-index = <1>; 276 device_type = "network"; 277 model = "eTSEC"; 278 compatible = "gianfar"; 279 reg = <0x25000 0x1000>; 280 local-mac-address = [ 00 00 00 00 00 00 ]; 281 interrupts = <35 0x8 36 0x8 37 0x8>; 282 phy-connection-type = "mii"; 283 interrupt-parent = <&ipic>; 284 fixed-link = <1 1 1000 0 0>; 285 tbi-handle = <&tbi1>; 286 }; 287 288 serial0: serial@4500 { 289 cell-index = <0>; 290 device_type = "serial"; 291 compatible = "ns16550"; 292 reg = <0x4500 0x100>; 293 clock-frequency = <0>; 294 interrupts = <9 0x8>; 295 interrupt-parent = <&ipic>; 296 }; 297 298 serial1: serial@4600 { 299 cell-index = <1>; 300 device_type = "serial"; 301 compatible = "ns16550"; 302 reg = <0x4600 0x100>; 303 clock-frequency = <0>; 304 interrupts = <10 0x8>; 305 interrupt-parent = <&ipic>; 306 }; 307 308 crypto@30000 { 309 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 310 "fsl,sec2.1", "fsl,sec2.0"; 311 reg = <0x30000 0x10000>; 312 interrupts = <11 0x8>; 313 interrupt-parent = <&ipic>; 314 fsl,num-channels = <4>; 315 fsl,channel-fifo-len = <24>; 316 fsl,exec-units-mask = <0x9fe>; 317 fsl,descriptor-types-mask = <0x3ab0ebf>; 318 }; 319 320 sdhci@2e000 { 321 compatible = "fsl,mpc8379-esdhc"; 322 reg = <0x2e000 0x1000>; 323 interrupts = <42 0x8>; 324 interrupt-parent = <&ipic>; 325 /* Filled in by U-Boot */ 326 clock-frequency = <0>; 327 }; 328 329 sata@18000 { 330 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 331 reg = <0x18000 0x1000>; 332 interrupts = <44 0x8>; 333 interrupt-parent = <&ipic>; 334 }; 335 336 sata@19000 { 337 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 338 reg = <0x19000 0x1000>; 339 interrupts = <45 0x8>; 340 interrupt-parent = <&ipic>; 341 }; 342 343 sata@1a000 { 344 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 345 reg = <0x1a000 0x1000>; 346 interrupts = <46 0x8>; 347 interrupt-parent = <&ipic>; 348 }; 349 350 sata@1b000 { 351 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 352 reg = <0x1b000 0x1000>; 353 interrupts = <47 0x8>; 354 interrupt-parent = <&ipic>; 355 }; 356 357 /* IPIC 358 * interrupts cell = <intr #, sense> 359 * sense values match linux IORESOURCE_IRQ_* defines: 360 * sense == 8: Level, low assertion 361 * sense == 2: Edge, high-to-low change 362 */ 363 ipic: interrupt-controller@700 { 364 compatible = "fsl,ipic"; 365 interrupt-controller; 366 #address-cells = <0>; 367 #interrupt-cells = <2>; 368 reg = <0x700 0x100>; 369 }; 370 }; 371 372 pci0: pci@e0008500 { 373 interrupt-map-mask = <0xf800 0 0 7>; 374 interrupt-map = < 375 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 376 377 /* IDSEL AD14 IRQ6 inta */ 378 0x7000 0x0 0x0 0x1 &ipic 22 0x8 379 380 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 381 0x7800 0x0 0x0 0x1 &ipic 21 0x8 382 0x7800 0x0 0x0 0x2 &ipic 22 0x8 383 0x7800 0x0 0x0 0x4 &ipic 23 0x8 384 385 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 386 0xE000 0x0 0x0 0x1 &ipic 23 0x8 387 0xE000 0x0 0x0 0x2 &ipic 21 0x8 388 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; 389 interrupt-parent = <&ipic>; 390 interrupts = <66 0x8>; 391 bus-range = <0x0 0x0>; 392 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 393 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 394 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 395 clock-frequency = <66666666>; 396 #interrupt-cells = <1>; 397 #size-cells = <2>; 398 #address-cells = <3>; 399 reg = <0xe0008500 0x100 /* internal registers */ 400 0xe0008300 0x8>; /* config space access registers */ 401 compatible = "fsl,mpc8349-pci"; 402 device_type = "pci"; 403 }; 404}; 405