1/* 2 * MPC8379E RDB Device Tree Source 3 * 4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 compatible = "fsl,mpc8379rdb"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 ethernet0 = &enet0; 21 ethernet1 = &enet1; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8379@0 { 32 device_type = "cpu"; 33 reg = <0x0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <32768>; 37 i-cache-size = <32768>; 38 timebase-frequency = <0>; 39 bus-frequency = <0>; 40 clock-frequency = <0>; 41 }; 42 }; 43 44 memory { 45 device_type = "memory"; 46 reg = <0x00000000 0x10000000>; // 256MB at 0 47 }; 48 49 localbus@e0005000 { 50 #address-cells = <2>; 51 #size-cells = <1>; 52 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus"; 53 reg = <0xe0005000 0x1000>; 54 interrupts = <77 0x8>; 55 interrupt-parent = <&ipic>; 56 57 // CS0 and CS1 are swapped when 58 // booting from nand, but the 59 // addresses are the same. 60 ranges = <0x0 0x0 0xfe000000 0x00800000 61 0x1 0x0 0xe0600000 0x00008000 62 0x2 0x0 0xf0000000 0x00020000 63 0x3 0x0 0xfa000000 0x00008000>; 64 65 flash@0,0 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "cfi-flash"; 69 reg = <0x0 0x0 0x800000>; 70 bank-width = <2>; 71 device-width = <1>; 72 }; 73 74 nand@1,0 { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "fsl,mpc8379-fcm-nand", 78 "fsl,elbc-fcm-nand"; 79 reg = <0x1 0x0 0x8000>; 80 81 u-boot@0 { 82 reg = <0x0 0x100000>; 83 read-only; 84 }; 85 86 kernel@100000 { 87 reg = <0x100000 0x300000>; 88 }; 89 fs@400000 { 90 reg = <0x400000 0x1c00000>; 91 }; 92 }; 93 }; 94 95 immr@e0000000 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 device_type = "soc"; 99 compatible = "simple-bus"; 100 ranges = <0x0 0xe0000000 0x00100000>; 101 reg = <0xe0000000 0x00000200>; 102 bus-frequency = <0>; 103 104 wdt@200 { 105 device_type = "watchdog"; 106 compatible = "mpc83xx_wdt"; 107 reg = <0x200 0x100>; 108 }; 109 110 gpio1: gpio-controller@c00 { 111 #gpio-cells = <2>; 112 compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; 113 reg = <0xc00 0x100>; 114 interrupts = <74 0x8>; 115 interrupt-parent = <&ipic>; 116 gpio-controller; 117 }; 118 119 gpio2: gpio-controller@d00 { 120 #gpio-cells = <2>; 121 compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; 122 reg = <0xd00 0x100>; 123 interrupts = <75 0x8>; 124 interrupt-parent = <&ipic>; 125 gpio-controller; 126 }; 127 128 i2c@3000 { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 cell-index = <0>; 132 compatible = "fsl-i2c"; 133 reg = <0x3000 0x100>; 134 interrupts = <14 0x8>; 135 interrupt-parent = <&ipic>; 136 dfsrr; 137 138 at24@50 { 139 compatible = "at24,24c256"; 140 reg = <0x50>; 141 }; 142 143 rtc@68 { 144 compatible = "dallas,ds1339"; 145 reg = <0x68>; 146 }; 147 148 mcu_pio: mcu@a { 149 #gpio-cells = <2>; 150 compatible = "fsl,mc9s08qg8-mpc8379erdb", 151 "fsl,mcu-mpc8349emitx"; 152 reg = <0x0a>; 153 gpio-controller; 154 }; 155 }; 156 157 i2c@3100 { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 cell-index = <1>; 161 compatible = "fsl-i2c"; 162 reg = <0x3100 0x100>; 163 interrupts = <15 0x8>; 164 interrupt-parent = <&ipic>; 165 dfsrr; 166 }; 167 168 spi@7000 { 169 cell-index = <0>; 170 compatible = "fsl,spi"; 171 reg = <0x7000 0x1000>; 172 interrupts = <16 0x8>; 173 interrupt-parent = <&ipic>; 174 mode = "cpu"; 175 }; 176 177 dma@82a8 { 178 #address-cells = <1>; 179 #size-cells = <1>; 180 compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; 181 reg = <0x82a8 4>; 182 ranges = <0 0x8100 0x1a8>; 183 interrupt-parent = <&ipic>; 184 interrupts = <71 8>; 185 cell-index = <0>; 186 dma-channel@0 { 187 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 188 reg = <0 0x80>; 189 cell-index = <0>; 190 interrupt-parent = <&ipic>; 191 interrupts = <71 8>; 192 }; 193 dma-channel@80 { 194 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 195 reg = <0x80 0x80>; 196 cell-index = <1>; 197 interrupt-parent = <&ipic>; 198 interrupts = <71 8>; 199 }; 200 dma-channel@100 { 201 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 202 reg = <0x100 0x80>; 203 cell-index = <2>; 204 interrupt-parent = <&ipic>; 205 interrupts = <71 8>; 206 }; 207 dma-channel@180 { 208 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 209 reg = <0x180 0x28>; 210 cell-index = <3>; 211 interrupt-parent = <&ipic>; 212 interrupts = <71 8>; 213 }; 214 }; 215 216 usb@23000 { 217 compatible = "fsl-usb2-dr"; 218 reg = <0x23000 0x1000>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 interrupt-parent = <&ipic>; 222 interrupts = <38 0x8>; 223 phy_type = "ulpi"; 224 }; 225 226 mdio@24520 { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 compatible = "fsl,gianfar-mdio"; 230 reg = <0x24520 0x20>; 231 phy2: ethernet-phy@2 { 232 interrupt-parent = <&ipic>; 233 interrupts = <17 0x8>; 234 reg = <0x2>; 235 device_type = "ethernet-phy"; 236 }; 237 tbi0: tbi-phy@11 { 238 reg = <0x11>; 239 device_type = "tbi-phy"; 240 }; 241 }; 242 243 mdio@25520 { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 compatible = "fsl,gianfar-tbi"; 247 reg = <0x25520 0x20>; 248 249 tbi1: tbi-phy@11 { 250 reg = <0x11>; 251 device_type = "tbi-phy"; 252 }; 253 }; 254 255 enet0: ethernet@24000 { 256 cell-index = <0>; 257 device_type = "network"; 258 model = "eTSEC"; 259 compatible = "gianfar"; 260 reg = <0x24000 0x1000>; 261 local-mac-address = [ 00 00 00 00 00 00 ]; 262 interrupts = <32 0x8 33 0x8 34 0x8>; 263 phy-connection-type = "mii"; 264 interrupt-parent = <&ipic>; 265 tbi-handle = <&tbi0>; 266 phy-handle = <&phy2>; 267 }; 268 269 enet1: ethernet@25000 { 270 cell-index = <1>; 271 device_type = "network"; 272 model = "eTSEC"; 273 compatible = "gianfar"; 274 reg = <0x25000 0x1000>; 275 local-mac-address = [ 00 00 00 00 00 00 ]; 276 interrupts = <35 0x8 36 0x8 37 0x8>; 277 phy-connection-type = "mii"; 278 interrupt-parent = <&ipic>; 279 fixed-link = <1 1 1000 0 0>; 280 tbi-handle = <&tbi1>; 281 }; 282 283 serial0: serial@4500 { 284 cell-index = <0>; 285 device_type = "serial"; 286 compatible = "ns16550"; 287 reg = <0x4500 0x100>; 288 clock-frequency = <0>; 289 interrupts = <9 0x8>; 290 interrupt-parent = <&ipic>; 291 }; 292 293 serial1: serial@4600 { 294 cell-index = <1>; 295 device_type = "serial"; 296 compatible = "ns16550"; 297 reg = <0x4600 0x100>; 298 clock-frequency = <0>; 299 interrupts = <10 0x8>; 300 interrupt-parent = <&ipic>; 301 }; 302 303 crypto@30000 { 304 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 305 "fsl,sec2.1", "fsl,sec2.0"; 306 reg = <0x30000 0x10000>; 307 interrupts = <11 0x8>; 308 interrupt-parent = <&ipic>; 309 fsl,num-channels = <4>; 310 fsl,channel-fifo-len = <24>; 311 fsl,exec-units-mask = <0x9fe>; 312 fsl,descriptor-types-mask = <0x3ab0ebf>; 313 }; 314 315 sata@18000 { 316 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 317 reg = <0x18000 0x1000>; 318 interrupts = <44 0x8>; 319 interrupt-parent = <&ipic>; 320 }; 321 322 sata@19000 { 323 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 324 reg = <0x19000 0x1000>; 325 interrupts = <45 0x8>; 326 interrupt-parent = <&ipic>; 327 }; 328 329 sata@1a000 { 330 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 331 reg = <0x1a000 0x1000>; 332 interrupts = <46 0x8>; 333 interrupt-parent = <&ipic>; 334 }; 335 336 sata@1b000 { 337 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 338 reg = <0x1b000 0x1000>; 339 interrupts = <47 0x8>; 340 interrupt-parent = <&ipic>; 341 }; 342 343 /* IPIC 344 * interrupts cell = <intr #, sense> 345 * sense values match linux IORESOURCE_IRQ_* defines: 346 * sense == 8: Level, low assertion 347 * sense == 2: Edge, high-to-low change 348 */ 349 ipic: interrupt-controller@700 { 350 compatible = "fsl,ipic"; 351 interrupt-controller; 352 #address-cells = <0>; 353 #interrupt-cells = <2>; 354 reg = <0x700 0x100>; 355 }; 356 }; 357 358 pci0: pci@e0008500 { 359 interrupt-map-mask = <0xf800 0 0 7>; 360 interrupt-map = < 361 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 362 363 /* IDSEL AD14 IRQ6 inta */ 364 0x7000 0x0 0x0 0x1 &ipic 22 0x8 365 366 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 367 0x7800 0x0 0x0 0x1 &ipic 21 0x8 368 0x7800 0x0 0x0 0x2 &ipic 22 0x8 369 0x7800 0x0 0x0 0x4 &ipic 23 0x8 370 371 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 372 0xE000 0x0 0x0 0x1 &ipic 23 0x8 373 0xE000 0x0 0x0 0x2 &ipic 21 0x8 374 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; 375 interrupt-parent = <&ipic>; 376 interrupts = <66 0x8>; 377 bus-range = <0x0 0x0>; 378 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 379 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 380 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 381 clock-frequency = <66666666>; 382 #interrupt-cells = <1>; 383 #size-cells = <2>; 384 #address-cells = <3>; 385 reg = <0xe0008500 0x100 /* internal registers */ 386 0xe0008300 0x8>; /* config space access registers */ 387 compatible = "fsl,mpc8349-pci"; 388 device_type = "pci"; 389 }; 390}; 391