1/*
2 * MPC8378E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	compatible = "fsl,mpc8378rdb";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet0;
21		ethernet1 = &enet1;
22		serial0 = &serial0;
23		serial1 = &serial1;
24		pci0 = &pci0;
25		pci1 = &pci1;
26		pci2 = &pci2;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		PowerPC,8378@0 {
34			device_type = "cpu";
35			reg = <0x0>;
36			d-cache-line-size = <32>;
37			i-cache-line-size = <32>;
38			d-cache-size = <32768>;
39			i-cache-size = <32768>;
40			timebase-frequency = <0>;
41			bus-frequency = <0>;
42			clock-frequency = <0>;
43		};
44	};
45
46	memory {
47		device_type = "memory";
48		reg = <0x00000000 0x10000000>;	// 256MB at 0
49	};
50
51	localbus@e0005000 {
52		#address-cells = <2>;
53		#size-cells = <1>;
54		compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
55		reg = <0xe0005000 0x1000>;
56		interrupts = <77 0x8>;
57		interrupt-parent = <&ipic>;
58
59		// CS0 and CS1 are swapped when
60		// booting from nand, but the
61		// addresses are the same.
62		ranges = <0x0 0x0 0xfe000000 0x00800000
63		          0x1 0x0 0xe0600000 0x00008000
64		          0x2 0x0 0xf0000000 0x00020000
65		          0x3 0x0 0xfa000000 0x00008000>;
66
67		flash@0,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70			compatible = "cfi-flash";
71			reg = <0x0 0x0 0x800000>;
72			bank-width = <2>;
73			device-width = <1>;
74		};
75
76		nand@1,0 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "fsl,mpc8378-fcm-nand",
80			             "fsl,elbc-fcm-nand";
81			reg = <0x1 0x0 0x8000>;
82
83			u-boot@0 {
84				reg = <0x0 0x100000>;
85				read-only;
86			};
87
88			kernel@100000 {
89				reg = <0x100000 0x300000>;
90			};
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	immr@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "simple-bus";
102		ranges = <0x0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		i2c@3000 {
113			#address-cells = <1>;
114			#size-cells = <0>;
115			cell-index = <0>;
116			compatible = "fsl-i2c";
117			reg = <0x3000 0x100>;
118			interrupts = <14 0x8>;
119			interrupt-parent = <&ipic>;
120			dfsrr;
121
122			at24@50 {
123				compatible = "at24,24c256";
124				reg = <0x50>;
125			};
126
127			rtc@68 {
128				compatible = "dallas,ds1339";
129				reg = <0x68>;
130			};
131
132			mcu_pio: mcu@a {
133				#gpio-cells = <2>;
134				compatible = "fsl,mc9s08qg8-mpc8378erdb",
135					     "fsl,mcu-mpc8349emitx";
136				reg = <0x0a>;
137				gpio-controller;
138			};
139		};
140
141		i2c@3100 {
142			#address-cells = <1>;
143			#size-cells = <0>;
144			cell-index = <1>;
145			compatible = "fsl-i2c";
146			reg = <0x3100 0x100>;
147			interrupts = <15 0x8>;
148			interrupt-parent = <&ipic>;
149			dfsrr;
150		};
151
152		spi@7000 {
153			cell-index = <0>;
154			compatible = "fsl,spi";
155			reg = <0x7000 0x1000>;
156			interrupts = <16 0x8>;
157			interrupt-parent = <&ipic>;
158			mode = "cpu";
159		};
160
161		dma@82a8 {
162			#address-cells = <1>;
163			#size-cells = <1>;
164			compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
165			reg = <0x82a8 4>;
166			ranges = <0 0x8100 0x1a8>;
167			interrupt-parent = <&ipic>;
168			interrupts = <71 8>;
169			cell-index = <0>;
170			dma-channel@0 {
171				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
172				reg = <0 0x80>;
173				cell-index = <0>;
174				interrupt-parent = <&ipic>;
175				interrupts = <71 8>;
176			};
177			dma-channel@80 {
178				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
179				reg = <0x80 0x80>;
180				cell-index = <1>;
181				interrupt-parent = <&ipic>;
182				interrupts = <71 8>;
183			};
184			dma-channel@100 {
185				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
186				reg = <0x100 0x80>;
187				cell-index = <2>;
188				interrupt-parent = <&ipic>;
189				interrupts = <71 8>;
190			};
191			dma-channel@180 {
192				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
193				reg = <0x180 0x28>;
194				cell-index = <3>;
195				interrupt-parent = <&ipic>;
196				interrupts = <71 8>;
197			};
198		};
199
200		usb@23000 {
201			compatible = "fsl-usb2-dr";
202			reg = <0x23000 0x1000>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205			interrupt-parent = <&ipic>;
206			interrupts = <38 0x8>;
207			phy_type = "ulpi";
208		};
209
210		mdio@24520 {
211			#address-cells = <1>;
212			#size-cells = <0>;
213			compatible = "fsl,gianfar-mdio";
214			reg = <0x24520 0x20>;
215			phy2: ethernet-phy@2 {
216				interrupt-parent = <&ipic>;
217				interrupts = <17 0x8>;
218				reg = <0x2>;
219				device_type = "ethernet-phy";
220			};
221			tbi0: tbi-phy@11 {
222				reg = <0x11>;
223				device_type = "tbi-phy";
224			};
225		};
226
227		mdio@25520 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			compatible = "fsl,gianfar-tbi";
231			reg = <0x25520 0x20>;
232
233			tbi1: tbi-phy@11 {
234				reg = <0x11>;
235				device_type = "tbi-phy";
236			};
237		};
238
239
240		enet0: ethernet@24000 {
241			cell-index = <0>;
242			device_type = "network";
243			model = "eTSEC";
244			compatible = "gianfar";
245			reg = <0x24000 0x1000>;
246			local-mac-address = [ 00 00 00 00 00 00 ];
247			interrupts = <32 0x8 33 0x8 34 0x8>;
248			phy-connection-type = "mii";
249			interrupt-parent = <&ipic>;
250			phy-handle = <&phy2>;
251		};
252
253		enet1: ethernet@25000 {
254			cell-index = <1>;
255			device_type = "network";
256			model = "eTSEC";
257			compatible = "gianfar";
258			reg = <0x25000 0x1000>;
259			local-mac-address = [ 00 00 00 00 00 00 ];
260			interrupts = <35 0x8 36 0x8 37 0x8>;
261			phy-connection-type = "mii";
262			interrupt-parent = <&ipic>;
263			fixed-link = <1 1 1000 0 0>;
264		};
265
266		serial0: serial@4500 {
267			cell-index = <0>;
268			device_type = "serial";
269			compatible = "ns16550";
270			reg = <0x4500 0x100>;
271			clock-frequency = <0>;
272			interrupts = <9 0x8>;
273			interrupt-parent = <&ipic>;
274		};
275
276		serial1: serial@4600 {
277			cell-index = <1>;
278			device_type = "serial";
279			compatible = "ns16550";
280			reg = <0x4600 0x100>;
281			clock-frequency = <0>;
282			interrupts = <10 0x8>;
283			interrupt-parent = <&ipic>;
284		};
285
286		crypto@30000 {
287			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
288				     "fsl,sec2.1", "fsl,sec2.0";
289			reg = <0x30000 0x10000>;
290			interrupts = <11 0x8>;
291			interrupt-parent = <&ipic>;
292			fsl,num-channels = <4>;
293			fsl,channel-fifo-len = <24>;
294			fsl,exec-units-mask = <0x9fe>;
295			fsl,descriptor-types-mask = <0x3ab0ebf>;
296		};
297
298		/* IPIC
299		 * interrupts cell = <intr #, sense>
300		 * sense values match linux IORESOURCE_IRQ_* defines:
301		 * sense == 8: Level, low assertion
302		 * sense == 2: Edge, high-to-low change
303		 */
304		ipic: interrupt-controller@700 {
305			compatible = "fsl,ipic";
306			interrupt-controller;
307			#address-cells = <0>;
308			#interrupt-cells = <2>;
309			reg = <0x700 0x100>;
310		};
311	};
312
313	pci0: pci@e0008500 {
314		interrupt-map-mask = <0xf800 0 0 7>;
315		interrupt-map = <
316				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
317
318				/* IDSEL AD14 IRQ6 inta */
319				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
320
321				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
322				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
323				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
324				 0x7800 0x0 0x0 0x4 &ipic 23 0x8
325
326				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
327				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
328				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
329				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
330		interrupt-parent = <&ipic>;
331		interrupts = <66 0x8>;
332		bus-range = <0 0>;
333		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
334		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
335		          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
336		clock-frequency = <66666666>;
337		#interrupt-cells = <1>;
338		#size-cells = <2>;
339		#address-cells = <3>;
340		reg = <0xe0008500 0x100		/* internal registers */
341		       0xe0008300 0x8>;		/* config space access registers */
342		compatible = "fsl,mpc8349-pci";
343		device_type = "pci";
344	};
345
346	pci1: pcie@e0009000 {
347		#address-cells = <3>;
348		#size-cells = <2>;
349		#interrupt-cells = <1>;
350		device_type = "pci";
351		compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
352		reg = <0xe0009000 0x00001000>;
353		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
354		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
355		bus-range = <0 255>;
356		interrupt-map-mask = <0xf800 0 0 7>;
357		interrupt-map = <0 0 0 1 &ipic 1 8
358				 0 0 0 2 &ipic 1 8
359				 0 0 0 3 &ipic 1 8
360				 0 0 0 4 &ipic 1 8>;
361		clock-frequency = <0>;
362
363		pcie@0 {
364			#address-cells = <3>;
365			#size-cells = <2>;
366			device_type = "pci";
367			reg = <0 0 0 0 0>;
368			ranges = <0x02000000 0 0xa8000000
369				  0x02000000 0 0xa8000000
370				  0 0x10000000
371				  0x01000000 0 0x00000000
372				  0x01000000 0 0x00000000
373				  0 0x00800000>;
374		};
375	};
376
377	pci2: pcie@e000a000 {
378		#address-cells = <3>;
379		#size-cells = <2>;
380		#interrupt-cells = <1>;
381		device_type = "pci";
382		compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
383		reg = <0xe000a000 0x00001000>;
384		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
385			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
386		bus-range = <0 255>;
387		interrupt-map-mask = <0xf800 0 0 7>;
388		interrupt-map = <0 0 0 1 &ipic 2 8
389				 0 0 0 2 &ipic 2 8
390				 0 0 0 3 &ipic 2 8
391				 0 0 0 4 &ipic 2 8>;
392		clock-frequency = <0>;
393
394		pcie@0 {
395			#address-cells = <3>;
396			#size-cells = <2>;
397			device_type = "pci";
398			reg = <0 0 0 0 0>;
399			ranges = <0x02000000 0 0xc8000000
400				  0x02000000 0 0xc8000000
401				  0 0x10000000
402				  0x01000000 0 0x00000000
403				  0x01000000 0 0x00000000
404				  0 0x00800000>;
405		};
406	};
407};
408